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include
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asm-ppc
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mpc83xx.h

mpc83xx.h 3.9 KB
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  1. /*
    2. 

  2.  * include/asm-ppc/mpc83xx.h
    3. 

  3.  *
    4. 

  4.  * MPC83xx definitions
    5. 

  5.  *
    6. 

  6.  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
    7. 

  7.  *
    8. 

  8.  * Copyright 2005 Freescale Semiconductor, Inc
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute  it and/or modify it
    11. 

  11.  * under  the terms of  the GNU General  Public License as published by the
    12. 

  12.  * Free Software Foundation;  either version 2 of the  License, or (at your
    13. 

  13.  * option) any later version.
    14. 

  14.  */
    15. 

  15. 

  16. #ifdef __KERNEL__
    17. 

  17. #ifndef __ASM_MPC83xx_H__
    18. 

  18. #define __ASM_MPC83xx_H__
    19. 

  19. 

  20. #include <asm/mmu.h>
    21. 

  21. 

  22. #ifdef CONFIG_83xx
    23. 

  23. 

  24. #ifdef CONFIG_MPC834x_SYS
    25. 

  25. #include <platforms/83xx/mpc834x_sys.h>
    26. 

  26. #endif
    27. 

  27. 

  28. #define _IO_BASE        isa_io_base
    29. 

  29. #define _ISA_MEM_BASE   isa_mem_base
    30. 

  30. #ifdef CONFIG_PCI
    31. 

  31. #define PCI_DRAM_OFFSET pci_dram_offset
    32. 

  32. #else
    33. 

  33. #define PCI_DRAM_OFFSET 0
    34. 

  34. #endif
    35. 

  35. 

  36. /*
    37. 

  37.  * The "residual" board information structure the boot loader passes
    38. 

  38.  * into the kernel.
    39. 

  39.  */
    40. 

  40. extern unsigned char __res[];
    41. 

  41. 

  42. /* Internal IRQs on MPC83xx OpenPIC */
    43. 

  43. /* Not all of these exist on all MPC83xx implementations */
    44. 

  44. 

  45. #ifndef MPC83xx_IPIC_IRQ_OFFSET
    46. 

  46. #define MPC83xx_IPIC_IRQ_OFFSET	0
    47. 

  47. #endif
    48. 

  48. 

  49. #define NR_IPIC_INTS 128
    50. 

  50. 

  51. #define MPC83xx_IRQ_UART1	( 9 + MPC83xx_IPIC_IRQ_OFFSET)
    52. 

  52. #define MPC83xx_IRQ_UART2	(10 + MPC83xx_IPIC_IRQ_OFFSET)
    53. 

  53. #define MPC83xx_IRQ_SEC2	(11 + MPC83xx_IPIC_IRQ_OFFSET)
    54. 

  54. #define MPC83xx_IRQ_IIC1	(14 + MPC83xx_IPIC_IRQ_OFFSET)
    55. 

  55. #define MPC83xx_IRQ_IIC2	(15 + MPC83xx_IPIC_IRQ_OFFSET)
    56. 

  56. #define MPC83xx_IRQ_SPI		(16 + MPC83xx_IPIC_IRQ_OFFSET)
    57. 

  57. #define MPC83xx_IRQ_EXT1	(17 + MPC83xx_IPIC_IRQ_OFFSET)
    58. 

  58. #define MPC83xx_IRQ_EXT2	(18 + MPC83xx_IPIC_IRQ_OFFSET)
    59. 

  59. #define MPC83xx_IRQ_EXT3	(19 + MPC83xx_IPIC_IRQ_OFFSET)
    60. 

  60. #define MPC83xx_IRQ_EXT4	(20 + MPC83xx_IPIC_IRQ_OFFSET)
    61. 

  61. #define MPC83xx_IRQ_EXT5	(21 + MPC83xx_IPIC_IRQ_OFFSET)
    62. 

  62. #define MPC83xx_IRQ_EXT6	(22 + MPC83xx_IPIC_IRQ_OFFSET)
    63. 

  63. #define MPC83xx_IRQ_EXT7	(23 + MPC83xx_IPIC_IRQ_OFFSET)
    64. 

  64. #define MPC83xx_IRQ_TSEC1_TX	(32 + MPC83xx_IPIC_IRQ_OFFSET)
    65. 

  65. #define MPC83xx_IRQ_TSEC1_RX	(33 + MPC83xx_IPIC_IRQ_OFFSET)
    66. 

  66. #define MPC83xx_IRQ_TSEC1_ERROR	(34 + MPC83xx_IPIC_IRQ_OFFSET)
    67. 

  67. #define MPC83xx_IRQ_TSEC2_TX	(35 + MPC83xx_IPIC_IRQ_OFFSET)
    68. 

  68. #define MPC83xx_IRQ_TSEC2_RX	(36 + MPC83xx_IPIC_IRQ_OFFSET)
    69. 

  69. #define MPC83xx_IRQ_TSEC2_ERROR	(37 + MPC83xx_IPIC_IRQ_OFFSET)
    70. 

  70. #define MPC83xx_IRQ_USB2_DR	(38 + MPC83xx_IPIC_IRQ_OFFSET)
    71. 

  71. #define MPC83xx_IRQ_USB2_MPH	(39 + MPC83xx_IPIC_IRQ_OFFSET)
    72. 

  72. #define MPC83xx_IRQ_EXT0	(48 + MPC83xx_IPIC_IRQ_OFFSET)
    73. 

  73. #define MPC83xx_IRQ_RTC_SEC	(64 + MPC83xx_IPIC_IRQ_OFFSET)
    74. 

  74. #define MPC83xx_IRQ_PIT		(65 + MPC83xx_IPIC_IRQ_OFFSET)
    75. 

  75. #define MPC83xx_IRQ_PCI1	(66 + MPC83xx_IPIC_IRQ_OFFSET)
    76. 

  76. #define MPC83xx_IRQ_PCI2	(67 + MPC83xx_IPIC_IRQ_OFFSET)
    77. 

  77. #define MPC83xx_IRQ_RTC_ALR	(68 + MPC83xx_IPIC_IRQ_OFFSET)
    78. 

  78. #define MPC83xx_IRQ_MU		(69 + MPC83xx_IPIC_IRQ_OFFSET)
    79. 

  79. #define MPC83xx_IRQ_SBA		(70 + MPC83xx_IPIC_IRQ_OFFSET)
    80. 

  80. #define MPC83xx_IRQ_DMA		(71 + MPC83xx_IPIC_IRQ_OFFSET)
    81. 

  81. #define MPC83xx_IRQ_GTM4	(72 + MPC83xx_IPIC_IRQ_OFFSET)
    82. 

  82. #define MPC83xx_IRQ_GTM8	(73 + MPC83xx_IPIC_IRQ_OFFSET)
    83. 

  83. #define MPC83xx_IRQ_GPIO1	(74 + MPC83xx_IPIC_IRQ_OFFSET)
    84. 

  84. #define MPC83xx_IRQ_GPIO2	(75 + MPC83xx_IPIC_IRQ_OFFSET)
    85. 

  85. #define MPC83xx_IRQ_DDR		(76 + MPC83xx_IPIC_IRQ_OFFSET)
    86. 

  86. #define MPC83xx_IRQ_LBC		(77 + MPC83xx_IPIC_IRQ_OFFSET)
    87. 

  87. #define MPC83xx_IRQ_GTM2	(78 + MPC83xx_IPIC_IRQ_OFFSET)
    88. 

  88. #define MPC83xx_IRQ_GTM6	(79 + MPC83xx_IPIC_IRQ_OFFSET)
    89. 

  89. #define MPC83xx_IRQ_PMC		(80 + MPC83xx_IPIC_IRQ_OFFSET)
    90. 

  90. #define MPC83xx_IRQ_GTM3	(84 + MPC83xx_IPIC_IRQ_OFFSET)
    91. 

  91. #define MPC83xx_IRQ_GTM7	(85 + MPC83xx_IPIC_IRQ_OFFSET)
    92. 

  92. #define MPC83xx_IRQ_GTM1	(90 + MPC83xx_IPIC_IRQ_OFFSET)
    93. 

  93. #define MPC83xx_IRQ_GTM5	(91 + MPC83xx_IPIC_IRQ_OFFSET)
    94. 

  94. 

  95. #define MPC83xx_CCSRBAR_SIZE	(1024*1024)
    96. 

  96. 

  97. /* Let modules/drivers get at immrbar (physical) */
    98. 

  98. extern phys_addr_t immrbar;
    99. 

  99. 

  100. enum ppc_sys_devices {
    101. 

  101. 	MPC83xx_TSEC1,
    102. 

  102. 	MPC83xx_TSEC2,
    103. 

  103. 	MPC83xx_IIC1,
    104. 

  104. 	MPC83xx_IIC2,
    105. 

  105. 	MPC83xx_DUART,
    106. 

  106. 	MPC83xx_SEC2,
    107. 

  107. 	MPC83xx_USB2_DR,
    108. 

  108. 	MPC83xx_USB2_MPH,
    109. 

  109. 	MPC83xx_MDIO,
    110. 

  110. 	NUM_PPC_SYS_DEVS,
    111. 

  111. };
    112. 

  112. 

  113. #endif /* CONFIG_83xx */
    114. 

  114. #endif /* __ASM_MPC83xx_H__ */
    115. 

  115. #endif /* __KERNEL__ */
    116.