spi.h 2.4 KB

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  1. /*
  2. * linux/include/asm-mips/tx4938/spi.h
  3. * Definitions for TX4937/TX4938 SPI
  4. *
  5. * Copyright (C) 2000-2001 Toshiba Corporation
  6. *
  7. * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
  8. * terms of the GNU General Public License version 2. This program is
  9. * licensed "as is" without any warranty of any kind, whether express
  10. * or implied.
  11. *
  12. * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
  13. */
  14. #ifndef __ASM_TX_BOARDS_TX4938_SPI_H
  15. #define __ASM_TX_BOARDS_TX4938_SPI_H
  16. /* SPI */
  17. struct spi_dev_desc {
  18. unsigned int baud;
  19. unsigned short tcss, tcsh, tcsr; /* CS setup/hold/recovery time */
  20. unsigned int byteorder:1; /* 0:LSB-First, 1:MSB-First */
  21. unsigned int polarity:1; /* 0:High-Active */
  22. unsigned int phase:1; /* 0:Sample-Then-Shift */
  23. };
  24. extern void txx9_spi_init(unsigned long base, int (*cs_func)(int chipid, int on)) __init;
  25. extern void txx9_spi_irqinit(int irc_irq) __init;
  26. extern int txx9_spi_io(int chipid, struct spi_dev_desc *desc,
  27. unsigned char **inbufs, unsigned int *incounts,
  28. unsigned char **outbufs, unsigned int *outcounts,
  29. int cansleep);
  30. extern int spi_eeprom_write_enable(int chipid, int enable);
  31. extern int spi_eeprom_read_status(int chipid);
  32. extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
  33. extern int spi_eeprom_write(int chipid, int address, unsigned char *buf, int len);
  34. extern void spi_eeprom_proc_create(struct proc_dir_entry *dir, int chipid) __init;
  35. #define TXX9_IMCLK (txx9_gbus_clock / 2)
  36. /*
  37. * SPI
  38. */
  39. /* SPMCR : SPI Master Control */
  40. #define TXx9_SPMCR_OPMODE 0xc0
  41. #define TXx9_SPMCR_CONFIG 0x40
  42. #define TXx9_SPMCR_ACTIVE 0x80
  43. #define TXx9_SPMCR_SPSTP 0x02
  44. #define TXx9_SPMCR_BCLR 0x01
  45. /* SPCR0 : SPI Status */
  46. #define TXx9_SPCR0_TXIFL_MASK 0xc000
  47. #define TXx9_SPCR0_RXIFL_MASK 0x3000
  48. #define TXx9_SPCR0_SIDIE 0x0800
  49. #define TXx9_SPCR0_SOEIE 0x0400
  50. #define TXx9_SPCR0_RBSIE 0x0200
  51. #define TXx9_SPCR0_TBSIE 0x0100
  52. #define TXx9_SPCR0_IFSPSE 0x0010
  53. #define TXx9_SPCR0_SBOS 0x0004
  54. #define TXx9_SPCR0_SPHA 0x0002
  55. #define TXx9_SPCR0_SPOL 0x0001
  56. /* SPSR : SPI Status */
  57. #define TXx9_SPSR_TBSI 0x8000
  58. #define TXx9_SPSR_RBSI 0x4000
  59. #define TXx9_SPSR_TBS_MASK 0x3800
  60. #define TXx9_SPSR_RBS_MASK 0x0700
  61. #define TXx9_SPSR_SPOE 0x0080
  62. #define TXx9_SPSR_IFSD 0x0008
  63. #define TXx9_SPSR_SIDLE 0x0004
  64. #define TXx9_SPSR_STRDY 0x0002
  65. #define TXx9_SPSR_SRRDY 0x0001
  66. #endif /* __ASM_TX_BOARDS_TX4938_SPI_H */