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linux-vybrid_pu...
/
include
/
asm-mips
/
asmmacro.h

asmmacro.h 1.8 KB
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  1. /*
    2. 

  2.  * This file is subject to the terms and conditions of the GNU General Public
    3. 

  3.  * License.  See the file "COPYING" in the main directory of this archive
    4. 

  4.  * for more details.
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 2003 Ralf Baechle
    7. 

  7.  */
    8. 

  8. #ifndef _ASM_ASMMACRO_H
    9. 

  9. #define _ASM_ASMMACRO_H
    10. 

  10. 

  11. #include <asm/hazards.h>
    12. 

  12. 

  13. #ifdef CONFIG_32BIT
    14. 

  14. #include <asm/asmmacro-32.h>
    15. 

  15. #endif
    16. 

  16. #ifdef CONFIG_64BIT
    17. 

  17. #include <asm/asmmacro-64.h>
    18. 

  18. #endif
    19. 

  19. #ifdef CONFIG_MIPS_MT_SMTC
    20. 

  20. #include <asm/mipsmtregs.h>
    21. 

  21. #endif
    22. 

  22. 

  23. #ifdef CONFIG_MIPS_MT_SMTC
    24. 

  24. 	.macro	local_irq_enable reg=t0
    25. 

  25. 	mfc0	\reg, CP0_TCSTATUS
    26. 

  26. 	ori	\reg, \reg, TCSTATUS_IXMT
    27. 

  27. 	xori	\reg, \reg, TCSTATUS_IXMT
    28. 

  28. 	mtc0	\reg, CP0_TCSTATUS
    29. 

  29. 	_ehb
    30. 

  30. 	.endm
    31. 

  31. 

  32. 	.macro	local_irq_disable reg=t0
    33. 

  33. 	mfc0	\reg, CP0_TCSTATUS
    34. 

  34. 	ori	\reg, \reg, TCSTATUS_IXMT
    35. 

  35. 	mtc0	\reg, CP0_TCSTATUS
    36. 

  36. 	_ehb
    37. 

  37. 	.endm
    38. 

  38. #else
    39. 

  39. 	.macro	local_irq_enable reg=t0
    40. 

  40. 	mfc0	\reg, CP0_STATUS
    41. 

  41. 	ori	\reg, \reg, 1
    42. 

  42. 	mtc0	\reg, CP0_STATUS
    43. 

  43. 	irq_enable_hazard
    44. 

  44. 	.endm
    45. 

  45. 

  46. 	.macro	local_irq_disable reg=t0
    47. 

  47. 	mfc0	\reg, CP0_STATUS
    48. 

  48. 	ori	\reg, \reg, 1
    49. 

  49. 	xori	\reg, \reg, 1
    50. 

  50. 	mtc0	\reg, CP0_STATUS
    51. 

  51. 	irq_disable_hazard
    52. 

  52. 	.endm
    53. 

  53. #endif /* CONFIG_MIPS_MT_SMTC */
    54. 

  54. 

  55. #ifdef CONFIG_CPU_SB1
    56. 

  56. 	.macro	fpu_enable_hazard
    57. 

  57. 	.set	push
    58. 

  58. 	.set	noreorder
    59. 

  59. 	.set	mips2
    60. 

  60. 	SSNOP
    61. 

  61. 	bnezl	$0, .+4
    62. 

  62. 	 SSNOP
    63. 

  63. 	.set	pop
    64. 

  64. 	.endm
    65. 

  65. #else
    66. 

  66. 	.macro	fpu_enable_hazard
    67. 

  67. 	.endm
    68. 

  68. #endif
    69. 

  69. 

  70. /*
    71. 

  71.  * Temporary until all gas have MT ASE support
    72. 

  72.  */
    73. 

  73. 	.macro	DMT	reg=0
    74. 

  74. 	.word	(0x41600bc1 | (\reg << 16))
    75. 

  75. 	.endm
    76. 

  76. 

  77. 	.macro	EMT	reg=0
    78. 

  78. 	.word	(0x41600be1 | (\reg << 16))
    79. 

  79. 	.endm
    80. 

  80. 

  81. 	.macro	DVPE	reg=0
    82. 

  82. 	.word	(0x41600001 | (\reg << 16))
    83. 

  83. 	.endm
    84. 

  84. 

  85. 	.macro	EVPE	reg=0
    86. 

  86. 	.word	(0x41600021 | (\reg << 16))
    87. 

  87. 	.endm
    88. 

  88. 

  89. 	.macro	MFTR	rt=0, rd=0, u=0, sel=0
    90. 

  90. 	 .word	(0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel))
    91. 

  91. 	.endm
    92. 

  92. 

  93. 	.macro	MTTR	rt=0, rd=0, u=0, sel=0
    94. 

  94. 	 .word	(0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel))
    95. 

  95. 	.endm
    96. 

  96. 

  97. #endif /* _ASM_ASMMACRO_H */
    98.