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include
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asm-m68knommu
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m520xsim.h

m520xsim.h 2.1 KB
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  1. /****************************************************************************/
    2. 

  2. 

  3. /*
    4. 

  4.  *  m520xsim.h -- ColdFire 5207/5208 System Integration Module support.
    5. 

  5.  *
    6. 

  6.  *  (C) Copyright 2005, Intec Automation (mike@steroidmicros.com)
    7. 

  7.  */
    8. 

  8. 

  9. /****************************************************************************/
    10. 

  10. #ifndef m520xsim_h
    11. 

  11. #define m520xsim_h
    12. 

  12. /****************************************************************************/
    13. 

  13. 

  14. 

  15. /*
    16. 

  16.  *  Define the 5282 SIM register set addresses.
    17. 

  17.  */
    18. 

  18. #define MCFICM_INTC0        0x48000     /* Base for Interrupt Ctrl 0 */
    19. 

  19. #define MCFINTC_IPRH        0x00        /* Interrupt pending 32-63 */
    20. 

  20. #define MCFINTC_IPRL        0x04        /* Interrupt pending 1-31 */
    21. 

  21. #define MCFINTC_IMRH        0x08        /* Interrupt mask 32-63 */
    22. 

  22. #define MCFINTC_IMRL        0x0c        /* Interrupt mask 1-31 */
    23. 

  23. #define MCFINTC_INTFRCH     0x10        /* Interrupt force 32-63 */
    24. 

  24. #define MCFINTC_INTFRCL     0x14        /* Interrupt force 1-31 */
    25. 

  25. #define MCFINTC_ICR0        0x40        /* Base ICR register */
    26. 

  26. 

  27. #define MCFINT_VECBASE      64
    28. 

  28. #define MCFINT_UART0        26          /* Interrupt number for UART0 */
    29. 

  29. #define MCFINT_UART1        27          /* Interrupt number for UART1 */
    30. 

  30. #define MCFINT_UART2        28          /* Interrupt number for UART2 */
    31. 

  31. #define MCFINT_QSPI         31          /* Interrupt number for QSPI */
    32. 

  32. #define MCFINT_PIT1         4           /* Interrupt number for PIT1 (PIT0 in processor) */
    33. 

  33. 

  34. 

  35. #define MCF_GPIO_PAR_UART                   (0xA4036)
    36. 

  36. #define MCF_GPIO_PAR_FECI2C                 (0xA4033)
    37. 

  37. #define MCF_GPIO_PAR_FEC                    (0xA4038)
    38. 

  38. 

  39. #define MCF_GPIO_PAR_UART_PAR_URXD0         (0x0001)
    40. 

  40. #define MCF_GPIO_PAR_UART_PAR_UTXD0         (0x0002)
    41. 

  41. 

  42. #define MCF_GPIO_PAR_UART_PAR_URXD1         (0x0040)
    43. 

  43. #define MCF_GPIO_PAR_UART_PAR_UTXD1         (0x0080)
    44. 

  44. 

  45. #define MCF_GPIO_PAR_FECI2C_PAR_SDA_URXD2   (0x02)
    46. 

  46. #define MCF_GPIO_PAR_FECI2C_PAR_SCL_UTXD2   (0x04)
    47. 

  47. 

  48. #define ICR_INTRCONF		0x05
    49. 

  49. #define MCFPIT_IMR		MCFINTC_IMRL
    50. 

  50. #define MCFPIT_IMR_IBIT	(1 << MCFINT_PIT1)
    51. 

  51. 

  52. /****************************************************************************/
    53. 

  53. #endif  /* m520xsim_h */
    54.