dma.h 5.5 KB

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  1. #ifndef __ASM_ARM_DMA_H
  2. #define __ASM_ARM_DMA_H
  3. typedef unsigned int dmach_t;
  4. #include <linux/spinlock.h>
  5. #include <asm/system.h>
  6. #include <asm/memory.h>
  7. #include <asm/scatterlist.h>
  8. // FIXME - do we really need this? arm26 cant do 'proper' DMA
  9. typedef struct dma_struct dma_t;
  10. typedef unsigned int dmamode_t;
  11. struct dma_ops {
  12. int (*request)(dmach_t, dma_t *); /* optional */
  13. void (*free)(dmach_t, dma_t *); /* optional */
  14. void (*enable)(dmach_t, dma_t *); /* mandatory */
  15. void (*disable)(dmach_t, dma_t *); /* mandatory */
  16. int (*residue)(dmach_t, dma_t *); /* optional */
  17. int (*setspeed)(dmach_t, dma_t *, int); /* optional */
  18. char *type;
  19. };
  20. struct dma_struct {
  21. struct scatterlist buf; /* single DMA */
  22. int sgcount; /* number of DMA SG */
  23. struct scatterlist *sg; /* DMA Scatter-Gather List */
  24. unsigned int active:1; /* Transfer active */
  25. unsigned int invalid:1; /* Address/Count changed */
  26. unsigned int using_sg:1; /* using scatter list? */
  27. dmamode_t dma_mode; /* DMA mode */
  28. int speed; /* DMA speed */
  29. unsigned int lock; /* Device is allocated */
  30. const char *device_id; /* Device name */
  31. unsigned int dma_base; /* Controller base address */
  32. int dma_irq; /* Controller IRQ */
  33. int state; /* Controller state */
  34. struct scatterlist cur_sg; /* Current controller buffer */
  35. struct dma_ops *d_ops;
  36. };
  37. /* Prototype: void arch_dma_init(dma)
  38. * Purpose : Initialise architecture specific DMA
  39. * Params : dma - pointer to array of DMA structures
  40. */
  41. extern void arch_dma_init(dma_t *dma);
  42. extern void isa_init_dma(dma_t *dma);
  43. #define MAX_DMA_ADDRESS 0x03000000
  44. #define MAX_DMA_CHANNELS 3
  45. /* ARC */
  46. #define DMA_VIRTUAL_FLOPPY0 0
  47. #define DMA_VIRTUAL_FLOPPY1 1
  48. #define DMA_VIRTUAL_SOUND 2
  49. /* A5K */
  50. #define DMA_FLOPPY 0
  51. /*
  52. * DMA modes
  53. */
  54. #define DMA_MODE_MASK 3
  55. #define DMA_MODE_READ 0
  56. #define DMA_MODE_WRITE 1
  57. #define DMA_MODE_CASCADE 2
  58. #define DMA_AUTOINIT 4
  59. extern spinlock_t dma_spin_lock;
  60. static inline unsigned long claim_dma_lock(void)
  61. {
  62. unsigned long flags;
  63. spin_lock_irqsave(&dma_spin_lock, flags);
  64. return flags;
  65. }
  66. static inline void release_dma_lock(unsigned long flags)
  67. {
  68. spin_unlock_irqrestore(&dma_spin_lock, flags);
  69. }
  70. /* Clear the 'DMA Pointer Flip Flop'.
  71. * Write 0 for LSB/MSB, 1 for MSB/LSB access.
  72. */
  73. #define clear_dma_ff(channel)
  74. /* Set only the page register bits of the transfer address.
  75. *
  76. * NOTE: This is an architecture specific function, and should
  77. * be hidden from the drivers
  78. */
  79. extern void set_dma_page(dmach_t channel, char pagenr);
  80. /* Request a DMA channel
  81. *
  82. * Some architectures may need to do allocate an interrupt
  83. */
  84. extern int request_dma(dmach_t channel, const char * device_id);
  85. /* Free a DMA channel
  86. *
  87. * Some architectures may need to do free an interrupt
  88. */
  89. extern void free_dma(dmach_t channel);
  90. /* Enable DMA for this channel
  91. *
  92. * On some architectures, this may have other side effects like
  93. * enabling an interrupt and setting the DMA registers.
  94. */
  95. extern void enable_dma(dmach_t channel);
  96. /* Disable DMA for this channel
  97. *
  98. * On some architectures, this may have other side effects like
  99. * disabling an interrupt or whatever.
  100. */
  101. extern void disable_dma(dmach_t channel);
  102. /* Test whether the specified channel has an active DMA transfer
  103. */
  104. extern int dma_channel_active(dmach_t channel);
  105. /* Set the DMA scatter gather list for this channel
  106. *
  107. * This should not be called if a DMA channel is enabled,
  108. * especially since some DMA architectures don't update the
  109. * DMA address immediately, but defer it to the enable_dma().
  110. */
  111. extern void set_dma_sg(dmach_t channel, struct scatterlist *sg, int nr_sg);
  112. /* Set the DMA address for this channel
  113. *
  114. * This should not be called if a DMA channel is enabled,
  115. * especially since some DMA architectures don't update the
  116. * DMA address immediately, but defer it to the enable_dma().
  117. */
  118. extern void set_dma_addr(dmach_t channel, unsigned long physaddr);
  119. /* Set the DMA byte count for this channel
  120. *
  121. * This should not be called if a DMA channel is enabled,
  122. * especially since some DMA architectures don't update the
  123. * DMA count immediately, but defer it to the enable_dma().
  124. */
  125. extern void set_dma_count(dmach_t channel, unsigned long count);
  126. /* Set the transfer direction for this channel
  127. *
  128. * This should not be called if a DMA channel is enabled,
  129. * especially since some DMA architectures don't update the
  130. * DMA transfer direction immediately, but defer it to the
  131. * enable_dma().
  132. */
  133. extern void set_dma_mode(dmach_t channel, dmamode_t mode);
  134. /* Set the transfer speed for this channel
  135. */
  136. extern void set_dma_speed(dmach_t channel, int cycle_ns);
  137. /* Get DMA residue count. After a DMA transfer, this
  138. * should return zero. Reading this while a DMA transfer is
  139. * still in progress will return unpredictable results.
  140. * If called before the channel has been used, it may return 1.
  141. * Otherwise, it returns the number of _bytes_ left to transfer.
  142. */
  143. extern int get_dma_residue(dmach_t channel);
  144. #ifndef NO_DMA
  145. #define NO_DMA 255
  146. #endif
  147. #endif /* _ARM_DMA_H */