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include
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asm-arm
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arch-ep93xx
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ep93xx-regs.h

ep93xx-regs.h 4.7 KB
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  1. /*
    2. 

  2.  * linux/include/asm-arm/arch-ep93xx/ep93xx-regs.h
    3. 

  3.  */
    4. 

  4. 

  5. #ifndef __ASM_ARCH_EP93XX_REGS_H
    6. 

  6. #define __ASM_ARCH_EP93XX_REGS_H
    7. 

  7. 

  8. /*
    9. 

  9.  * EP93xx linux memory map:
    10. 

  10.  *
    11. 

  11.  * virt		phys		size
    12. 

  12.  * fe800000			5M		per-platform mappings
    13. 

  13.  * fed00000	80800000	2M		APB
    14. 

  14.  * fef00000	80000000	1M		AHB
    15. 

  15.  */
    16. 

  16. 

  17. #define EP93XX_AHB_PHYS_BASE		0x80000000
    18. 

  18. #define EP93XX_AHB_VIRT_BASE		0xfef00000
    19. 

  19. #define EP93XX_AHB_SIZE			0x00100000
    20. 

  20. 

  21. #define EP93XX_APB_PHYS_BASE		0x80800000
    22. 

  22. #define EP93XX_APB_VIRT_BASE		0xfed00000
    23. 

  23. #define EP93XX_APB_SIZE			0x00200000
    24. 

  24. 

  25. 

  26. /* AHB peripherals */
    27. 

  27. #define EP93XX_DMA_BASE			(EP93XX_AHB_VIRT_BASE + 0x00000000)
    28. 

  28. 

  29. #define EP93XX_ETHERNET_BASE		(EP93XX_AHB_VIRT_BASE + 0x00010000)
    30. 

  30. #define EP93XX_ETHERNET_PHYS_BASE	(EP93XX_AHB_PHYS_BASE + 0x00010000)
    31. 

  31. 

  32. #define EP93XX_USB_BASE			(EP93XX_AHB_VIRT_BASE + 0x00020000)
    33. 

  33. #define EP93XX_USB_PHYS_BASE		(EP93XX_AHB_PHYS_BASE + 0x00020000)
    34. 

  34. 

  35. #define EP93XX_RASTER_BASE		(EP93XX_AHB_VIRT_BASE + 0x00030000)
    36. 

  36. 

  37. #define EP93XX_GRAPHICS_ACCEL_BASE	(EP93XX_AHB_VIRT_BASE + 0x00040000)
    38. 

  38. 

  39. #define EP93XX_SDRAM_CONTROLLER_BASE	(EP93XX_AHB_VIRT_BASE + 0x00060000)
    40. 

  40. 

  41. #define EP93XX_PCMCIA_CONTROLLER_BASE	(EP93XX_AHB_VIRT_BASE + 0x00080000)
    42. 

  42. 

  43. #define EP93XX_BOOT_ROM_BASE		(EP93XX_AHB_VIRT_BASE + 0x00090000)
    44. 

  44. 

  45. #define EP93XX_IDE_BASE			(EP93XX_AHB_VIRT_BASE + 0x000a0000)
    46. 

  46. 

  47. #define EP93XX_VIC1_BASE		(EP93XX_AHB_VIRT_BASE + 0x000b0000)
    48. 

  48. 

  49. #define EP93XX_VIC2_BASE		(EP93XX_AHB_VIRT_BASE + 0x000c0000)
    50. 

  50. 

  51. 

  52. /* APB peripherals */
    53. 

  53. #define EP93XX_TIMER_BASE		(EP93XX_APB_VIRT_BASE + 0x00010000)
    54. 

  54. #define EP93XX_TIMER_REG(x)		(EP93XX_TIMER_BASE + (x))
    55. 

  55. #define EP93XX_TIMER1_LOAD		EP93XX_TIMER_REG(0x00)
    56. 

  56. #define EP93XX_TIMER1_VALUE		EP93XX_TIMER_REG(0x04)
    57. 

  57. #define EP93XX_TIMER1_CONTROL		EP93XX_TIMER_REG(0x08)
    58. 

  58. #define EP93XX_TIMER1_CLEAR		EP93XX_TIMER_REG(0x0c)
    59. 

  59. #define EP93XX_TIMER2_LOAD		EP93XX_TIMER_REG(0x20)
    60. 

  60. #define EP93XX_TIMER2_VALUE		EP93XX_TIMER_REG(0x24)
    61. 

  61. #define EP93XX_TIMER2_CONTROL		EP93XX_TIMER_REG(0x28)
    62. 

  62. #define EP93XX_TIMER2_CLEAR		EP93XX_TIMER_REG(0x2c)
    63. 

  63. #define EP93XX_TIMER4_VALUE_LOW		EP93XX_TIMER_REG(0x60)
    64. 

  64. #define EP93XX_TIMER4_VALUE_HIGH	EP93XX_TIMER_REG(0x64)
    65. 

  65. #define EP93XX_TIMER3_LOAD		EP93XX_TIMER_REG(0x80)
    66. 

  66. #define EP93XX_TIMER3_VALUE		EP93XX_TIMER_REG(0x84)
    67. 

  67. #define EP93XX_TIMER3_CONTROL		EP93XX_TIMER_REG(0x88)
    68. 

  68. #define EP93XX_TIMER3_CLEAR		EP93XX_TIMER_REG(0x8c)
    69. 

  69. 

  70. #define EP93XX_I2S_BASE			(EP93XX_APB_VIRT_BASE + 0x00020000)
    71. 

  71. 

  72. #define EP93XX_SECURITY_BASE		(EP93XX_APB_VIRT_BASE + 0x00030000)
    73. 

  73. 

  74. #define EP93XX_GPIO_BASE		(EP93XX_APB_VIRT_BASE + 0x00040000)
    75. 

  75. #define EP93XX_GPIO_REG(x)		(EP93XX_GPIO_BASE + (x))
    76. 

  76. #define EP93XX_GPIO_A_INT_TYPE1		EP93XX_GPIO_REG(0x90)
    77. 

  77. #define EP93XX_GPIO_A_INT_TYPE2		EP93XX_GPIO_REG(0x94)
    78. 

  78. #define EP93XX_GPIO_A_INT_ACK		EP93XX_GPIO_REG(0x98)
    79. 

  79. #define EP93XX_GPIO_A_INT_ENABLE	EP93XX_GPIO_REG(0x9c)
    80. 

  80. #define EP93XX_GPIO_A_INT_STATUS	EP93XX_GPIO_REG(0xa0)
    81. 

  81. #define EP93XX_GPIO_B_INT_TYPE1		EP93XX_GPIO_REG(0xac)
    82. 

  82. #define EP93XX_GPIO_B_INT_TYPE2		EP93XX_GPIO_REG(0xb0)
    83. 

  83. #define EP93XX_GPIO_B_INT_ACK		EP93XX_GPIO_REG(0xb4)
    84. 

  84. #define EP93XX_GPIO_B_INT_ENABLE	EP93XX_GPIO_REG(0xb8)
    85. 

  85. #define EP93XX_GPIO_B_INT_STATUS	EP93XX_GPIO_REG(0xbc)
    86. 

  86. 

  87. #define EP93XX_AAC_BASE			(EP93XX_APB_VIRT_BASE + 0x00080000)
    88. 

  88. 

  89. #define EP93XX_SPI_BASE			(EP93XX_APB_VIRT_BASE + 0x000a0000)
    90. 

  90. 

  91. #define EP93XX_IRDA_BASE		(EP93XX_APB_VIRT_BASE + 0x000b0000)
    92. 

  92. 

  93. #define EP93XX_UART1_BASE		(EP93XX_APB_VIRT_BASE + 0x000c0000)
    94. 

  94. #define EP93XX_UART1_PHYS_BASE		(EP93XX_APB_PHYS_BASE + 0x000c0000)
    95. 

  95. 

  96. #define EP93XX_UART2_BASE		(EP93XX_APB_VIRT_BASE + 0x000d0000)
    97. 

  97. #define EP93XX_UART2_PHYS_BASE		(EP93XX_APB_PHYS_BASE + 0x000d0000)
    98. 

  98. 

  99. #define EP93XX_UART3_BASE		(EP93XX_APB_VIRT_BASE + 0x000e0000)
    100. 

  100. #define EP93XX_UART3_PHYS_BASE		(EP93XX_APB_PHYS_BASE + 0x000e0000)
    101. 

  101. 

  102. #define EP93XX_KEY_MATRIX_BASE		(EP93XX_APB_VIRT_BASE + 0x000f0000)
    103. 

  103. 

  104. #define EP93XX_ADC_BASE			(EP93XX_APB_VIRT_BASE + 0x00100000)
    105. 

  105. #define EP93XX_TOUCHSCREEN_BASE		(EP93XX_APB_VIRT_BASE + 0x00100000)
    106. 

  106. 

  107. #define EP93XX_PWM_BASE			(EP93XX_APB_VIRT_BASE + 0x00110000)
    108. 

  108. 

  109. #define EP93XX_RTC_BASE			(EP93XX_APB_VIRT_BASE + 0x00120000)
    110. 

  110. 

  111. #define EP93XX_SYSCON_BASE		(EP93XX_APB_VIRT_BASE + 0x00130000)
    112. 

  112. #define EP93XX_SYSCON_REG(x)		(EP93XX_SYSCON_BASE + (x))
    113. 

  113. #define EP93XX_SYSCON_POWER_STATE	EP93XX_SYSCON_REG(0x00)
    114. 

  114. #define EP93XX_SYSCON_CLOCK_CONTROL	EP93XX_SYSCON_REG(0x04)
    115. 

  115. #define EP93XX_SYSCON_CLOCK_UARTBAUD	0x20000000
    116. 

  116. #define EP93XX_SYSCON_CLOCK_USH_EN	0x10000000
    117. 

  117. #define EP93XX_SYSCON_HALT		EP93XX_SYSCON_REG(0x08)
    118. 

  118. #define EP93XX_SYSCON_STANDBY		EP93XX_SYSCON_REG(0x0c)
    119. 

  119. #define EP93XX_SYSCON_CLOCK_SET1	EP93XX_SYSCON_REG(0x20)
    120. 

  120. #define EP93XX_SYSCON_CLOCK_SET2	EP93XX_SYSCON_REG(0x24)
    121. 

  121. #define EP93XX_SYSCON_DEVICE_CONFIG	EP93XX_SYSCON_REG(0x80)
    122. 

  122. #define EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE	0x00800000
    123. 

  123. #define EP93XX_SYSCON_SWLOCK		EP93XX_SYSCON_REG(0xc0)
    124. 

  124. 

  125. #define EP93XX_WATCHDOG_BASE		(EP93XX_APB_VIRT_BASE + 0x00140000)
    126. 

  126. 

  127. 

  128. #endif
    129.