spi_s3c24xx.c 9.4 KB

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  1. /* linux/drivers/spi/spi_s3c24xx.c
  2. *
  3. * Copyright (c) 2006 Ben Dooks
  4. * Copyright (c) 2006 Simtec Electronics
  5. * Ben Dooks <ben@simtec.co.uk>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. */
  12. //#define DEBUG
  13. #include <linux/init.h>
  14. #include <linux/spinlock.h>
  15. #include <linux/workqueue.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include <linux/err.h>
  20. #include <linux/clk.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/spi/spi.h>
  23. #include <linux/spi/spi_bitbang.h>
  24. #include <asm/io.h>
  25. #include <asm/dma.h>
  26. #include <asm/hardware.h>
  27. #include <asm/arch/regs-gpio.h>
  28. #include <asm/arch/regs-spi.h>
  29. #include <asm/arch/spi.h>
  30. struct s3c24xx_spi {
  31. /* bitbang has to be first */
  32. struct spi_bitbang bitbang;
  33. struct completion done;
  34. void __iomem *regs;
  35. int irq;
  36. int len;
  37. int count;
  38. /* data buffers */
  39. const unsigned char *tx;
  40. unsigned char *rx;
  41. struct clk *clk;
  42. struct resource *ioarea;
  43. struct spi_master *master;
  44. struct spi_device *curdev;
  45. struct device *dev;
  46. struct s3c2410_spi_info *pdata;
  47. };
  48. #define SPCON_DEFAULT (S3C2410_SPCON_MSTR | S3C2410_SPCON_SMOD_INT)
  49. #define SPPIN_DEFAULT (S3C2410_SPPIN_KEEP)
  50. static inline struct s3c24xx_spi *to_hw(struct spi_device *sdev)
  51. {
  52. return spi_master_get_devdata(sdev->master);
  53. }
  54. static void s3c24xx_spi_chipsel(struct spi_device *spi, int value)
  55. {
  56. struct s3c24xx_spi *hw = to_hw(spi);
  57. unsigned int cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
  58. unsigned int spcon;
  59. switch (value) {
  60. case BITBANG_CS_INACTIVE:
  61. if (hw->pdata->set_cs)
  62. hw->pdata->set_cs(hw->pdata, value, cspol);
  63. else
  64. s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol ^ 1);
  65. break;
  66. case BITBANG_CS_ACTIVE:
  67. spcon = readb(hw->regs + S3C2410_SPCON);
  68. if (spi->mode & SPI_CPHA)
  69. spcon |= S3C2410_SPCON_CPHA_FMTB;
  70. else
  71. spcon &= ~S3C2410_SPCON_CPHA_FMTB;
  72. if (spi->mode & SPI_CPOL)
  73. spcon |= S3C2410_SPCON_CPOL_HIGH;
  74. else
  75. spcon &= ~S3C2410_SPCON_CPOL_HIGH;
  76. spcon |= S3C2410_SPCON_ENSCK;
  77. /* write new configration */
  78. writeb(spcon, hw->regs + S3C2410_SPCON);
  79. if (hw->pdata->set_cs)
  80. hw->pdata->set_cs(hw->pdata, value, cspol);
  81. else
  82. s3c2410_gpio_setpin(hw->pdata->pin_cs, cspol);
  83. break;
  84. }
  85. }
  86. static int s3c24xx_spi_setupxfer(struct spi_device *spi,
  87. struct spi_transfer *t)
  88. {
  89. struct s3c24xx_spi *hw = to_hw(spi);
  90. unsigned int bpw;
  91. unsigned int hz;
  92. unsigned int div;
  93. bpw = t ? t->bits_per_word : spi->bits_per_word;
  94. hz = t ? t->speed_hz : spi->max_speed_hz;
  95. if (bpw != 8) {
  96. dev_err(&spi->dev, "invalid bits-per-word (%d)\n", bpw);
  97. return -EINVAL;
  98. }
  99. div = clk_get_rate(hw->clk) / hz;
  100. /* is clk = pclk / (2 * (pre+1)), or is it
  101. * clk = (pclk * 2) / ( pre + 1) */
  102. div = (div / 2) - 1;
  103. if (div < 0)
  104. div = 1;
  105. if (div > 255)
  106. div = 255;
  107. dev_dbg(&spi->dev, "setting pre-scaler to %d (hz %d)\n", div, hz);
  108. writeb(div, hw->regs + S3C2410_SPPRE);
  109. spin_lock(&hw->bitbang.lock);
  110. if (!hw->bitbang.busy) {
  111. hw->bitbang.chipselect(spi, BITBANG_CS_INACTIVE);
  112. /* need to ndelay for 0.5 clocktick ? */
  113. }
  114. spin_unlock(&hw->bitbang.lock);
  115. return 0;
  116. }
  117. static int s3c24xx_spi_setup(struct spi_device *spi)
  118. {
  119. int ret;
  120. if (!spi->bits_per_word)
  121. spi->bits_per_word = 8;
  122. if ((spi->mode & SPI_LSB_FIRST) != 0)
  123. return -EINVAL;
  124. ret = s3c24xx_spi_setupxfer(spi, NULL);
  125. if (ret < 0) {
  126. dev_err(&spi->dev, "setupxfer returned %d\n", ret);
  127. return ret;
  128. }
  129. dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n",
  130. __FUNCTION__, spi->mode, spi->bits_per_word,
  131. spi->max_speed_hz);
  132. return 0;
  133. }
  134. static inline unsigned int hw_txbyte(struct s3c24xx_spi *hw, int count)
  135. {
  136. return hw->tx ? hw->tx[count] : 0xff;
  137. }
  138. static int s3c24xx_spi_txrx(struct spi_device *spi, struct spi_transfer *t)
  139. {
  140. struct s3c24xx_spi *hw = to_hw(spi);
  141. dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
  142. t->tx_buf, t->rx_buf, t->len);
  143. hw->tx = t->tx_buf;
  144. hw->rx = t->rx_buf;
  145. hw->len = t->len;
  146. hw->count = 0;
  147. /* send the first byte */
  148. writeb(hw_txbyte(hw, 0), hw->regs + S3C2410_SPTDAT);
  149. wait_for_completion(&hw->done);
  150. return hw->count;
  151. }
  152. static irqreturn_t s3c24xx_spi_irq(int irq, void *dev)
  153. {
  154. struct s3c24xx_spi *hw = dev;
  155. unsigned int spsta = readb(hw->regs + S3C2410_SPSTA);
  156. unsigned int count = hw->count;
  157. if (spsta & S3C2410_SPSTA_DCOL) {
  158. dev_dbg(hw->dev, "data-collision\n");
  159. complete(&hw->done);
  160. goto irq_done;
  161. }
  162. if (!(spsta & S3C2410_SPSTA_READY)) {
  163. dev_dbg(hw->dev, "spi not ready for tx?\n");
  164. complete(&hw->done);
  165. goto irq_done;
  166. }
  167. hw->count++;
  168. if (hw->rx)
  169. hw->rx[count] = readb(hw->regs + S3C2410_SPRDAT);
  170. count++;
  171. if (count < hw->len)
  172. writeb(hw_txbyte(hw, count), hw->regs + S3C2410_SPTDAT);
  173. else
  174. complete(&hw->done);
  175. irq_done:
  176. return IRQ_HANDLED;
  177. }
  178. static int s3c24xx_spi_probe(struct platform_device *pdev)
  179. {
  180. struct s3c24xx_spi *hw;
  181. struct spi_master *master;
  182. struct spi_board_info *bi;
  183. struct resource *res;
  184. int err = 0;
  185. int i;
  186. master = spi_alloc_master(&pdev->dev, sizeof(struct s3c24xx_spi));
  187. if (master == NULL) {
  188. dev_err(&pdev->dev, "No memory for spi_master\n");
  189. err = -ENOMEM;
  190. goto err_nomem;
  191. }
  192. hw = spi_master_get_devdata(master);
  193. memset(hw, 0, sizeof(struct s3c24xx_spi));
  194. hw->master = spi_master_get(master);
  195. hw->pdata = pdev->dev.platform_data;
  196. hw->dev = &pdev->dev;
  197. if (hw->pdata == NULL) {
  198. dev_err(&pdev->dev, "No platform data supplied\n");
  199. err = -ENOENT;
  200. goto err_no_pdata;
  201. }
  202. platform_set_drvdata(pdev, hw);
  203. init_completion(&hw->done);
  204. /* setup the state for the bitbang driver */
  205. hw->bitbang.master = hw->master;
  206. hw->bitbang.setup_transfer = s3c24xx_spi_setupxfer;
  207. hw->bitbang.chipselect = s3c24xx_spi_chipsel;
  208. hw->bitbang.txrx_bufs = s3c24xx_spi_txrx;
  209. hw->bitbang.master->setup = s3c24xx_spi_setup;
  210. dev_dbg(hw->dev, "bitbang at %p\n", &hw->bitbang);
  211. /* find and map our resources */
  212. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  213. if (res == NULL) {
  214. dev_err(&pdev->dev, "Cannot get IORESOURCE_MEM\n");
  215. err = -ENOENT;
  216. goto err_no_iores;
  217. }
  218. hw->ioarea = request_mem_region(res->start, (res->end - res->start)+1,
  219. pdev->name);
  220. if (hw->ioarea == NULL) {
  221. dev_err(&pdev->dev, "Cannot reserve region\n");
  222. err = -ENXIO;
  223. goto err_no_iores;
  224. }
  225. hw->regs = ioremap(res->start, (res->end - res->start)+1);
  226. if (hw->regs == NULL) {
  227. dev_err(&pdev->dev, "Cannot map IO\n");
  228. err = -ENXIO;
  229. goto err_no_iomap;
  230. }
  231. hw->irq = platform_get_irq(pdev, 0);
  232. if (hw->irq < 0) {
  233. dev_err(&pdev->dev, "No IRQ specified\n");
  234. err = -ENOENT;
  235. goto err_no_irq;
  236. }
  237. err = request_irq(hw->irq, s3c24xx_spi_irq, 0, pdev->name, hw);
  238. if (err) {
  239. dev_err(&pdev->dev, "Cannot claim IRQ\n");
  240. goto err_no_irq;
  241. }
  242. hw->clk = clk_get(&pdev->dev, "spi");
  243. if (IS_ERR(hw->clk)) {
  244. dev_err(&pdev->dev, "No clock for device\n");
  245. err = PTR_ERR(hw->clk);
  246. goto err_no_clk;
  247. }
  248. /* for the moment, permanently enable the clock */
  249. clk_enable(hw->clk);
  250. /* program defaults into the registers */
  251. writeb(0xff, hw->regs + S3C2410_SPPRE);
  252. writeb(SPPIN_DEFAULT, hw->regs + S3C2410_SPPIN);
  253. writeb(SPCON_DEFAULT, hw->regs + S3C2410_SPCON);
  254. /* setup any gpio we can */
  255. if (!hw->pdata->set_cs) {
  256. s3c2410_gpio_setpin(hw->pdata->pin_cs, 1);
  257. s3c2410_gpio_cfgpin(hw->pdata->pin_cs, S3C2410_GPIO_OUTPUT);
  258. }
  259. /* register our spi controller */
  260. err = spi_bitbang_start(&hw->bitbang);
  261. if (err) {
  262. dev_err(&pdev->dev, "Failed to register SPI master\n");
  263. goto err_register;
  264. }
  265. dev_dbg(hw->dev, "shutdown=%d\n", hw->bitbang.shutdown);
  266. /* register all the devices associated */
  267. bi = &hw->pdata->board_info[0];
  268. for (i = 0; i < hw->pdata->board_size; i++, bi++) {
  269. dev_info(hw->dev, "registering %s\n", bi->modalias);
  270. bi->controller_data = hw;
  271. spi_new_device(master, bi);
  272. }
  273. return 0;
  274. err_register:
  275. clk_disable(hw->clk);
  276. clk_put(hw->clk);
  277. err_no_clk:
  278. free_irq(hw->irq, hw);
  279. err_no_irq:
  280. iounmap(hw->regs);
  281. err_no_iomap:
  282. release_resource(hw->ioarea);
  283. kfree(hw->ioarea);
  284. err_no_iores:
  285. err_no_pdata:
  286. spi_master_put(hw->master);;
  287. err_nomem:
  288. return err;
  289. }
  290. static int s3c24xx_spi_remove(struct platform_device *dev)
  291. {
  292. struct s3c24xx_spi *hw = platform_get_drvdata(dev);
  293. platform_set_drvdata(dev, NULL);
  294. spi_unregister_master(hw->master);
  295. clk_disable(hw->clk);
  296. clk_put(hw->clk);
  297. free_irq(hw->irq, hw);
  298. iounmap(hw->regs);
  299. release_resource(hw->ioarea);
  300. kfree(hw->ioarea);
  301. spi_master_put(hw->master);
  302. return 0;
  303. }
  304. #ifdef CONFIG_PM
  305. static int s3c24xx_spi_suspend(struct platform_device *pdev, pm_message_t msg)
  306. {
  307. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  308. clk_disable(hw->clk);
  309. return 0;
  310. }
  311. static int s3c24xx_spi_resume(struct platform_device *pdev)
  312. {
  313. struct s3c24xx_spi *hw = platform_get_drvdata(pdev);
  314. clk_enable(hw->clk);
  315. return 0;
  316. }
  317. #else
  318. #define s3c24xx_spi_suspend NULL
  319. #define s3c24xx_spi_resume NULL
  320. #endif
  321. static struct platform_driver s3c24xx_spidrv = {
  322. .probe = s3c24xx_spi_probe,
  323. .remove = s3c24xx_spi_remove,
  324. .suspend = s3c24xx_spi_suspend,
  325. .resume = s3c24xx_spi_resume,
  326. .driver = {
  327. .name = "s3c2410-spi",
  328. .owner = THIS_MODULE,
  329. },
  330. };
  331. static int __init s3c24xx_spi_init(void)
  332. {
  333. return platform_driver_register(&s3c24xx_spidrv);
  334. }
  335. static void __exit s3c24xx_spi_exit(void)
  336. {
  337. platform_driver_unregister(&s3c24xx_spidrv);
  338. }
  339. module_init(s3c24xx_spi_init);
  340. module_exit(s3c24xx_spi_exit);
  341. MODULE_DESCRIPTION("S3C24XX SPI Driver");
  342. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  343. MODULE_LICENSE("GPL");