amba-pl010.c 18 KB

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  1. /*
  2. * linux/drivers/char/amba.c
  3. *
  4. * Driver for AMBA serial ports
  5. *
  6. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  7. *
  8. * Copyright 1999 ARM Limited
  9. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License as published by
  13. * the Free Software Foundation; either version 2 of the License, or
  14. * (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  24. *
  25. * $Id: amba.c,v 1.41 2002/07/28 10:03:27 rmk Exp $
  26. *
  27. * This is a generic driver for ARM AMBA-type serial ports. They
  28. * have a lot of 16550-like features, but are not register compatible.
  29. * Note that although they do have CTS, DCD and DSR inputs, they do
  30. * not have an RI input, nor do they have DTR or RTS outputs. If
  31. * required, these have to be supplied via some other means (eg, GPIO)
  32. * and hooked into this driver.
  33. */
  34. #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  35. #define SUPPORT_SYSRQ
  36. #endif
  37. #include <linux/module.h>
  38. #include <linux/ioport.h>
  39. #include <linux/init.h>
  40. #include <linux/console.h>
  41. #include <linux/sysrq.h>
  42. #include <linux/device.h>
  43. #include <linux/tty.h>
  44. #include <linux/tty_flip.h>
  45. #include <linux/serial_core.h>
  46. #include <linux/serial.h>
  47. #include <linux/amba/bus.h>
  48. #include <linux/amba/serial.h>
  49. #include <asm/io.h>
  50. #define UART_NR 8
  51. #define SERIAL_AMBA_MAJOR 204
  52. #define SERIAL_AMBA_MINOR 16
  53. #define SERIAL_AMBA_NR UART_NR
  54. #define AMBA_ISR_PASS_LIMIT 256
  55. #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
  56. #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
  57. #define UART_DUMMY_RSR_RX 256
  58. #define UART_PORT_SIZE 64
  59. /*
  60. * We wrap our port structure around the generic uart_port.
  61. */
  62. struct uart_amba_port {
  63. struct uart_port port;
  64. struct amba_device *dev;
  65. struct amba_pl010_data *data;
  66. unsigned int old_status;
  67. };
  68. static void pl010_stop_tx(struct uart_port *port)
  69. {
  70. unsigned int cr;
  71. cr = readb(port->membase + UART010_CR);
  72. cr &= ~UART010_CR_TIE;
  73. writel(cr, port->membase + UART010_CR);
  74. }
  75. static void pl010_start_tx(struct uart_port *port)
  76. {
  77. unsigned int cr;
  78. cr = readb(port->membase + UART010_CR);
  79. cr |= UART010_CR_TIE;
  80. writel(cr, port->membase + UART010_CR);
  81. }
  82. static void pl010_stop_rx(struct uart_port *port)
  83. {
  84. unsigned int cr;
  85. cr = readb(port->membase + UART010_CR);
  86. cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
  87. writel(cr, port->membase + UART010_CR);
  88. }
  89. static void pl010_enable_ms(struct uart_port *port)
  90. {
  91. unsigned int cr;
  92. cr = readb(port->membase + UART010_CR);
  93. cr |= UART010_CR_MSIE;
  94. writel(cr, port->membase + UART010_CR);
  95. }
  96. static void pl010_rx_chars(struct uart_port *port)
  97. {
  98. struct tty_struct *tty = port->info->tty;
  99. unsigned int status, ch, flag, rsr, max_count = 256;
  100. status = readb(port->membase + UART01x_FR);
  101. while (UART_RX_DATA(status) && max_count--) {
  102. ch = readb(port->membase + UART01x_DR);
  103. flag = TTY_NORMAL;
  104. port->icount.rx++;
  105. /*
  106. * Note that the error handling code is
  107. * out of the main execution path
  108. */
  109. rsr = readb(port->membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
  110. if (unlikely(rsr & UART01x_RSR_ANY)) {
  111. if (rsr & UART01x_RSR_BE) {
  112. rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
  113. port->icount.brk++;
  114. if (uart_handle_break(port))
  115. goto ignore_char;
  116. } else if (rsr & UART01x_RSR_PE)
  117. port->icount.parity++;
  118. else if (rsr & UART01x_RSR_FE)
  119. port->icount.frame++;
  120. if (rsr & UART01x_RSR_OE)
  121. port->icount.overrun++;
  122. rsr &= port->read_status_mask;
  123. if (rsr & UART01x_RSR_BE)
  124. flag = TTY_BREAK;
  125. else if (rsr & UART01x_RSR_PE)
  126. flag = TTY_PARITY;
  127. else if (rsr & UART01x_RSR_FE)
  128. flag = TTY_FRAME;
  129. }
  130. if (uart_handle_sysrq_char(port, ch))
  131. goto ignore_char;
  132. uart_insert_char(port, rsr, UART01x_RSR_OE, ch, flag);
  133. ignore_char:
  134. status = readb(port->membase + UART01x_FR);
  135. }
  136. tty_flip_buffer_push(tty);
  137. return;
  138. }
  139. static void pl010_tx_chars(struct uart_port *port)
  140. {
  141. struct circ_buf *xmit = &port->info->xmit;
  142. int count;
  143. if (port->x_char) {
  144. writel(port->x_char, port->membase + UART01x_DR);
  145. port->icount.tx++;
  146. port->x_char = 0;
  147. return;
  148. }
  149. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  150. pl010_stop_tx(port);
  151. return;
  152. }
  153. count = port->fifosize >> 1;
  154. do {
  155. writel(xmit->buf[xmit->tail], port->membase + UART01x_DR);
  156. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  157. port->icount.tx++;
  158. if (uart_circ_empty(xmit))
  159. break;
  160. } while (--count > 0);
  161. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  162. uart_write_wakeup(port);
  163. if (uart_circ_empty(xmit))
  164. pl010_stop_tx(port);
  165. }
  166. static void pl010_modem_status(struct uart_port *port)
  167. {
  168. struct uart_amba_port *uap = (struct uart_amba_port *)port;
  169. unsigned int status, delta;
  170. writel(0, uap->port.membase + UART010_ICR);
  171. status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
  172. delta = status ^ uap->old_status;
  173. uap->old_status = status;
  174. if (!delta)
  175. return;
  176. if (delta & UART01x_FR_DCD)
  177. uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
  178. if (delta & UART01x_FR_DSR)
  179. uap->port.icount.dsr++;
  180. if (delta & UART01x_FR_CTS)
  181. uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
  182. wake_up_interruptible(&uap->port.info->delta_msr_wait);
  183. }
  184. static irqreturn_t pl010_int(int irq, void *dev_id)
  185. {
  186. struct uart_port *port = dev_id;
  187. unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
  188. int handled = 0;
  189. spin_lock(&port->lock);
  190. status = readb(port->membase + UART010_IIR);
  191. if (status) {
  192. do {
  193. if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
  194. pl010_rx_chars(port);
  195. if (status & UART010_IIR_MIS)
  196. pl010_modem_status(port);
  197. if (status & UART010_IIR_TIS)
  198. pl010_tx_chars(port);
  199. if (pass_counter-- == 0)
  200. break;
  201. status = readb(port->membase + UART010_IIR);
  202. } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
  203. UART010_IIR_TIS));
  204. handled = 1;
  205. }
  206. spin_unlock(&port->lock);
  207. return IRQ_RETVAL(handled);
  208. }
  209. static unsigned int pl010_tx_empty(struct uart_port *port)
  210. {
  211. return readb(port->membase + UART01x_FR) & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
  212. }
  213. static unsigned int pl010_get_mctrl(struct uart_port *port)
  214. {
  215. unsigned int result = 0;
  216. unsigned int status;
  217. status = readb(port->membase + UART01x_FR);
  218. if (status & UART01x_FR_DCD)
  219. result |= TIOCM_CAR;
  220. if (status & UART01x_FR_DSR)
  221. result |= TIOCM_DSR;
  222. if (status & UART01x_FR_CTS)
  223. result |= TIOCM_CTS;
  224. return result;
  225. }
  226. static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
  227. {
  228. struct uart_amba_port *uap = (struct uart_amba_port *)port;
  229. if (uap->data)
  230. uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
  231. }
  232. static void pl010_break_ctl(struct uart_port *port, int break_state)
  233. {
  234. unsigned long flags;
  235. unsigned int lcr_h;
  236. spin_lock_irqsave(&port->lock, flags);
  237. lcr_h = readb(port->membase + UART010_LCRH);
  238. if (break_state == -1)
  239. lcr_h |= UART01x_LCRH_BRK;
  240. else
  241. lcr_h &= ~UART01x_LCRH_BRK;
  242. writel(lcr_h, port->membase + UART010_LCRH);
  243. spin_unlock_irqrestore(&port->lock, flags);
  244. }
  245. static int pl010_startup(struct uart_port *port)
  246. {
  247. struct uart_amba_port *uap = (struct uart_amba_port *)port;
  248. int retval;
  249. /*
  250. * Allocate the IRQ
  251. */
  252. retval = request_irq(port->irq, pl010_int, 0, "uart-pl010", port);
  253. if (retval)
  254. return retval;
  255. /*
  256. * initialise the old status of the modem signals
  257. */
  258. uap->old_status = readb(port->membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
  259. /*
  260. * Finally, enable interrupts
  261. */
  262. writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
  263. port->membase + UART010_CR);
  264. return 0;
  265. }
  266. static void pl010_shutdown(struct uart_port *port)
  267. {
  268. /*
  269. * Free the interrupt
  270. */
  271. free_irq(port->irq, port);
  272. /*
  273. * disable all interrupts, disable the port
  274. */
  275. writel(0, port->membase + UART010_CR);
  276. /* disable break condition and fifos */
  277. writel(readb(port->membase + UART010_LCRH) &
  278. ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
  279. port->membase + UART010_LCRH);
  280. }
  281. static void
  282. pl010_set_termios(struct uart_port *port, struct termios *termios,
  283. struct termios *old)
  284. {
  285. unsigned int lcr_h, old_cr;
  286. unsigned long flags;
  287. unsigned int baud, quot;
  288. /*
  289. * Ask the core to calculate the divisor for us.
  290. */
  291. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  292. quot = uart_get_divisor(port, baud);
  293. switch (termios->c_cflag & CSIZE) {
  294. case CS5:
  295. lcr_h = UART01x_LCRH_WLEN_5;
  296. break;
  297. case CS6:
  298. lcr_h = UART01x_LCRH_WLEN_6;
  299. break;
  300. case CS7:
  301. lcr_h = UART01x_LCRH_WLEN_7;
  302. break;
  303. default: // CS8
  304. lcr_h = UART01x_LCRH_WLEN_8;
  305. break;
  306. }
  307. if (termios->c_cflag & CSTOPB)
  308. lcr_h |= UART01x_LCRH_STP2;
  309. if (termios->c_cflag & PARENB) {
  310. lcr_h |= UART01x_LCRH_PEN;
  311. if (!(termios->c_cflag & PARODD))
  312. lcr_h |= UART01x_LCRH_EPS;
  313. }
  314. if (port->fifosize > 1)
  315. lcr_h |= UART01x_LCRH_FEN;
  316. spin_lock_irqsave(&port->lock, flags);
  317. /*
  318. * Update the per-port timeout.
  319. */
  320. uart_update_timeout(port, termios->c_cflag, baud);
  321. port->read_status_mask = UART01x_RSR_OE;
  322. if (termios->c_iflag & INPCK)
  323. port->read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
  324. if (termios->c_iflag & (BRKINT | PARMRK))
  325. port->read_status_mask |= UART01x_RSR_BE;
  326. /*
  327. * Characters to ignore
  328. */
  329. port->ignore_status_mask = 0;
  330. if (termios->c_iflag & IGNPAR)
  331. port->ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
  332. if (termios->c_iflag & IGNBRK) {
  333. port->ignore_status_mask |= UART01x_RSR_BE;
  334. /*
  335. * If we're ignoring parity and break indicators,
  336. * ignore overruns too (for real raw support).
  337. */
  338. if (termios->c_iflag & IGNPAR)
  339. port->ignore_status_mask |= UART01x_RSR_OE;
  340. }
  341. /*
  342. * Ignore all characters if CREAD is not set.
  343. */
  344. if ((termios->c_cflag & CREAD) == 0)
  345. port->ignore_status_mask |= UART_DUMMY_RSR_RX;
  346. /* first, disable everything */
  347. old_cr = readb(port->membase + UART010_CR) & ~UART010_CR_MSIE;
  348. if (UART_ENABLE_MS(port, termios->c_cflag))
  349. old_cr |= UART010_CR_MSIE;
  350. writel(0, port->membase + UART010_CR);
  351. /* Set baud rate */
  352. quot -= 1;
  353. writel((quot & 0xf00) >> 8, port->membase + UART010_LCRM);
  354. writel(quot & 0xff, port->membase + UART010_LCRL);
  355. /*
  356. * ----------v----------v----------v----------v-----
  357. * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
  358. * ----------^----------^----------^----------^-----
  359. */
  360. writel(lcr_h, port->membase + UART010_LCRH);
  361. writel(old_cr, port->membase + UART010_CR);
  362. spin_unlock_irqrestore(&port->lock, flags);
  363. }
  364. static const char *pl010_type(struct uart_port *port)
  365. {
  366. return port->type == PORT_AMBA ? "AMBA" : NULL;
  367. }
  368. /*
  369. * Release the memory region(s) being used by 'port'
  370. */
  371. static void pl010_release_port(struct uart_port *port)
  372. {
  373. release_mem_region(port->mapbase, UART_PORT_SIZE);
  374. }
  375. /*
  376. * Request the memory region(s) being used by 'port'
  377. */
  378. static int pl010_request_port(struct uart_port *port)
  379. {
  380. return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
  381. != NULL ? 0 : -EBUSY;
  382. }
  383. /*
  384. * Configure/autoconfigure the port.
  385. */
  386. static void pl010_config_port(struct uart_port *port, int flags)
  387. {
  388. if (flags & UART_CONFIG_TYPE) {
  389. port->type = PORT_AMBA;
  390. pl010_request_port(port);
  391. }
  392. }
  393. /*
  394. * verify the new serial_struct (for TIOCSSERIAL).
  395. */
  396. static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
  397. {
  398. int ret = 0;
  399. if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
  400. ret = -EINVAL;
  401. if (ser->irq < 0 || ser->irq >= NR_IRQS)
  402. ret = -EINVAL;
  403. if (ser->baud_base < 9600)
  404. ret = -EINVAL;
  405. return ret;
  406. }
  407. static struct uart_ops amba_pl010_pops = {
  408. .tx_empty = pl010_tx_empty,
  409. .set_mctrl = pl010_set_mctrl,
  410. .get_mctrl = pl010_get_mctrl,
  411. .stop_tx = pl010_stop_tx,
  412. .start_tx = pl010_start_tx,
  413. .stop_rx = pl010_stop_rx,
  414. .enable_ms = pl010_enable_ms,
  415. .break_ctl = pl010_break_ctl,
  416. .startup = pl010_startup,
  417. .shutdown = pl010_shutdown,
  418. .set_termios = pl010_set_termios,
  419. .type = pl010_type,
  420. .release_port = pl010_release_port,
  421. .request_port = pl010_request_port,
  422. .config_port = pl010_config_port,
  423. .verify_port = pl010_verify_port,
  424. };
  425. static struct uart_amba_port *amba_ports[UART_NR];
  426. #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
  427. static void pl010_console_putchar(struct uart_port *port, int ch)
  428. {
  429. unsigned int status;
  430. do {
  431. status = readb(port->membase + UART01x_FR);
  432. barrier();
  433. } while (!UART_TX_READY(status));
  434. writel(ch, port->membase + UART01x_DR);
  435. }
  436. static void
  437. pl010_console_write(struct console *co, const char *s, unsigned int count)
  438. {
  439. struct uart_port *port = &amba_ports[co->index]->port;
  440. unsigned int status, old_cr;
  441. /*
  442. * First save the CR then disable the interrupts
  443. */
  444. old_cr = readb(port->membase + UART010_CR);
  445. writel(UART01x_CR_UARTEN, port->membase + UART010_CR);
  446. uart_console_write(port, s, count, pl010_console_putchar);
  447. /*
  448. * Finally, wait for transmitter to become empty
  449. * and restore the TCR
  450. */
  451. do {
  452. status = readb(port->membase + UART01x_FR);
  453. barrier();
  454. } while (status & UART01x_FR_BUSY);
  455. writel(old_cr, port->membase + UART010_CR);
  456. }
  457. static void __init
  458. pl010_console_get_options(struct uart_port *port, int *baud,
  459. int *parity, int *bits)
  460. {
  461. if (readb(port->membase + UART010_CR) & UART01x_CR_UARTEN) {
  462. unsigned int lcr_h, quot;
  463. lcr_h = readb(port->membase + UART010_LCRH);
  464. *parity = 'n';
  465. if (lcr_h & UART01x_LCRH_PEN) {
  466. if (lcr_h & UART01x_LCRH_EPS)
  467. *parity = 'e';
  468. else
  469. *parity = 'o';
  470. }
  471. if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
  472. *bits = 7;
  473. else
  474. *bits = 8;
  475. quot = readb(port->membase + UART010_LCRL) | readb(port->membase + UART010_LCRM) << 8;
  476. *baud = port->uartclk / (16 * (quot + 1));
  477. }
  478. }
  479. static int __init pl010_console_setup(struct console *co, char *options)
  480. {
  481. struct uart_port *port;
  482. int baud = 38400;
  483. int bits = 8;
  484. int parity = 'n';
  485. int flow = 'n';
  486. /*
  487. * Check whether an invalid uart number has been specified, and
  488. * if so, search for the first available port that does have
  489. * console support.
  490. */
  491. if (co->index >= UART_NR)
  492. co->index = 0;
  493. port = &amba_ports[co->index]->port;
  494. if (options)
  495. uart_parse_options(options, &baud, &parity, &bits, &flow);
  496. else
  497. pl010_console_get_options(port, &baud, &parity, &bits);
  498. return uart_set_options(port, co, baud, parity, bits, flow);
  499. }
  500. static struct uart_driver amba_reg;
  501. static struct console amba_console = {
  502. .name = "ttyAM",
  503. .write = pl010_console_write,
  504. .device = uart_console_device,
  505. .setup = pl010_console_setup,
  506. .flags = CON_PRINTBUFFER,
  507. .index = -1,
  508. .data = &amba_reg,
  509. };
  510. #define AMBA_CONSOLE &amba_console
  511. #else
  512. #define AMBA_CONSOLE NULL
  513. #endif
  514. static struct uart_driver amba_reg = {
  515. .owner = THIS_MODULE,
  516. .driver_name = "ttyAM",
  517. .dev_name = "ttyAM",
  518. .major = SERIAL_AMBA_MAJOR,
  519. .minor = SERIAL_AMBA_MINOR,
  520. .nr = UART_NR,
  521. .cons = AMBA_CONSOLE,
  522. };
  523. static int pl010_probe(struct amba_device *dev, void *id)
  524. {
  525. struct uart_amba_port *port;
  526. void __iomem *base;
  527. int i, ret;
  528. for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
  529. if (amba_ports[i] == NULL)
  530. break;
  531. if (i == ARRAY_SIZE(amba_ports)) {
  532. ret = -EBUSY;
  533. goto out;
  534. }
  535. port = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL);
  536. if (!port) {
  537. ret = -ENOMEM;
  538. goto out;
  539. }
  540. base = ioremap(dev->res.start, PAGE_SIZE);
  541. if (!base) {
  542. ret = -ENOMEM;
  543. goto free;
  544. }
  545. port->port.dev = &dev->dev;
  546. port->port.mapbase = dev->res.start;
  547. port->port.membase = base;
  548. port->port.iotype = UPIO_MEM;
  549. port->port.irq = dev->irq[0];
  550. port->port.uartclk = 14745600;
  551. port->port.fifosize = 16;
  552. port->port.ops = &amba_pl010_pops;
  553. port->port.flags = UPF_BOOT_AUTOCONF;
  554. port->port.line = i;
  555. port->dev = dev;
  556. port->data = dev->dev.platform_data;
  557. amba_ports[i] = port;
  558. amba_set_drvdata(dev, port);
  559. ret = uart_add_one_port(&amba_reg, &port->port);
  560. if (ret) {
  561. amba_set_drvdata(dev, NULL);
  562. amba_ports[i] = NULL;
  563. iounmap(base);
  564. free:
  565. kfree(port);
  566. }
  567. out:
  568. return ret;
  569. }
  570. static int pl010_remove(struct amba_device *dev)
  571. {
  572. struct uart_amba_port *port = amba_get_drvdata(dev);
  573. int i;
  574. amba_set_drvdata(dev, NULL);
  575. uart_remove_one_port(&amba_reg, &port->port);
  576. for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
  577. if (amba_ports[i] == port)
  578. amba_ports[i] = NULL;
  579. iounmap(port->port.membase);
  580. kfree(port);
  581. return 0;
  582. }
  583. static int pl010_suspend(struct amba_device *dev, pm_message_t state)
  584. {
  585. struct uart_amba_port *uap = amba_get_drvdata(dev);
  586. if (uap)
  587. uart_suspend_port(&amba_reg, &uap->port);
  588. return 0;
  589. }
  590. static int pl010_resume(struct amba_device *dev)
  591. {
  592. struct uart_amba_port *uap = amba_get_drvdata(dev);
  593. if (uap)
  594. uart_resume_port(&amba_reg, &uap->port);
  595. return 0;
  596. }
  597. static struct amba_id pl010_ids[] __initdata = {
  598. {
  599. .id = 0x00041010,
  600. .mask = 0x000fffff,
  601. },
  602. { 0, 0 },
  603. };
  604. static struct amba_driver pl010_driver = {
  605. .drv = {
  606. .name = "uart-pl010",
  607. },
  608. .id_table = pl010_ids,
  609. .probe = pl010_probe,
  610. .remove = pl010_remove,
  611. .suspend = pl010_suspend,
  612. .resume = pl010_resume,
  613. };
  614. static int __init pl010_init(void)
  615. {
  616. int ret;
  617. printk(KERN_INFO "Serial: AMBA driver $Revision: 1.41 $\n");
  618. ret = uart_register_driver(&amba_reg);
  619. if (ret == 0) {
  620. ret = amba_driver_register(&pl010_driver);
  621. if (ret)
  622. uart_unregister_driver(&amba_reg);
  623. }
  624. return ret;
  625. }
  626. static void __exit pl010_exit(void)
  627. {
  628. amba_driver_unregister(&pl010_driver);
  629. uart_unregister_driver(&amba_reg);
  630. }
  631. module_init(pl010_init);
  632. module_exit(pl010_exit);
  633. MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
  634. MODULE_DESCRIPTION("ARM AMBA serial port driver $Revision: 1.41 $");
  635. MODULE_LICENSE("GPL");