hptiop.h 12 KB

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  1. /*
  2. * HighPoint RR3xxx controller driver for Linux
  3. * Copyright (C) 2006 HighPoint Technologies, Inc. All Rights Reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; version 2 of the License.
  8. *
  9. * This program is distributed in the hope that it will be useful,
  10. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  12. * GNU General Public License for more details.
  13. *
  14. * Please report bugs/comments/suggestions to linux@highpoint-tech.com
  15. *
  16. * For more information, visit http://www.highpoint-tech.com
  17. */
  18. #ifndef _HPTIOP_H_
  19. #define _HPTIOP_H_
  20. /*
  21. * logical device type.
  22. * Identify array (logical device) and physical device.
  23. */
  24. #define LDT_ARRAY 1
  25. #define LDT_DEVICE 2
  26. /*
  27. * Array types
  28. */
  29. #define AT_UNKNOWN 0
  30. #define AT_RAID0 1
  31. #define AT_RAID1 2
  32. #define AT_RAID5 3
  33. #define AT_RAID6 4
  34. #define AT_JBOD 7
  35. #define MAX_NAME_LENGTH 36
  36. #define MAX_ARRAYNAME_LEN 16
  37. #define MAX_ARRAY_MEMBERS_V1 8
  38. #define MAX_ARRAY_MEMBERS_V2 16
  39. /* keep definition for source code compatiblity */
  40. #define MAX_ARRAY_MEMBERS MAX_ARRAY_MEMBERS_V1
  41. /*
  42. * array flags
  43. */
  44. #define ARRAY_FLAG_DISABLED 0x00000001 /* The array is disabled */
  45. #define ARRAY_FLAG_NEEDBUILDING 0x00000002 /* need to be rebuilt */
  46. #define ARRAY_FLAG_REBUILDING 0x00000004 /* in rebuilding process */
  47. #define ARRAY_FLAG_BROKEN 0x00000008 /* broken but still working */
  48. #define ARRAY_FLAG_BOOTDISK 0x00000010 /* has a active partition */
  49. #define ARRAY_FLAG_BOOTMARK 0x00000040 /* array has boot mark set */
  50. #define ARRAY_FLAG_NEED_AUTOREBUILD 0x00000080 /* auto-rebuild should start */
  51. #define ARRAY_FLAG_VERIFYING 0x00000100 /* is being verified */
  52. #define ARRAY_FLAG_INITIALIZING 0x00000200 /* is being initialized */
  53. #define ARRAY_FLAG_TRANSFORMING 0x00000400 /* tranform in progress */
  54. #define ARRAY_FLAG_NEEDTRANSFORM 0x00000800 /* array need tranform */
  55. #define ARRAY_FLAG_NEEDINITIALIZING 0x00001000 /* initialization not done */
  56. #define ARRAY_FLAG_BROKEN_REDUNDANT 0x00002000 /* broken but redundant */
  57. /*
  58. * device flags
  59. */
  60. #define DEVICE_FLAG_DISABLED 0x00000001 /* device is disabled */
  61. #define DEVICE_FLAG_UNINITIALIZED 0x00010000 /* device is not initialized */
  62. #define DEVICE_FLAG_LEGACY 0x00020000 /* lagacy drive */
  63. #define DEVICE_FLAG_IS_SPARE 0x80000000 /* is a spare disk */
  64. /*
  65. * ioctl codes
  66. */
  67. #define HPT_CTL_CODE(x) (x+0xFF00)
  68. #define HPT_CTL_CODE_LINUX_TO_IOP(x) ((x)-0xff00)
  69. #define HPT_IOCTL_GET_CONTROLLER_INFO HPT_CTL_CODE(2)
  70. #define HPT_IOCTL_GET_CHANNEL_INFO HPT_CTL_CODE(3)
  71. #define HPT_IOCTL_GET_LOGICAL_DEVICES HPT_CTL_CODE(4)
  72. #define HPT_IOCTL_GET_DRIVER_CAPABILITIES HPT_CTL_CODE(19)
  73. #define HPT_IOCTL_GET_DEVICE_INFO_V3 HPT_CTL_CODE(46)
  74. #define HPT_IOCTL_GET_CONTROLLER_INFO_V2 HPT_CTL_CODE(47)
  75. /*
  76. * Controller information.
  77. */
  78. struct hpt_controller_info {
  79. u8 chip_type; /* chip type */
  80. u8 interrupt_level; /* IRQ level */
  81. u8 num_buses; /* bus count */
  82. u8 chip_flags;
  83. u8 product_id[MAX_NAME_LENGTH];/* product name */
  84. u8 vendor_id[MAX_NAME_LENGTH]; /* vendor name */
  85. }
  86. __attribute__((packed));
  87. /*
  88. * Channel information.
  89. */
  90. struct hpt_channel_info {
  91. __le32 io_port; /* IDE Base Port Address */
  92. __le32 control_port; /* IDE Control Port Address */
  93. __le32 devices[2]; /* device connected to this channel */
  94. }
  95. __attribute__((packed));
  96. /*
  97. * Array information.
  98. */
  99. struct hpt_array_info_v3 {
  100. u8 name[MAX_ARRAYNAME_LEN]; /* array name */
  101. u8 description[64]; /* array description */
  102. u8 create_manager[16]; /* who created it */
  103. __le32 create_time; /* when created it */
  104. u8 array_type; /* array type */
  105. u8 block_size_shift; /* stripe size */
  106. u8 ndisk; /* Number of ID in Members[] */
  107. u8 reserved;
  108. __le32 flags; /* working flags, see ARRAY_FLAG_XXX */
  109. __le32 members[MAX_ARRAY_MEMBERS_V2]; /* member array/disks */
  110. __le32 rebuilding_progress;
  111. __le64 rebuilt_sectors; /* rebuilding point (LBA) for single member */
  112. __le32 transform_source;
  113. __le32 transform_target; /* destination device ID */
  114. __le32 transforming_progress;
  115. __le32 signature; /* persistent identification*/
  116. __le16 critical_members; /* bit mask of critical members */
  117. __le16 reserve2;
  118. __le32 reserve;
  119. }
  120. __attribute__((packed));
  121. /*
  122. * physical device information.
  123. */
  124. #define MAX_PARENTS_PER_DISK 8
  125. struct hpt_device_info_v2 {
  126. u8 ctlr_id; /* controller id */
  127. u8 path_id; /* bus */
  128. u8 target_id; /* id */
  129. u8 device_mode_setting; /* Current Data Transfer mode: 0-4 PIO0-4 */
  130. /* 5-7 MW DMA0-2, 8-13 UDMA0-5 */
  131. u8 device_type; /* device type */
  132. u8 usable_mode; /* highest usable mode */
  133. #ifdef __BIG_ENDIAN_BITFIELD
  134. u8 NCQ_enabled: 1;
  135. u8 NCQ_supported: 1;
  136. u8 TCQ_enabled: 1;
  137. u8 TCQ_supported: 1;
  138. u8 write_cache_enabled: 1;
  139. u8 write_cache_supported: 1;
  140. u8 read_ahead_enabled: 1;
  141. u8 read_ahead_supported: 1;
  142. u8 reserved6: 6;
  143. u8 spin_up_mode: 2;
  144. #else
  145. u8 read_ahead_supported: 1;
  146. u8 read_ahead_enabled: 1;
  147. u8 write_cache_supported: 1;
  148. u8 write_cache_enabled: 1;
  149. u8 TCQ_supported: 1;
  150. u8 TCQ_enabled: 1;
  151. u8 NCQ_supported: 1;
  152. u8 NCQ_enabled: 1;
  153. u8 spin_up_mode: 2;
  154. u8 reserved6: 6;
  155. #endif
  156. __le32 flags; /* working flags, see DEVICE_FLAG_XXX */
  157. u8 ident[150]; /* (partitial) Identify Data of this device */
  158. __le64 total_free;
  159. __le64 max_free;
  160. __le64 bad_sectors;
  161. __le32 parent_arrays[MAX_PARENTS_PER_DISK];
  162. }
  163. __attribute__((packed));
  164. /*
  165. * Logical device information.
  166. */
  167. #define INVALID_TARGET_ID 0xFF
  168. #define INVALID_BUS_ID 0xFF
  169. struct hpt_logical_device_info_v3 {
  170. u8 type; /* LDT_ARRAY or LDT_DEVICE */
  171. u8 cache_policy; /* refer to CACHE_POLICY_xxx */
  172. u8 vbus_id; /* vbus sequence in vbus_list */
  173. u8 target_id; /* OS target id. 0xFF is invalid */
  174. /* OS name: DISK $VBusId_$TargetId */
  175. __le64 capacity; /* array capacity */
  176. __le32 parent_array; /* don't use this field for physical
  177. device. use ParentArrays field in
  178. hpt_device_info_v2 */
  179. /* reserved statistic fields */
  180. __le32 stat1;
  181. __le32 stat2;
  182. __le32 stat3;
  183. __le32 stat4;
  184. union {
  185. struct hpt_array_info_v3 array;
  186. struct hpt_device_info_v2 device;
  187. } __attribute__((packed)) u;
  188. }
  189. __attribute__((packed));
  190. /*
  191. * ioctl structure
  192. */
  193. #define HPT_IOCTL_MAGIC 0xA1B2C3D4
  194. struct hpt_ioctl_u {
  195. u32 magic; /* used to check if it's a valid ioctl packet */
  196. u32 ioctl_code; /* operation control code */
  197. void __user *inbuf; /* input data buffer */
  198. u32 inbuf_size; /* size of input data buffer */
  199. void __user *outbuf; /* output data buffer */
  200. u32 outbuf_size; /* size of output data buffer */
  201. void __user *bytes_returned; /* count of bytes returned */
  202. }
  203. __attribute__((packed));
  204. struct hpt_iopmu
  205. {
  206. __le32 resrved0[4];
  207. __le32 inbound_msgaddr0;
  208. __le32 inbound_msgaddr1;
  209. __le32 outbound_msgaddr0;
  210. __le32 outbound_msgaddr1;
  211. __le32 inbound_doorbell;
  212. __le32 inbound_intstatus;
  213. __le32 inbound_intmask;
  214. __le32 outbound_doorbell;
  215. __le32 outbound_intstatus;
  216. __le32 outbound_intmask;
  217. __le32 reserved1[2];
  218. __le32 inbound_queue;
  219. __le32 outbound_queue;
  220. };
  221. #define IOPMU_QUEUE_EMPTY 0xffffffff
  222. #define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000
  223. #define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000
  224. #define IOPMU_OUTBOUND_INT_MSG0 1
  225. #define IOPMU_OUTBOUND_INT_MSG1 2
  226. #define IOPMU_OUTBOUND_INT_DOORBELL 4
  227. #define IOPMU_OUTBOUND_INT_POSTQUEUE 8
  228. #define IOPMU_OUTBOUND_INT_PCI 0x10
  229. #define IOPMU_INBOUND_INT_MSG0 1
  230. #define IOPMU_INBOUND_INT_MSG1 2
  231. #define IOPMU_INBOUND_INT_DOORBELL 4
  232. #define IOPMU_INBOUND_INT_ERROR 8
  233. #define IOPMU_INBOUND_INT_POSTQUEUE 0x10
  234. enum hpt_iopmu_message {
  235. /* host-to-iop messages */
  236. IOPMU_INBOUND_MSG0_NOP = 0,
  237. IOPMU_INBOUND_MSG0_RESET,
  238. IOPMU_INBOUND_MSG0_FLUSH,
  239. IOPMU_INBOUND_MSG0_SHUTDOWN,
  240. IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK,
  241. IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK,
  242. IOPMU_INBOUND_MSG0_MAX = 0xff,
  243. /* iop-to-host messages */
  244. IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100,
  245. IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff,
  246. IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200,
  247. IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff,
  248. IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300,
  249. IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff,
  250. };
  251. struct hpt_iop_request_header
  252. {
  253. __le32 size;
  254. __le32 type;
  255. __le32 flags;
  256. __le32 result;
  257. __le32 context; /* host context */
  258. __le32 context_hi32;
  259. };
  260. #define IOP_REQUEST_FLAG_SYNC_REQUEST 1
  261. #define IOP_REQUEST_FLAG_BIST_REQUEST 2
  262. #define IOP_REQUEST_FLAG_REMAPPED 4
  263. #define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8
  264. enum hpt_iop_request_type {
  265. IOP_REQUEST_TYPE_GET_CONFIG = 0,
  266. IOP_REQUEST_TYPE_SET_CONFIG,
  267. IOP_REQUEST_TYPE_BLOCK_COMMAND,
  268. IOP_REQUEST_TYPE_SCSI_COMMAND,
  269. IOP_REQUEST_TYPE_IOCTL_COMMAND,
  270. IOP_REQUEST_TYPE_MAX
  271. };
  272. enum hpt_iop_result_type {
  273. IOP_RESULT_PENDING = 0,
  274. IOP_RESULT_SUCCESS,
  275. IOP_RESULT_FAIL,
  276. IOP_RESULT_BUSY,
  277. IOP_RESULT_RESET,
  278. IOP_RESULT_INVALID_REQUEST,
  279. IOP_RESULT_BAD_TARGET,
  280. IOP_RESULT_MODE_SENSE_CHECK_CONDITION,
  281. };
  282. struct hpt_iop_request_get_config
  283. {
  284. struct hpt_iop_request_header header;
  285. __le32 interface_version;
  286. __le32 firmware_version;
  287. __le32 max_requests;
  288. __le32 request_size;
  289. __le32 max_sg_count;
  290. __le32 data_transfer_length;
  291. __le32 alignment_mask;
  292. __le32 max_devices;
  293. __le32 sdram_size;
  294. };
  295. struct hpt_iop_request_set_config
  296. {
  297. struct hpt_iop_request_header header;
  298. __le32 iop_id;
  299. __le32 vbus_id;
  300. __le32 reserve[6];
  301. };
  302. struct hpt_iopsg
  303. {
  304. __le32 size;
  305. __le32 eot; /* non-zero: end of table */
  306. __le64 pci_address;
  307. };
  308. struct hpt_iop_request_block_command
  309. {
  310. struct hpt_iop_request_header header;
  311. u8 channel;
  312. u8 target;
  313. u8 lun;
  314. u8 pad1;
  315. __le16 command; /* IOP_BLOCK_COMMAND_{READ,WRITE} */
  316. __le16 sectors;
  317. __le64 lba;
  318. struct hpt_iopsg sg_list[1];
  319. };
  320. #define IOP_BLOCK_COMMAND_READ 1
  321. #define IOP_BLOCK_COMMAND_WRITE 2
  322. #define IOP_BLOCK_COMMAND_VERIFY 3
  323. #define IOP_BLOCK_COMMAND_FLUSH 4
  324. #define IOP_BLOCK_COMMAND_SHUTDOWN 5
  325. struct hpt_iop_request_scsi_command
  326. {
  327. struct hpt_iop_request_header header;
  328. u8 channel;
  329. u8 target;
  330. u8 lun;
  331. u8 pad1;
  332. u8 cdb[16];
  333. __le32 dataxfer_length;
  334. struct hpt_iopsg sg_list[1];
  335. };
  336. struct hpt_iop_request_ioctl_command
  337. {
  338. struct hpt_iop_request_header header;
  339. __le32 ioctl_code;
  340. __le32 inbuf_size;
  341. __le32 outbuf_size;
  342. __le32 bytes_returned;
  343. u8 buf[1];
  344. /* out data should be put at buf[(inbuf_size+3)&~3] */
  345. };
  346. #define HPTIOP_MAX_REQUESTS 256u
  347. struct hptiop_request {
  348. struct hptiop_request * next;
  349. void * req_virt;
  350. u32 req_shifted_phy;
  351. struct scsi_cmnd * scp;
  352. int index;
  353. };
  354. struct hpt_scsi_pointer {
  355. int mapped;
  356. int sgcnt;
  357. dma_addr_t dma_handle;
  358. };
  359. #define HPT_SCP(scp) ((struct hpt_scsi_pointer *)&(scp)->SCp)
  360. struct hptiop_hba {
  361. struct hpt_iopmu __iomem * iop;
  362. struct Scsi_Host * host;
  363. struct pci_dev * pcidev;
  364. struct list_head link;
  365. /* IOP config info */
  366. u32 firmware_version;
  367. u32 sdram_size;
  368. u32 max_devices;
  369. u32 max_requests;
  370. u32 max_request_size;
  371. u32 max_sg_descriptors;
  372. u32 req_size; /* host-allocated request buffer size */
  373. int initialized;
  374. int msg_done;
  375. struct hptiop_request * req_list;
  376. struct hptiop_request reqs[HPTIOP_MAX_REQUESTS];
  377. /* used to free allocated dma area */
  378. void * dma_coherent;
  379. dma_addr_t dma_coherent_handle;
  380. atomic_t reset_count;
  381. atomic_t resetting;
  382. wait_queue_head_t reset_wq;
  383. wait_queue_head_t ioctl_wq;
  384. };
  385. struct hpt_ioctl_k
  386. {
  387. struct hptiop_hba * hba;
  388. u32 ioctl_code;
  389. u32 inbuf_size;
  390. u32 outbuf_size;
  391. void * inbuf;
  392. void * outbuf;
  393. u32 * bytes_returned;
  394. void (*done)(struct hpt_ioctl_k *);
  395. int result; /* HPT_IOCTL_RESULT_ */
  396. };
  397. #define HPT_IOCTL_RESULT_OK 0
  398. #define HPT_IOCTL_RESULT_FAILED (-1)
  399. #if 0
  400. #define dprintk(fmt, args...) do { printk(fmt, ##args); } while(0)
  401. #else
  402. #define dprintk(fmt, args...)
  403. #endif
  404. #endif