gdth.c 201 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.74 2006/04/10 13:44:47 achim
  34. * Community changes for 2.6.x
  35. * Kernel 2.2.x no longer supported
  36. * scsi_request interface removed, thanks to Christoph Hellwig
  37. *
  38. * Revision 1.73 2004/03/31 13:33:03 achim
  39. * Special command 0xfd implemented to detect 64-bit DMA support
  40. *
  41. * Revision 1.72 2004/03/17 08:56:04 achim
  42. * 64-bit DMA only enabled if FW >= x.43
  43. *
  44. * Revision 1.71 2004/03/05 15:51:29 achim
  45. * Screen service: separate message buffer, bugfixes
  46. *
  47. * Revision 1.70 2004/02/27 12:19:07 achim
  48. * Bugfix: Reset bit in config (0xfe) call removed
  49. *
  50. * Revision 1.69 2004/02/20 09:50:24 achim
  51. * Compatibility changes for kernels < 2.4.20
  52. * Bugfix screen service command size
  53. * pci_set_dma_mask() error handling added
  54. *
  55. * Revision 1.68 2004/02/19 15:46:54 achim
  56. * 64-bit DMA bugfixes
  57. * Drive size bugfix for drives > 1TB
  58. *
  59. * Revision 1.67 2004/01/14 13:11:57 achim
  60. * Tool access over /proc no longer supported
  61. * Bugfixes IOCTLs
  62. *
  63. * Revision 1.66 2003/12/19 15:04:06 achim
  64. * Bugfixes support for drives > 2TB
  65. *
  66. * Revision 1.65 2003/12/15 11:21:56 achim
  67. * 64-bit DMA support added
  68. * Support for drives > 2 TB implemented
  69. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  70. *
  71. * Revision 1.64 2003/09/17 08:30:26 achim
  72. * EISA/ISA controller scan disabled
  73. * Command line switch probe_eisa_isa added
  74. *
  75. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  76. * Minor cleanups in gdth_ioctl.
  77. *
  78. * Revision 1.62 2003/02/27 15:01:59 achim
  79. * Dynamic DMA mapping implemented
  80. * New (character device) IOCTL interface added
  81. * Other controller related changes made
  82. *
  83. * Revision 1.61 2002/11/08 13:09:52 boji
  84. * Added support for XSCALE based RAID Controllers
  85. * Fixed SCREENSERVICE initialization in SMP cases
  86. * Added checks for gdth_polling before GDTH_HA_LOCK
  87. *
  88. * Revision 1.60 2002/02/05 09:35:22 achim
  89. * MODULE_LICENSE only if kernel >= 2.4.11
  90. *
  91. * Revision 1.59 2002/01/30 09:46:33 achim
  92. * Small changes
  93. *
  94. * Revision 1.58 2002/01/29 15:30:02 achim
  95. * Set default value of shared_access to Y
  96. * New status S_CACHE_RESERV for clustering added
  97. *
  98. * Revision 1.57 2001/08/21 11:16:35 achim
  99. * Bugfix free_irq()
  100. *
  101. * Revision 1.56 2001/08/09 11:19:39 achim
  102. * Scsi_Host_Template changes
  103. *
  104. * Revision 1.55 2001/08/09 10:11:28 achim
  105. * Command HOST_UNFREEZE_IO before cache service init.
  106. *
  107. * Revision 1.54 2001/07/20 13:48:12 achim
  108. * Expand: gdth_analyse_hdrive() removed
  109. *
  110. * Revision 1.53 2001/07/17 09:52:49 achim
  111. * Small OEM related change
  112. *
  113. * Revision 1.52 2001/06/19 15:06:20 achim
  114. * New host command GDT_UNFREEZE_IO added
  115. *
  116. * Revision 1.51 2001/05/22 06:42:37 achim
  117. * PCI: Subdevice ID added
  118. *
  119. * Revision 1.50 2001/05/17 13:42:16 achim
  120. * Support for Intel Storage RAID Controllers added
  121. *
  122. * Revision 1.50 2001/05/17 12:12:34 achim
  123. * Support for Intel Storage RAID Controllers added
  124. *
  125. * Revision 1.49 2001/03/15 15:07:17 achim
  126. * New __setup interface for boot command line options added
  127. *
  128. * Revision 1.48 2001/02/06 12:36:28 achim
  129. * Bugfix Cluster protocol
  130. *
  131. * Revision 1.47 2001/01/10 14:42:06 achim
  132. * New switch shared_access added
  133. *
  134. * Revision 1.46 2001/01/09 08:11:35 achim
  135. * gdth_command() removed
  136. * meaning of Scsi_Pointer members changed
  137. *
  138. * Revision 1.45 2000/11/16 12:02:24 achim
  139. * Changes for kernel 2.4
  140. *
  141. * Revision 1.44 2000/10/11 08:44:10 achim
  142. * Clustering changes: New flag media_changed added
  143. *
  144. * Revision 1.43 2000/09/20 12:59:01 achim
  145. * DPMEM remap functions for all PCI controller types implemented
  146. * Small changes for ia64 platform
  147. *
  148. * Revision 1.42 2000/07/20 09:04:50 achim
  149. * Small changes for kernel 2.4
  150. *
  151. * Revision 1.41 2000/07/04 14:11:11 achim
  152. * gdth_analyse_hdrive() added to rescan drives after online expansion
  153. *
  154. * Revision 1.40 2000/06/27 11:24:16 achim
  155. * Changes Clustering, Screenservice
  156. *
  157. * Revision 1.39 2000/06/15 13:09:04 achim
  158. * Changes for gdth_do_cmd()
  159. *
  160. * Revision 1.38 2000/06/15 12:08:43 achim
  161. * Bugfix gdth_sync_event(), service SCREENSERVICE
  162. * Data direction for command 0xc2 changed to DOU
  163. *
  164. * Revision 1.37 2000/05/25 13:50:10 achim
  165. * New driver parameter virt_ctr added
  166. *
  167. * Revision 1.36 2000/05/04 08:50:46 achim
  168. * Event buffer now in gdth_ha_str
  169. *
  170. * Revision 1.35 2000/03/03 10:44:08 achim
  171. * New event_string only valid for the RP controller family
  172. *
  173. * Revision 1.34 2000/03/02 14:55:29 achim
  174. * New mechanism for async. event handling implemented
  175. *
  176. * Revision 1.33 2000/02/21 15:37:37 achim
  177. * Bugfix Alpha platform + DPMEM above 4GB
  178. *
  179. * Revision 1.32 2000/02/14 16:17:37 achim
  180. * Bugfix sense_buffer[] + raw devices
  181. *
  182. * Revision 1.31 2000/02/10 10:29:00 achim
  183. * Delete sense_buffer[0], if command OK
  184. *
  185. * Revision 1.30 1999/11/02 13:42:39 achim
  186. * ARRAY_DRV_LIST2 implemented
  187. * Now 255 log. and 100 host drives supported
  188. *
  189. * Revision 1.29 1999/10/05 13:28:47 achim
  190. * GDT_CLUST_RESET added
  191. *
  192. * Revision 1.28 1999/08/12 13:44:54 achim
  193. * MOUNTALL removed
  194. * Cluster drives -> removeable drives
  195. *
  196. * Revision 1.27 1999/06/22 07:22:38 achim
  197. * Small changes
  198. *
  199. * Revision 1.26 1999/06/10 16:09:12 achim
  200. * Cluster Host Drive support: Bugfixes
  201. *
  202. * Revision 1.25 1999/06/01 16:03:56 achim
  203. * gdth_init_pci(): Manipulate config. space to start RP controller
  204. *
  205. * Revision 1.24 1999/05/26 11:53:06 achim
  206. * Cluster Host Drive support added
  207. *
  208. * Revision 1.23 1999/03/26 09:12:31 achim
  209. * Default value for hdr_channel set to 0
  210. *
  211. * Revision 1.22 1999/03/22 16:27:16 achim
  212. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  213. *
  214. * Revision 1.21 1999/03/16 13:40:34 achim
  215. * Problems with reserved drives solved
  216. * gdth_eh_bus_reset() implemented
  217. *
  218. * Revision 1.20 1999/03/10 09:08:13 achim
  219. * Bugfix: Corrections in gdth_direction_tab[] made
  220. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  221. *
  222. * Revision 1.19 1999/03/05 14:38:16 achim
  223. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  224. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  225. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  226. * with BIOS disabled and memory test set to Intensive
  227. * Enhanced /proc support
  228. *
  229. * Revision 1.18 1999/02/24 09:54:33 achim
  230. * Command line parameter hdr_channel implemented
  231. * Bugfix for EISA controllers + Linux 2.2.x
  232. *
  233. * Revision 1.17 1998/12/17 15:58:11 achim
  234. * Command line parameters implemented
  235. * Changes for Alpha platforms
  236. * PCI controller scan changed
  237. * SMP support improved (spin_lock_irqsave(),...)
  238. * New async. events, new scan/reserve commands included
  239. *
  240. * Revision 1.16 1998/09/28 16:08:46 achim
  241. * GDT_PCIMPR: DPMEM remapping, if required
  242. * mdelay() added
  243. *
  244. * Revision 1.15 1998/06/03 14:54:06 achim
  245. * gdth_delay(), gdth_flush() implemented
  246. * Bugfix: gdth_release() changed
  247. *
  248. * Revision 1.14 1998/05/22 10:01:17 achim
  249. * mj: pcibios_strerror() removed
  250. * Improved SMP support (if version >= 2.1.95)
  251. * gdth_halt(): halt_called flag added (if version < 2.1)
  252. *
  253. * Revision 1.13 1998/04/16 09:14:57 achim
  254. * Reserve drives (for raw service) implemented
  255. * New error handling code enabled
  256. * Get controller name from board_info() IOCTL
  257. * Final round of PCI device driver patches by Martin Mares
  258. *
  259. * Revision 1.12 1998/03/03 09:32:37 achim
  260. * Fibre channel controller support added
  261. *
  262. * Revision 1.11 1998/01/27 16:19:14 achim
  263. * SA_SHIRQ added
  264. * add_timer()/del_timer() instead of GDTH_TIMER
  265. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  266. * New error handling included
  267. *
  268. * Revision 1.10 1997/10/31 12:29:57 achim
  269. * Read heads/sectors from host drive
  270. *
  271. * Revision 1.9 1997/09/04 10:07:25 achim
  272. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  273. * register_reboot_notifier() to get a notify on shutown used
  274. *
  275. * Revision 1.8 1997/04/02 12:14:30 achim
  276. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  277. *
  278. * Revision 1.7 1997/03/12 13:33:37 achim
  279. * gdth_reset() changed, new async. events
  280. *
  281. * Revision 1.6 1997/03/04 14:01:11 achim
  282. * Shutdown routine gdth_halt() implemented
  283. *
  284. * Revision 1.5 1997/02/21 09:08:36 achim
  285. * New controller included (RP, RP1, RP2 series)
  286. * IOCTL interface implemented
  287. *
  288. * Revision 1.4 1996/07/05 12:48:55 achim
  289. * Function gdth_bios_param() implemented
  290. * New constant GDTH_MAXC_P_L inserted
  291. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  292. * Function gdth_reset() changed
  293. *
  294. * Revision 1.3 1996/05/10 09:04:41 achim
  295. * Small changes for Linux 1.2.13
  296. *
  297. * Revision 1.2 1996/05/09 12:45:27 achim
  298. * Loadable module support implemented
  299. * /proc support corrections made
  300. *
  301. * Revision 1.1 1996/04/11 07:35:57 achim
  302. * Initial revision
  303. *
  304. ************************************************************************/
  305. /* All GDT Disk Array Controllers are fully supported by this driver.
  306. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  307. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  308. * list of all controller types.
  309. *
  310. * If you have one or more GDT3000/3020 EISA controllers with
  311. * controller BIOS disabled, you have to set the IRQ values with the
  312. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  313. * the IRQ values for the EISA controllers.
  314. *
  315. * After the optional list of IRQ values, other possible
  316. * command line options are:
  317. * disable:Y disable driver
  318. * disable:N enable driver
  319. * reserve_mode:0 reserve no drives for the raw service
  320. * reserve_mode:1 reserve all not init., removable drives
  321. * reserve_mode:2 reserve all not init. drives
  322. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  323. * h- controller no., b- channel no.,
  324. * t- target ID, l- LUN
  325. * reverse_scan:Y reverse scan order for PCI controllers
  326. * reverse_scan:N scan PCI controllers like BIOS
  327. * max_ids:x x - target ID count per channel (1..MAXID)
  328. * rescan:Y rescan all channels/IDs
  329. * rescan:N use all devices found until now
  330. * virt_ctr:Y map every channel to a virtual controller
  331. * virt_ctr:N use multi channel support
  332. * hdr_channel:x x - number of virtual bus for host drives
  333. * shared_access:Y disable driver reserve/release protocol to
  334. * access a shared resource from several nodes,
  335. * appropriate controller firmware required
  336. * shared_access:N enable driver reserve/release protocol
  337. * probe_eisa_isa:Y scan for EISA/ISA controllers
  338. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  339. * force_dma32:Y use only 32 bit DMA mode
  340. * force_dma32:N use 64 bit DMA mode, if supported
  341. *
  342. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  343. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  344. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  345. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  346. *
  347. * When loading the gdth driver as a module, the same options are available.
  348. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  349. * options changes slightly. You must replace all ',' between options
  350. * with ' ' and all ':' with '=' and you must use
  351. * '1' in place of 'Y' and '0' in place of 'N'.
  352. *
  353. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  354. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  355. * probe_eisa_isa=0 force_dma32=0"
  356. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  357. */
  358. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  359. * ptr: Chaining
  360. * this_residual: Command priority
  361. * buffer: phys. DMA sense buffer
  362. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  363. * buffers_residual: Timeout value
  364. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  365. * Message: Additional info (gdth_do_cmd()), DMA direction
  366. * have_data_in: Flag for gdth_wait_completion()
  367. * sent_command: Opcode special command
  368. * phase: Service/parameter/return code special command
  369. */
  370. /* interrupt coalescing */
  371. /* #define INT_COAL */
  372. /* statistics */
  373. #define GDTH_STATISTICS
  374. #include <linux/module.h>
  375. #include <linux/version.h>
  376. #include <linux/kernel.h>
  377. #include <linux/types.h>
  378. #include <linux/pci.h>
  379. #include <linux/string.h>
  380. #include <linux/ctype.h>
  381. #include <linux/ioport.h>
  382. #include <linux/delay.h>
  383. #include <linux/sched.h>
  384. #include <linux/interrupt.h>
  385. #include <linux/in.h>
  386. #include <linux/proc_fs.h>
  387. #include <linux/time.h>
  388. #include <linux/timer.h>
  389. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
  390. #include <linux/dma-mapping.h>
  391. #else
  392. #define DMA_32BIT_MASK 0x00000000ffffffffULL
  393. #define DMA_64BIT_MASK 0xffffffffffffffffULL
  394. #endif
  395. #ifdef GDTH_RTC
  396. #include <linux/mc146818rtc.h>
  397. #endif
  398. #include <linux/reboot.h>
  399. #include <asm/dma.h>
  400. #include <asm/system.h>
  401. #include <asm/io.h>
  402. #include <asm/uaccess.h>
  403. #include <linux/spinlock.h>
  404. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  405. #include <linux/blkdev.h>
  406. #else
  407. #include <linux/blk.h>
  408. #include "sd.h"
  409. #endif
  410. #include "scsi.h"
  411. #include <scsi/scsi_host.h>
  412. #include "gdth_kcompat.h"
  413. #include "gdth.h"
  414. static void gdth_delay(int milliseconds);
  415. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  416. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  417. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  418. static int gdth_async_event(int hanum);
  419. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  420. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  421. static void gdth_next(int hanum);
  422. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  423. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  424. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  425. ushort idx, gdth_evt_data *evt);
  426. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  427. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  428. gdth_evt_str *estr);
  429. static void gdth_clear_events(void);
  430. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  431. char *buffer,ushort count);
  432. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  433. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  434. static int gdth_search_eisa(ushort eisa_adr);
  435. static int gdth_search_isa(ulong32 bios_adr);
  436. static int gdth_search_pci(gdth_pci_str *pcistr);
  437. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  438. ushort vendor, ushort dev);
  439. static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
  440. static int gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha);
  441. static int gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha);
  442. static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
  443. static void gdth_enable_int(int hanum);
  444. static int gdth_get_status(unchar *pIStatus,int irq);
  445. static int gdth_test_busy(int hanum);
  446. static int gdth_get_cmd_index(int hanum);
  447. static void gdth_release_event(int hanum);
  448. static int gdth_wait(int hanum,int index,ulong32 time);
  449. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  450. ulong64 p2,ulong64 p3);
  451. static int gdth_search_drives(int hanum);
  452. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  453. static const char *gdth_ctr_name(int hanum);
  454. static int gdth_open(struct inode *inode, struct file *filep);
  455. static int gdth_close(struct inode *inode, struct file *filep);
  456. static int gdth_ioctl(struct inode *inode, struct file *filep,
  457. unsigned int cmd, unsigned long arg);
  458. static void gdth_flush(int hanum);
  459. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  460. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  461. static void gdth_scsi_done(struct scsi_cmnd *scp);
  462. #ifdef DEBUG_GDTH
  463. static unchar DebugState = DEBUG_GDTH;
  464. #ifdef __SERIAL__
  465. #define MAX_SERBUF 160
  466. static void ser_init(void);
  467. static void ser_puts(char *str);
  468. static void ser_putc(char c);
  469. static int ser_printk(const char *fmt, ...);
  470. static char strbuf[MAX_SERBUF+1];
  471. #ifdef __COM2__
  472. #define COM_BASE 0x2f8
  473. #else
  474. #define COM_BASE 0x3f8
  475. #endif
  476. static void ser_init()
  477. {
  478. unsigned port=COM_BASE;
  479. outb(0x80,port+3);
  480. outb(0,port+1);
  481. /* 19200 Baud, if 9600: outb(12,port) */
  482. outb(6, port);
  483. outb(3,port+3);
  484. outb(0,port+1);
  485. /*
  486. ser_putc('I');
  487. ser_putc(' ');
  488. */
  489. }
  490. static void ser_puts(char *str)
  491. {
  492. char *ptr;
  493. ser_init();
  494. for (ptr=str;*ptr;++ptr)
  495. ser_putc(*ptr);
  496. }
  497. static void ser_putc(char c)
  498. {
  499. unsigned port=COM_BASE;
  500. while ((inb(port+5) & 0x20)==0);
  501. outb(c,port);
  502. if (c==0x0a)
  503. {
  504. while ((inb(port+5) & 0x20)==0);
  505. outb(0x0d,port);
  506. }
  507. }
  508. static int ser_printk(const char *fmt, ...)
  509. {
  510. va_list args;
  511. int i;
  512. va_start(args,fmt);
  513. i = vsprintf(strbuf,fmt,args);
  514. ser_puts(strbuf);
  515. va_end(args);
  516. return i;
  517. }
  518. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  519. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  520. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  521. #else /* !__SERIAL__ */
  522. #define TRACE(a) {if (DebugState==1) {printk a;}}
  523. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  524. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  525. #endif
  526. #else /* !DEBUG */
  527. #define TRACE(a)
  528. #define TRACE2(a)
  529. #define TRACE3(a)
  530. #endif
  531. #ifdef GDTH_STATISTICS
  532. static ulong32 max_rq=0, max_index=0, max_sg=0;
  533. #ifdef INT_COAL
  534. static ulong32 max_int_coal=0;
  535. #endif
  536. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  537. static struct timer_list gdth_timer;
  538. #endif
  539. #define PTR2USHORT(a) (ushort)(ulong)(a)
  540. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  541. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  542. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  543. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  544. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  545. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  546. #define gdth_readb(addr) readb(addr)
  547. #define gdth_readw(addr) readw(addr)
  548. #define gdth_readl(addr) readl(addr)
  549. #define gdth_writeb(b,addr) writeb((b),(addr))
  550. #define gdth_writew(b,addr) writew((b),(addr))
  551. #define gdth_writel(b,addr) writel((b),(addr))
  552. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  553. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  554. static unchar gdth_polling; /* polling if TRUE */
  555. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  556. static int wait_index,wait_hanum; /* gdth_wait() */
  557. static int gdth_ctr_count = 0; /* controller count */
  558. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  559. static int gdth_ctr_released = 0; /* gdth_release() */
  560. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  561. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  562. static unchar gdth_write_through = FALSE; /* write through */
  563. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  564. static int elastidx;
  565. static int eoldidx;
  566. static int major;
  567. #define DIN 1 /* IN data direction */
  568. #define DOU 2 /* OUT data direction */
  569. #define DNO DIN /* no data transfer */
  570. #define DUN DIN /* unknown data direction */
  571. static unchar gdth_direction_tab[0x100] = {
  572. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  573. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  574. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  575. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  576. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  577. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  578. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  579. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  580. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  581. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  582. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  583. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  584. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  585. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  586. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  587. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  588. };
  589. /* LILO and modprobe/insmod parameters */
  590. /* IRQ list for GDT3000/3020 EISA controllers */
  591. static int irq[MAXHA] __initdata =
  592. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  593. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  594. /* disable driver flag */
  595. static int disable __initdata = 0;
  596. /* reserve flag */
  597. static int reserve_mode = 1;
  598. /* reserve list */
  599. static int reserve_list[MAX_RES_ARGS] =
  600. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  601. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  602. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  603. /* scan order for PCI controllers */
  604. static int reverse_scan = 0;
  605. /* virtual channel for the host drives */
  606. static int hdr_channel = 0;
  607. /* max. IDs per channel */
  608. static int max_ids = MAXID;
  609. /* rescan all IDs */
  610. static int rescan = 0;
  611. /* map channels to virtual controllers */
  612. static int virt_ctr = 0;
  613. /* shared access */
  614. static int shared_access = 1;
  615. /* enable support for EISA and ISA controllers */
  616. static int probe_eisa_isa = 0;
  617. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  618. static int force_dma32 = 0;
  619. /* parameters for modprobe/insmod */
  620. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
  621. module_param_array(irq, int, NULL, 0);
  622. module_param(disable, int, 0);
  623. module_param(reserve_mode, int, 0);
  624. module_param_array(reserve_list, int, NULL, 0);
  625. module_param(reverse_scan, int, 0);
  626. module_param(hdr_channel, int, 0);
  627. module_param(max_ids, int, 0);
  628. module_param(rescan, int, 0);
  629. module_param(virt_ctr, int, 0);
  630. module_param(shared_access, int, 0);
  631. module_param(probe_eisa_isa, int, 0);
  632. module_param(force_dma32, int, 0);
  633. #else
  634. MODULE_PARM(irq, "i");
  635. MODULE_PARM(disable, "i");
  636. MODULE_PARM(reserve_mode, "i");
  637. MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
  638. MODULE_PARM(reverse_scan, "i");
  639. MODULE_PARM(hdr_channel, "i");
  640. MODULE_PARM(max_ids, "i");
  641. MODULE_PARM(rescan, "i");
  642. MODULE_PARM(virt_ctr, "i");
  643. MODULE_PARM(shared_access, "i");
  644. MODULE_PARM(probe_eisa_isa, "i");
  645. MODULE_PARM(force_dma32, "i");
  646. #endif
  647. MODULE_AUTHOR("Achim Leubner");
  648. MODULE_LICENSE("GPL");
  649. /* ioctl interface */
  650. static struct file_operations gdth_fops = {
  651. .ioctl = gdth_ioctl,
  652. .open = gdth_open,
  653. .release = gdth_close,
  654. };
  655. #include "gdth_proc.h"
  656. #include "gdth_proc.c"
  657. /* notifier block to get a notify on system shutdown/halt/reboot */
  658. static struct notifier_block gdth_notifier = {
  659. gdth_halt, NULL, 0
  660. };
  661. static int notifier_disabled = 0;
  662. static void gdth_delay(int milliseconds)
  663. {
  664. if (milliseconds == 0) {
  665. udelay(1);
  666. } else {
  667. mdelay(milliseconds);
  668. }
  669. }
  670. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  671. static void gdth_scsi_done(struct scsi_cmnd *scp)
  672. {
  673. TRACE2(("gdth_scsi_done()\n"));
  674. if (scp->request)
  675. complete((struct completion *)scp->request);
  676. }
  677. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  678. int timeout, u32 *info)
  679. {
  680. Scsi_Cmnd *scp;
  681. DECLARE_COMPLETION_ONSTACK(wait);
  682. int rval;
  683. scp = kmalloc(sizeof(*scp), GFP_KERNEL);
  684. if (!scp)
  685. return -ENOMEM;
  686. memset(scp, 0, sizeof(*scp));
  687. scp->device = sdev;
  688. /* use request field to save the ptr. to completion struct. */
  689. scp->request = (struct request *)&wait;
  690. scp->timeout_per_command = timeout*HZ;
  691. scp->request_buffer = gdtcmd;
  692. scp->cmd_len = 12;
  693. memcpy(scp->cmnd, cmnd, 12);
  694. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  695. scp->done = gdth_scsi_done; /* some fn. test this */
  696. gdth_queuecommand(scp, gdth_scsi_done);
  697. wait_for_completion(&wait);
  698. rval = scp->SCp.Status;
  699. if (info)
  700. *info = scp->SCp.Message;
  701. kfree(scp);
  702. return rval;
  703. }
  704. #else
  705. static void gdth_scsi_done(Scsi_Cmnd *scp)
  706. {
  707. TRACE2(("gdth_scsi_done()\n"));
  708. scp->request.rq_status = RQ_SCSI_DONE;
  709. if (scp->request.waiting)
  710. complete(scp->request.waiting);
  711. }
  712. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  713. int timeout, u32 *info)
  714. {
  715. Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
  716. unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
  717. DECLARE_COMPLETION_ONSTACK(wait);
  718. int rval;
  719. if (!scp)
  720. return -ENOMEM;
  721. scp->cmd_len = 12;
  722. scp->use_sg = 0;
  723. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  724. scp->request.rq_status = RQ_SCSI_BUSY;
  725. scp->request.waiting = &wait;
  726. scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
  727. wait_for_completion(&wait);
  728. rval = scp->SCp.Status;
  729. if (info)
  730. *info = scp->SCp.Message;
  731. scsi_release_command(scp);
  732. return rval;
  733. }
  734. #endif
  735. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  736. int timeout, u32 *info)
  737. {
  738. struct scsi_device *sdev = scsi_get_host_dev(shost);
  739. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  740. scsi_free_host_dev(sdev);
  741. return rval;
  742. }
  743. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  744. {
  745. *cyls = size /HEADS/SECS;
  746. if (*cyls <= MAXCYLS) {
  747. *heads = HEADS;
  748. *secs = SECS;
  749. } else { /* too high for 64*32 */
  750. *cyls = size /MEDHEADS/MEDSECS;
  751. if (*cyls <= MAXCYLS) {
  752. *heads = MEDHEADS;
  753. *secs = MEDSECS;
  754. } else { /* too high for 127*63 */
  755. *cyls = size /BIGHEADS/BIGSECS;
  756. *heads = BIGHEADS;
  757. *secs = BIGSECS;
  758. }
  759. }
  760. }
  761. /* controller search and initialization functions */
  762. static int __init gdth_search_eisa(ushort eisa_adr)
  763. {
  764. ulong32 id;
  765. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  766. id = inl(eisa_adr+ID0REG);
  767. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  768. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  769. return 0; /* not EISA configured */
  770. return 1;
  771. }
  772. if (id == GDT3_ID) /* GDT3000 */
  773. return 1;
  774. return 0;
  775. }
  776. static int __init gdth_search_isa(ulong32 bios_adr)
  777. {
  778. void __iomem *addr;
  779. ulong32 id;
  780. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  781. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  782. id = gdth_readl(addr);
  783. iounmap(addr);
  784. if (id == GDT2_ID) /* GDT2000 */
  785. return 1;
  786. }
  787. return 0;
  788. }
  789. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  790. {
  791. ushort device, cnt;
  792. TRACE(("gdth_search_pci()\n"));
  793. cnt = 0;
  794. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  795. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  796. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  797. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  798. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  799. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  800. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  801. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  802. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  803. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  804. PCI_DEVICE_ID_INTEL_SRC);
  805. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  806. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  807. return cnt;
  808. }
  809. /* Vortex only makes RAID controllers.
  810. * We do not really want to specify all 550 ids here, so wildcard match.
  811. */
  812. static struct pci_device_id gdthtable[] __attribute_used__ = {
  813. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  814. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  815. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  816. {0}
  817. };
  818. MODULE_DEVICE_TABLE(pci,gdthtable);
  819. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  820. ushort vendor, ushort device)
  821. {
  822. ulong base0, base1, base2;
  823. struct pci_dev *pdev;
  824. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  825. *cnt, vendor, device));
  826. pdev = NULL;
  827. while ((pdev = pci_find_device(vendor, device, pdev))
  828. != NULL) {
  829. if (pci_enable_device(pdev))
  830. continue;
  831. if (*cnt >= MAXHA)
  832. return;
  833. /* GDT PCI controller found, resources are already in pdev */
  834. pcistr[*cnt].pdev = pdev;
  835. pcistr[*cnt].vendor_id = vendor;
  836. pcistr[*cnt].device_id = device;
  837. pcistr[*cnt].subdevice_id = pdev->subsystem_device;
  838. pcistr[*cnt].bus = pdev->bus->number;
  839. pcistr[*cnt].device_fn = pdev->devfn;
  840. pcistr[*cnt].irq = pdev->irq;
  841. base0 = pci_resource_flags(pdev, 0);
  842. base1 = pci_resource_flags(pdev, 1);
  843. base2 = pci_resource_flags(pdev, 2);
  844. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  845. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  846. if (!(base0 & IORESOURCE_MEM))
  847. continue;
  848. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  849. } else { /* GDT6110, GDT6120, .. */
  850. if (!(base0 & IORESOURCE_MEM) ||
  851. !(base2 & IORESOURCE_MEM) ||
  852. !(base1 & IORESOURCE_IO))
  853. continue;
  854. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  855. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  856. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  857. }
  858. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  859. pcistr[*cnt].bus, PCI_SLOT(pcistr[*cnt].device_fn),
  860. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  861. (*cnt)++;
  862. }
  863. }
  864. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  865. {
  866. gdth_pci_str temp;
  867. int i, changed;
  868. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  869. if (cnt == 0)
  870. return;
  871. do {
  872. changed = FALSE;
  873. for (i = 0; i < cnt-1; ++i) {
  874. if (!reverse_scan) {
  875. if ((pcistr[i].bus > pcistr[i+1].bus) ||
  876. (pcistr[i].bus == pcistr[i+1].bus &&
  877. PCI_SLOT(pcistr[i].device_fn) >
  878. PCI_SLOT(pcistr[i+1].device_fn))) {
  879. temp = pcistr[i];
  880. pcistr[i] = pcistr[i+1];
  881. pcistr[i+1] = temp;
  882. changed = TRUE;
  883. }
  884. } else {
  885. if ((pcistr[i].bus < pcistr[i+1].bus) ||
  886. (pcistr[i].bus == pcistr[i+1].bus &&
  887. PCI_SLOT(pcistr[i].device_fn) <
  888. PCI_SLOT(pcistr[i+1].device_fn))) {
  889. temp = pcistr[i];
  890. pcistr[i] = pcistr[i+1];
  891. pcistr[i+1] = temp;
  892. changed = TRUE;
  893. }
  894. }
  895. }
  896. } while (changed);
  897. }
  898. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  899. {
  900. ulong32 retries,id;
  901. unchar prot_ver,eisacf,i,irq_found;
  902. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  903. /* disable board interrupts, deinitialize services */
  904. outb(0xff,eisa_adr+EDOORREG);
  905. outb(0x00,eisa_adr+EDENABREG);
  906. outb(0x00,eisa_adr+EINTENABREG);
  907. outb(0xff,eisa_adr+LDOORREG);
  908. retries = INIT_RETRIES;
  909. gdth_delay(20);
  910. while (inb(eisa_adr+EDOORREG) != 0xff) {
  911. if (--retries == 0) {
  912. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  913. return 0;
  914. }
  915. gdth_delay(1);
  916. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  917. }
  918. prot_ver = inb(eisa_adr+MAILBOXREG);
  919. outb(0xff,eisa_adr+EDOORREG);
  920. if (prot_ver != PROTOCOL_VERSION) {
  921. printk("GDT-EISA: Illegal protocol version\n");
  922. return 0;
  923. }
  924. ha->bmic = eisa_adr;
  925. ha->brd_phys = (ulong32)eisa_adr >> 12;
  926. outl(0,eisa_adr+MAILBOXREG);
  927. outl(0,eisa_adr+MAILBOXREG+4);
  928. outl(0,eisa_adr+MAILBOXREG+8);
  929. outl(0,eisa_adr+MAILBOXREG+12);
  930. /* detect IRQ */
  931. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  932. ha->oem_id = OEM_ID_ICP;
  933. ha->type = GDT_EISA;
  934. ha->stype = id;
  935. outl(1,eisa_adr+MAILBOXREG+8);
  936. outb(0xfe,eisa_adr+LDOORREG);
  937. retries = INIT_RETRIES;
  938. gdth_delay(20);
  939. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  940. if (--retries == 0) {
  941. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  942. return 0;
  943. }
  944. gdth_delay(1);
  945. }
  946. ha->irq = inb(eisa_adr+MAILBOXREG);
  947. outb(0xff,eisa_adr+EDOORREG);
  948. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  949. /* check the result */
  950. if (ha->irq == 0) {
  951. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  952. for (i = 0, irq_found = FALSE;
  953. i < MAXHA && irq[i] != 0xff; ++i) {
  954. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  955. irq_found = TRUE;
  956. break;
  957. }
  958. }
  959. if (irq_found) {
  960. ha->irq = irq[i];
  961. irq[i] = 0;
  962. printk("GDT-EISA: Can not detect controller IRQ,\n");
  963. printk("Use IRQ setting from command line (IRQ = %d)\n",
  964. ha->irq);
  965. } else {
  966. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  967. printk("the controller BIOS or use command line parameters\n");
  968. return 0;
  969. }
  970. }
  971. } else {
  972. eisacf = inb(eisa_adr+EISAREG) & 7;
  973. if (eisacf > 4) /* level triggered */
  974. eisacf -= 4;
  975. ha->irq = gdth_irq_tab[eisacf];
  976. ha->oem_id = OEM_ID_ICP;
  977. ha->type = GDT_EISA;
  978. ha->stype = id;
  979. }
  980. ha->dma64_support = 0;
  981. return 1;
  982. }
  983. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  984. {
  985. register gdt2_dpram_str __iomem *dp2_ptr;
  986. int i;
  987. unchar irq_drq,prot_ver;
  988. ulong32 retries;
  989. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  990. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  991. if (ha->brd == NULL) {
  992. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  993. return 0;
  994. }
  995. dp2_ptr = ha->brd;
  996. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  997. /* reset interface area */
  998. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  999. if (gdth_readl(&dp2_ptr->u) != 0) {
  1000. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  1001. iounmap(ha->brd);
  1002. return 0;
  1003. }
  1004. /* disable board interrupts, read DRQ and IRQ */
  1005. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1006. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  1007. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  1008. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  1009. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  1010. for (i=0; i<3; ++i) {
  1011. if ((irq_drq & 1)==0)
  1012. break;
  1013. irq_drq >>= 1;
  1014. }
  1015. ha->drq = gdth_drq_tab[i];
  1016. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  1017. for (i=1; i<5; ++i) {
  1018. if ((irq_drq & 1)==0)
  1019. break;
  1020. irq_drq >>= 1;
  1021. }
  1022. ha->irq = gdth_irq_tab[i];
  1023. /* deinitialize services */
  1024. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  1025. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  1026. gdth_writeb(0, &dp2_ptr->io.event);
  1027. retries = INIT_RETRIES;
  1028. gdth_delay(20);
  1029. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  1030. if (--retries == 0) {
  1031. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  1032. iounmap(ha->brd);
  1033. return 0;
  1034. }
  1035. gdth_delay(1);
  1036. }
  1037. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  1038. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1039. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1040. if (prot_ver != PROTOCOL_VERSION) {
  1041. printk("GDT-ISA: Illegal protocol version\n");
  1042. iounmap(ha->brd);
  1043. return 0;
  1044. }
  1045. ha->oem_id = OEM_ID_ICP;
  1046. ha->type = GDT_ISA;
  1047. ha->ic_all_size = sizeof(dp2_ptr->u);
  1048. ha->stype= GDT2_ID;
  1049. ha->brd_phys = bios_adr >> 4;
  1050. /* special request to controller BIOS */
  1051. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  1052. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  1053. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  1054. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  1055. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  1056. gdth_writeb(0, &dp2_ptr->io.event);
  1057. retries = INIT_RETRIES;
  1058. gdth_delay(20);
  1059. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  1060. if (--retries == 0) {
  1061. printk("GDT-ISA: Initialization error\n");
  1062. iounmap(ha->brd);
  1063. return 0;
  1064. }
  1065. gdth_delay(1);
  1066. }
  1067. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1068. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1069. ha->dma64_support = 0;
  1070. return 1;
  1071. }
  1072. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  1073. {
  1074. register gdt6_dpram_str __iomem *dp6_ptr;
  1075. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1076. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1077. ulong32 retries;
  1078. unchar prot_ver;
  1079. ushort command;
  1080. int i, found = FALSE;
  1081. TRACE(("gdth_init_pci()\n"));
  1082. if (pcistr->vendor_id == PCI_VENDOR_ID_INTEL)
  1083. ha->oem_id = OEM_ID_INTEL;
  1084. else
  1085. ha->oem_id = OEM_ID_ICP;
  1086. ha->brd_phys = (pcistr->bus << 8) | (pcistr->device_fn & 0xf8);
  1087. ha->stype = (ulong32)pcistr->device_id;
  1088. ha->subdevice_id = pcistr->subdevice_id;
  1089. ha->irq = pcistr->irq;
  1090. ha->pdev = pcistr->pdev;
  1091. if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  1092. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1093. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  1094. if (ha->brd == NULL) {
  1095. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1096. return 0;
  1097. }
  1098. /* check and reset interface area */
  1099. dp6_ptr = ha->brd;
  1100. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1101. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1102. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1103. pcistr->dpmem);
  1104. found = FALSE;
  1105. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1106. iounmap(ha->brd);
  1107. ha->brd = ioremap(i, sizeof(ushort));
  1108. if (ha->brd == NULL) {
  1109. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1110. return 0;
  1111. }
  1112. if (gdth_readw(ha->brd) != 0xffff) {
  1113. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1114. continue;
  1115. }
  1116. iounmap(ha->brd);
  1117. pci_write_config_dword(pcistr->pdev,
  1118. PCI_BASE_ADDRESS_0, i);
  1119. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1120. if (ha->brd == NULL) {
  1121. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1122. return 0;
  1123. }
  1124. dp6_ptr = ha->brd;
  1125. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1126. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1127. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1128. found = TRUE;
  1129. break;
  1130. }
  1131. }
  1132. if (!found) {
  1133. printk("GDT-PCI: No free address found!\n");
  1134. iounmap(ha->brd);
  1135. return 0;
  1136. }
  1137. }
  1138. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1139. if (gdth_readl(&dp6_ptr->u) != 0) {
  1140. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1141. iounmap(ha->brd);
  1142. return 0;
  1143. }
  1144. /* disable board interrupts, deinit services */
  1145. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1146. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1147. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1148. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1149. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1150. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1151. gdth_writeb(0, &dp6_ptr->io.event);
  1152. retries = INIT_RETRIES;
  1153. gdth_delay(20);
  1154. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1155. if (--retries == 0) {
  1156. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1157. iounmap(ha->brd);
  1158. return 0;
  1159. }
  1160. gdth_delay(1);
  1161. }
  1162. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1163. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1164. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1165. if (prot_ver != PROTOCOL_VERSION) {
  1166. printk("GDT-PCI: Illegal protocol version\n");
  1167. iounmap(ha->brd);
  1168. return 0;
  1169. }
  1170. ha->type = GDT_PCI;
  1171. ha->ic_all_size = sizeof(dp6_ptr->u);
  1172. /* special command to controller BIOS */
  1173. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1174. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1175. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1176. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1177. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1178. gdth_writeb(0, &dp6_ptr->io.event);
  1179. retries = INIT_RETRIES;
  1180. gdth_delay(20);
  1181. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1182. if (--retries == 0) {
  1183. printk("GDT-PCI: Initialization error\n");
  1184. iounmap(ha->brd);
  1185. return 0;
  1186. }
  1187. gdth_delay(1);
  1188. }
  1189. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1190. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1191. ha->dma64_support = 0;
  1192. } else if (ha->stype <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1193. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1194. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1195. pcistr->dpmem,ha->irq));
  1196. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1197. if (ha->brd == NULL) {
  1198. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1199. iounmap(ha->brd);
  1200. return 0;
  1201. }
  1202. /* check and reset interface area */
  1203. dp6c_ptr = ha->brd;
  1204. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1205. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1206. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1207. pcistr->dpmem);
  1208. found = FALSE;
  1209. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1210. iounmap(ha->brd);
  1211. ha->brd = ioremap(i, sizeof(ushort));
  1212. if (ha->brd == NULL) {
  1213. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1214. return 0;
  1215. }
  1216. if (gdth_readw(ha->brd) != 0xffff) {
  1217. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1218. continue;
  1219. }
  1220. iounmap(ha->brd);
  1221. pci_write_config_dword(pcistr->pdev,
  1222. PCI_BASE_ADDRESS_2, i);
  1223. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1224. if (ha->brd == NULL) {
  1225. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1226. return 0;
  1227. }
  1228. dp6c_ptr = ha->brd;
  1229. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1230. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1231. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1232. found = TRUE;
  1233. break;
  1234. }
  1235. }
  1236. if (!found) {
  1237. printk("GDT-PCI: No free address found!\n");
  1238. iounmap(ha->brd);
  1239. return 0;
  1240. }
  1241. }
  1242. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1243. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1244. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1245. iounmap(ha->brd);
  1246. return 0;
  1247. }
  1248. /* disable board interrupts, deinit services */
  1249. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1250. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1251. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1252. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1253. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1254. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1255. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1256. retries = INIT_RETRIES;
  1257. gdth_delay(20);
  1258. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1259. if (--retries == 0) {
  1260. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1261. iounmap(ha->brd);
  1262. return 0;
  1263. }
  1264. gdth_delay(1);
  1265. }
  1266. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1267. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1268. if (prot_ver != PROTOCOL_VERSION) {
  1269. printk("GDT-PCI: Illegal protocol version\n");
  1270. iounmap(ha->brd);
  1271. return 0;
  1272. }
  1273. ha->type = GDT_PCINEW;
  1274. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1275. /* special command to controller BIOS */
  1276. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1277. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1278. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1279. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1280. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1281. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1282. retries = INIT_RETRIES;
  1283. gdth_delay(20);
  1284. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1285. if (--retries == 0) {
  1286. printk("GDT-PCI: Initialization error\n");
  1287. iounmap(ha->brd);
  1288. return 0;
  1289. }
  1290. gdth_delay(1);
  1291. }
  1292. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1293. ha->dma64_support = 0;
  1294. } else { /* MPR */
  1295. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1296. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1297. if (ha->brd == NULL) {
  1298. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1299. return 0;
  1300. }
  1301. /* manipulate config. space to enable DPMEM, start RP controller */
  1302. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1303. command |= 6;
  1304. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1305. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1306. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1307. i = 0xFEFF0001UL;
  1308. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1309. gdth_delay(1);
  1310. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1311. pci_resource_start(pcistr->pdev, 8));
  1312. dp6m_ptr = ha->brd;
  1313. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1314. * Aditional check needed for Xscale based RAID controllers */
  1315. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1316. gdth_delay(1);
  1317. /* check and reset interface area */
  1318. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1319. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1320. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1321. pcistr->dpmem);
  1322. found = FALSE;
  1323. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1324. iounmap(ha->brd);
  1325. ha->brd = ioremap(i, sizeof(ushort));
  1326. if (ha->brd == NULL) {
  1327. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1328. return 0;
  1329. }
  1330. if (gdth_readw(ha->brd) != 0xffff) {
  1331. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1332. continue;
  1333. }
  1334. iounmap(ha->brd);
  1335. pci_write_config_dword(pcistr->pdev,
  1336. PCI_BASE_ADDRESS_0, i);
  1337. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1338. if (ha->brd == NULL) {
  1339. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1340. return 0;
  1341. }
  1342. dp6m_ptr = ha->brd;
  1343. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1344. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1345. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1346. found = TRUE;
  1347. break;
  1348. }
  1349. }
  1350. if (!found) {
  1351. printk("GDT-PCI: No free address found!\n");
  1352. iounmap(ha->brd);
  1353. return 0;
  1354. }
  1355. }
  1356. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1357. /* disable board interrupts, deinit services */
  1358. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1359. &dp6m_ptr->i960r.edoor_en_reg);
  1360. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1361. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1362. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1363. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1364. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1365. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1366. retries = INIT_RETRIES;
  1367. gdth_delay(20);
  1368. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1369. if (--retries == 0) {
  1370. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1371. iounmap(ha->brd);
  1372. return 0;
  1373. }
  1374. gdth_delay(1);
  1375. }
  1376. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1377. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1378. if (prot_ver != PROTOCOL_VERSION) {
  1379. printk("GDT-PCI: Illegal protocol version\n");
  1380. iounmap(ha->brd);
  1381. return 0;
  1382. }
  1383. ha->type = GDT_PCIMPR;
  1384. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1385. /* special command to controller BIOS */
  1386. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1387. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1388. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1389. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1390. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1391. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1392. retries = INIT_RETRIES;
  1393. gdth_delay(20);
  1394. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1395. if (--retries == 0) {
  1396. printk("GDT-PCI: Initialization error\n");
  1397. iounmap(ha->brd);
  1398. return 0;
  1399. }
  1400. gdth_delay(1);
  1401. }
  1402. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1403. /* read FW version to detect 64-bit DMA support */
  1404. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1405. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1406. retries = INIT_RETRIES;
  1407. gdth_delay(20);
  1408. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1409. if (--retries == 0) {
  1410. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1411. iounmap(ha->brd);
  1412. return 0;
  1413. }
  1414. gdth_delay(1);
  1415. }
  1416. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1417. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1418. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1419. ha->dma64_support = 0;
  1420. else
  1421. ha->dma64_support = 1;
  1422. }
  1423. return 1;
  1424. }
  1425. /* controller protocol functions */
  1426. static void __init gdth_enable_int(int hanum)
  1427. {
  1428. gdth_ha_str *ha;
  1429. ulong flags;
  1430. gdt2_dpram_str __iomem *dp2_ptr;
  1431. gdt6_dpram_str __iomem *dp6_ptr;
  1432. gdt6m_dpram_str __iomem *dp6m_ptr;
  1433. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1434. ha = HADATA(gdth_ctr_tab[hanum]);
  1435. spin_lock_irqsave(&ha->smp_lock, flags);
  1436. if (ha->type == GDT_EISA) {
  1437. outb(0xff, ha->bmic + EDOORREG);
  1438. outb(0xff, ha->bmic + EDENABREG);
  1439. outb(0x01, ha->bmic + EINTENABREG);
  1440. } else if (ha->type == GDT_ISA) {
  1441. dp2_ptr = ha->brd;
  1442. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1443. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1444. gdth_writeb(1, &dp2_ptr->io.irqen);
  1445. } else if (ha->type == GDT_PCI) {
  1446. dp6_ptr = ha->brd;
  1447. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1448. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1449. gdth_writeb(1, &dp6_ptr->io.irqen);
  1450. } else if (ha->type == GDT_PCINEW) {
  1451. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1452. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1453. } else if (ha->type == GDT_PCIMPR) {
  1454. dp6m_ptr = ha->brd;
  1455. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1456. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1457. &dp6m_ptr->i960r.edoor_en_reg);
  1458. }
  1459. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1460. }
  1461. static int gdth_get_status(unchar *pIStatus,int irq)
  1462. {
  1463. register gdth_ha_str *ha;
  1464. int i;
  1465. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1466. irq,gdth_ctr_count));
  1467. *pIStatus = 0;
  1468. for (i=0; i<gdth_ctr_count; ++i) {
  1469. ha = HADATA(gdth_ctr_tab[i]);
  1470. if (ha->irq != (unchar)irq) /* check IRQ */
  1471. continue;
  1472. if (ha->type == GDT_EISA)
  1473. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1474. else if (ha->type == GDT_ISA)
  1475. *pIStatus =
  1476. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1477. else if (ha->type == GDT_PCI)
  1478. *pIStatus =
  1479. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1480. else if (ha->type == GDT_PCINEW)
  1481. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1482. else if (ha->type == GDT_PCIMPR)
  1483. *pIStatus =
  1484. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1485. if (*pIStatus)
  1486. return i; /* board found */
  1487. }
  1488. return -1;
  1489. }
  1490. static int gdth_test_busy(int hanum)
  1491. {
  1492. register gdth_ha_str *ha;
  1493. register int gdtsema0 = 0;
  1494. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1495. ha = HADATA(gdth_ctr_tab[hanum]);
  1496. if (ha->type == GDT_EISA)
  1497. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1498. else if (ha->type == GDT_ISA)
  1499. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1500. else if (ha->type == GDT_PCI)
  1501. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1502. else if (ha->type == GDT_PCINEW)
  1503. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1504. else if (ha->type == GDT_PCIMPR)
  1505. gdtsema0 =
  1506. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1507. return (gdtsema0 & 1);
  1508. }
  1509. static int gdth_get_cmd_index(int hanum)
  1510. {
  1511. register gdth_ha_str *ha;
  1512. int i;
  1513. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1514. ha = HADATA(gdth_ctr_tab[hanum]);
  1515. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1516. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1517. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1518. ha->cmd_tab[i].service = ha->pccb->Service;
  1519. ha->pccb->CommandIndex = (ulong32)i+2;
  1520. return (i+2);
  1521. }
  1522. }
  1523. return 0;
  1524. }
  1525. static void gdth_set_sema0(int hanum)
  1526. {
  1527. register gdth_ha_str *ha;
  1528. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1529. ha = HADATA(gdth_ctr_tab[hanum]);
  1530. if (ha->type == GDT_EISA) {
  1531. outb(1, ha->bmic + SEMA0REG);
  1532. } else if (ha->type == GDT_ISA) {
  1533. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1534. } else if (ha->type == GDT_PCI) {
  1535. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1536. } else if (ha->type == GDT_PCINEW) {
  1537. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1538. } else if (ha->type == GDT_PCIMPR) {
  1539. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1540. }
  1541. }
  1542. static void gdth_copy_command(int hanum)
  1543. {
  1544. register gdth_ha_str *ha;
  1545. register gdth_cmd_str *cmd_ptr;
  1546. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1547. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1548. gdt6_dpram_str __iomem *dp6_ptr;
  1549. gdt2_dpram_str __iomem *dp2_ptr;
  1550. ushort cp_count,dp_offset,cmd_no;
  1551. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1552. ha = HADATA(gdth_ctr_tab[hanum]);
  1553. cp_count = ha->cmd_len;
  1554. dp_offset= ha->cmd_offs_dpmem;
  1555. cmd_no = ha->cmd_cnt;
  1556. cmd_ptr = ha->pccb;
  1557. ++ha->cmd_cnt;
  1558. if (ha->type == GDT_EISA)
  1559. return; /* no DPMEM, no copy */
  1560. /* set cpcount dword aligned */
  1561. if (cp_count & 3)
  1562. cp_count += (4 - (cp_count & 3));
  1563. ha->cmd_offs_dpmem += cp_count;
  1564. /* set offset and service, copy command to DPMEM */
  1565. if (ha->type == GDT_ISA) {
  1566. dp2_ptr = ha->brd;
  1567. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1568. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1569. gdth_writew((ushort)cmd_ptr->Service,
  1570. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1571. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1572. } else if (ha->type == GDT_PCI) {
  1573. dp6_ptr = ha->brd;
  1574. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1575. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1576. gdth_writew((ushort)cmd_ptr->Service,
  1577. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1578. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1579. } else if (ha->type == GDT_PCINEW) {
  1580. dp6c_ptr = ha->brd;
  1581. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1582. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1583. gdth_writew((ushort)cmd_ptr->Service,
  1584. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1585. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1586. } else if (ha->type == GDT_PCIMPR) {
  1587. dp6m_ptr = ha->brd;
  1588. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1589. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1590. gdth_writew((ushort)cmd_ptr->Service,
  1591. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1592. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1593. }
  1594. }
  1595. static void gdth_release_event(int hanum)
  1596. {
  1597. register gdth_ha_str *ha;
  1598. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1599. ha = HADATA(gdth_ctr_tab[hanum]);
  1600. #ifdef GDTH_STATISTICS
  1601. {
  1602. ulong32 i,j;
  1603. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1604. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1605. ++i;
  1606. }
  1607. if (max_index < i) {
  1608. max_index = i;
  1609. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1610. }
  1611. }
  1612. #endif
  1613. if (ha->pccb->OpCode == GDT_INIT)
  1614. ha->pccb->Service |= 0x80;
  1615. if (ha->type == GDT_EISA) {
  1616. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1617. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1618. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1619. } else if (ha->type == GDT_ISA) {
  1620. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1621. } else if (ha->type == GDT_PCI) {
  1622. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1623. } else if (ha->type == GDT_PCINEW) {
  1624. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1625. } else if (ha->type == GDT_PCIMPR) {
  1626. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1627. }
  1628. }
  1629. static int gdth_wait(int hanum,int index,ulong32 time)
  1630. {
  1631. gdth_ha_str *ha;
  1632. int answer_found = FALSE;
  1633. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1634. ha = HADATA(gdth_ctr_tab[hanum]);
  1635. if (index == 0)
  1636. return 1; /* no wait required */
  1637. gdth_from_wait = TRUE;
  1638. do {
  1639. gdth_interrupt((int)ha->irq,ha);
  1640. if (wait_hanum==hanum && wait_index==index) {
  1641. answer_found = TRUE;
  1642. break;
  1643. }
  1644. gdth_delay(1);
  1645. } while (--time);
  1646. gdth_from_wait = FALSE;
  1647. while (gdth_test_busy(hanum))
  1648. gdth_delay(0);
  1649. return (answer_found);
  1650. }
  1651. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1652. ulong64 p2,ulong64 p3)
  1653. {
  1654. register gdth_ha_str *ha;
  1655. register gdth_cmd_str *cmd_ptr;
  1656. int retries,index;
  1657. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1658. ha = HADATA(gdth_ctr_tab[hanum]);
  1659. cmd_ptr = ha->pccb;
  1660. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1661. /* make command */
  1662. for (retries = INIT_RETRIES;;) {
  1663. cmd_ptr->Service = service;
  1664. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1665. if (!(index=gdth_get_cmd_index(hanum))) {
  1666. TRACE(("GDT: No free command index found\n"));
  1667. return 0;
  1668. }
  1669. gdth_set_sema0(hanum);
  1670. cmd_ptr->OpCode = opcode;
  1671. cmd_ptr->BoardNode = LOCALBOARD;
  1672. if (service == CACHESERVICE) {
  1673. if (opcode == GDT_IOCTL) {
  1674. cmd_ptr->u.ioctl.subfunc = p1;
  1675. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1676. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1677. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1678. } else {
  1679. if (ha->cache_feat & GDT_64BIT) {
  1680. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1681. cmd_ptr->u.cache64.BlockNo = p2;
  1682. } else {
  1683. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1684. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1685. }
  1686. }
  1687. } else if (service == SCSIRAWSERVICE) {
  1688. if (ha->raw_feat & GDT_64BIT) {
  1689. cmd_ptr->u.raw64.direction = p1;
  1690. cmd_ptr->u.raw64.bus = (unchar)p2;
  1691. cmd_ptr->u.raw64.target = (unchar)p3;
  1692. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1693. } else {
  1694. cmd_ptr->u.raw.direction = p1;
  1695. cmd_ptr->u.raw.bus = (unchar)p2;
  1696. cmd_ptr->u.raw.target = (unchar)p3;
  1697. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1698. }
  1699. } else if (service == SCREENSERVICE) {
  1700. if (opcode == GDT_REALTIME) {
  1701. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1702. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1703. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1704. }
  1705. }
  1706. ha->cmd_len = sizeof(gdth_cmd_str);
  1707. ha->cmd_offs_dpmem = 0;
  1708. ha->cmd_cnt = 0;
  1709. gdth_copy_command(hanum);
  1710. gdth_release_event(hanum);
  1711. gdth_delay(20);
  1712. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1713. printk("GDT: Initialization error (timeout service %d)\n",service);
  1714. return 0;
  1715. }
  1716. if (ha->status != S_BSY || --retries == 0)
  1717. break;
  1718. gdth_delay(1);
  1719. }
  1720. return (ha->status != S_OK ? 0:1);
  1721. }
  1722. /* search for devices */
  1723. static int __init gdth_search_drives(int hanum)
  1724. {
  1725. register gdth_ha_str *ha;
  1726. ushort cdev_cnt, i;
  1727. int ok;
  1728. ulong32 bus_no, drv_cnt, drv_no, j;
  1729. gdth_getch_str *chn;
  1730. gdth_drlist_str *drl;
  1731. gdth_iochan_str *ioc;
  1732. gdth_raw_iochan_str *iocr;
  1733. gdth_arcdl_str *alst;
  1734. gdth_alist_str *alst2;
  1735. gdth_oem_str_ioctl *oemstr;
  1736. #ifdef INT_COAL
  1737. gdth_perf_modes *pmod;
  1738. #endif
  1739. #ifdef GDTH_RTC
  1740. unchar rtc[12];
  1741. ulong flags;
  1742. #endif
  1743. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1744. ha = HADATA(gdth_ctr_tab[hanum]);
  1745. ok = 0;
  1746. /* initialize controller services, at first: screen service */
  1747. ha->screen_feat = 0;
  1748. if (!force_dma32) {
  1749. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1750. if (ok)
  1751. ha->screen_feat = GDT_64BIT;
  1752. }
  1753. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1754. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1755. if (!ok) {
  1756. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1757. hanum, ha->status);
  1758. return 0;
  1759. }
  1760. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1761. #ifdef GDTH_RTC
  1762. /* read realtime clock info, send to controller */
  1763. /* 1. wait for the falling edge of update flag */
  1764. spin_lock_irqsave(&rtc_lock, flags);
  1765. for (j = 0; j < 1000000; ++j)
  1766. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1767. break;
  1768. for (j = 0; j < 1000000; ++j)
  1769. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1770. break;
  1771. /* 2. read info */
  1772. do {
  1773. for (j = 0; j < 12; ++j)
  1774. rtc[j] = CMOS_READ(j);
  1775. } while (rtc[0] != CMOS_READ(0));
  1776. spin_lock_irqrestore(&rtc_lock, flags);
  1777. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1778. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1779. /* 3. send to controller firmware */
  1780. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1781. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1782. #endif
  1783. /* unfreeze all IOs */
  1784. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1785. /* initialize cache service */
  1786. ha->cache_feat = 0;
  1787. if (!force_dma32) {
  1788. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1789. if (ok)
  1790. ha->cache_feat = GDT_64BIT;
  1791. }
  1792. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1793. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1794. if (!ok) {
  1795. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1796. hanum, ha->status);
  1797. return 0;
  1798. }
  1799. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1800. cdev_cnt = (ushort)ha->info;
  1801. ha->fw_vers = ha->service;
  1802. #ifdef INT_COAL
  1803. if (ha->type == GDT_PCIMPR) {
  1804. /* set perf. modes */
  1805. pmod = (gdth_perf_modes *)ha->pscratch;
  1806. pmod->version = 1;
  1807. pmod->st_mode = 1; /* enable one status buffer */
  1808. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1809. pmod->st_buff_indx1 = COALINDEX;
  1810. pmod->st_buff_addr2 = 0;
  1811. pmod->st_buff_u_addr2 = 0;
  1812. pmod->st_buff_indx2 = 0;
  1813. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1814. pmod->cmd_mode = 0; // disable all cmd buffers
  1815. pmod->cmd_buff_addr1 = 0;
  1816. pmod->cmd_buff_u_addr1 = 0;
  1817. pmod->cmd_buff_indx1 = 0;
  1818. pmod->cmd_buff_addr2 = 0;
  1819. pmod->cmd_buff_u_addr2 = 0;
  1820. pmod->cmd_buff_indx2 = 0;
  1821. pmod->cmd_buff_size = 0;
  1822. pmod->reserved1 = 0;
  1823. pmod->reserved2 = 0;
  1824. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1825. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1826. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1827. }
  1828. }
  1829. #endif
  1830. /* detect number of buses - try new IOCTL */
  1831. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1832. iocr->hdr.version = 0xffffffff;
  1833. iocr->hdr.list_entries = MAXBUS;
  1834. iocr->hdr.first_chan = 0;
  1835. iocr->hdr.last_chan = MAXBUS-1;
  1836. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1837. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1838. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1839. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1840. ha->bus_cnt = iocr->hdr.chan_count;
  1841. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1842. if (iocr->list[bus_no].proc_id < MAXID)
  1843. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1844. else
  1845. ha->bus_id[bus_no] = 0xff;
  1846. }
  1847. } else {
  1848. /* old method */
  1849. chn = (gdth_getch_str *)ha->pscratch;
  1850. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1851. chn->channel_no = bus_no;
  1852. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1853. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1854. IO_CHANNEL | INVALID_CHANNEL,
  1855. sizeof(gdth_getch_str))) {
  1856. if (bus_no == 0) {
  1857. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1858. hanum, ha->status);
  1859. return 0;
  1860. }
  1861. break;
  1862. }
  1863. if (chn->siop_id < MAXID)
  1864. ha->bus_id[bus_no] = chn->siop_id;
  1865. else
  1866. ha->bus_id[bus_no] = 0xff;
  1867. }
  1868. ha->bus_cnt = (unchar)bus_no;
  1869. }
  1870. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1871. /* read cache configuration */
  1872. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1873. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1874. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1875. hanum, ha->status);
  1876. return 0;
  1877. }
  1878. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1879. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1880. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1881. ha->cpar.write_back,ha->cpar.block_size));
  1882. /* read board info and features */
  1883. ha->more_proc = FALSE;
  1884. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1885. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1886. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1887. sizeof(gdth_binfo_str));
  1888. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1889. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1890. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1891. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1892. ha->more_proc = TRUE;
  1893. }
  1894. } else {
  1895. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1896. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1897. }
  1898. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1899. /* read more informations */
  1900. if (ha->more_proc) {
  1901. /* physical drives, channel addresses */
  1902. ioc = (gdth_iochan_str *)ha->pscratch;
  1903. ioc->hdr.version = 0xffffffff;
  1904. ioc->hdr.list_entries = MAXBUS;
  1905. ioc->hdr.first_chan = 0;
  1906. ioc->hdr.last_chan = MAXBUS-1;
  1907. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1908. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1909. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1910. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1911. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1912. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1913. }
  1914. } else {
  1915. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1916. ha->raw[bus_no].address = IO_CHANNEL;
  1917. ha->raw[bus_no].local_no = bus_no;
  1918. }
  1919. }
  1920. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1921. chn = (gdth_getch_str *)ha->pscratch;
  1922. chn->channel_no = ha->raw[bus_no].local_no;
  1923. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1924. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1925. ha->raw[bus_no].address | INVALID_CHANNEL,
  1926. sizeof(gdth_getch_str))) {
  1927. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1928. TRACE2(("Channel %d: %d phys. drives\n",
  1929. bus_no,chn->drive_cnt));
  1930. }
  1931. if (ha->raw[bus_no].pdev_cnt > 0) {
  1932. drl = (gdth_drlist_str *)ha->pscratch;
  1933. drl->sc_no = ha->raw[bus_no].local_no;
  1934. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1935. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1936. SCSI_DR_LIST | L_CTRL_PATTERN,
  1937. ha->raw[bus_no].address | INVALID_CHANNEL,
  1938. sizeof(gdth_drlist_str))) {
  1939. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1940. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1941. } else {
  1942. ha->raw[bus_no].pdev_cnt = 0;
  1943. }
  1944. }
  1945. }
  1946. /* logical drives */
  1947. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1948. INVALID_CHANNEL,sizeof(ulong32))) {
  1949. drv_cnt = *(ulong32 *)ha->pscratch;
  1950. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1951. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1952. for (j = 0; j < drv_cnt; ++j) {
  1953. drv_no = ((ulong32 *)ha->pscratch)[j];
  1954. if (drv_no < MAX_LDRIVES) {
  1955. ha->hdr[drv_no].is_logdrv = TRUE;
  1956. TRACE2(("Drive %d is log. drive\n",drv_no));
  1957. }
  1958. }
  1959. }
  1960. alst = (gdth_arcdl_str *)ha->pscratch;
  1961. alst->entries_avail = MAX_LDRIVES;
  1962. alst->first_entry = 0;
  1963. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1964. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1965. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1966. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1967. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1968. for (j = 0; j < alst->entries_init; ++j) {
  1969. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1970. ha->hdr[j].is_master = alst->list[j].is_master;
  1971. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1972. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1973. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1974. }
  1975. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1976. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1977. 0, 35 * sizeof(gdth_alist_str))) {
  1978. for (j = 0; j < 35; ++j) {
  1979. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1980. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1981. ha->hdr[j].is_master = alst2->is_master;
  1982. ha->hdr[j].is_parity = alst2->is_parity;
  1983. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1984. ha->hdr[j].master_no = alst2->cd_handle;
  1985. }
  1986. }
  1987. }
  1988. }
  1989. /* initialize raw service */
  1990. ha->raw_feat = 0;
  1991. if (!force_dma32) {
  1992. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  1993. if (ok)
  1994. ha->raw_feat = GDT_64BIT;
  1995. }
  1996. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1997. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  1998. if (!ok) {
  1999. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  2000. hanum, ha->status);
  2001. return 0;
  2002. }
  2003. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  2004. /* set/get features raw service (scatter/gather) */
  2005. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  2006. 0,0)) {
  2007. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  2008. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  2009. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  2010. ha->info));
  2011. ha->raw_feat |= (ushort)ha->info;
  2012. }
  2013. }
  2014. /* set/get features cache service (equal to raw service) */
  2015. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  2016. SCATTER_GATHER,0)) {
  2017. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  2018. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  2019. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  2020. ha->info));
  2021. ha->cache_feat |= (ushort)ha->info;
  2022. }
  2023. }
  2024. /* reserve drives for raw service */
  2025. if (reserve_mode != 0) {
  2026. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  2027. reserve_mode == 1 ? 1 : 3, 0, 0);
  2028. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  2029. ha->status));
  2030. }
  2031. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  2032. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  2033. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  2034. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  2035. reserve_list[i], reserve_list[i+1],
  2036. reserve_list[i+2], reserve_list[i+3]));
  2037. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  2038. reserve_list[i+1], reserve_list[i+2] |
  2039. (reserve_list[i+3] << 8))) {
  2040. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  2041. hanum, ha->status);
  2042. }
  2043. }
  2044. }
  2045. /* Determine OEM string using IOCTL */
  2046. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  2047. oemstr->params.ctl_version = 0x01;
  2048. oemstr->params.buffer_size = sizeof(oemstr->text);
  2049. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  2050. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  2051. sizeof(gdth_oem_str_ioctl))) {
  2052. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  2053. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  2054. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  2055. /* Save the Host Drive inquiry data */
  2056. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2057. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  2058. sizeof(ha->oem_name));
  2059. #else
  2060. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  2061. ha->oem_name[7] = '\0';
  2062. #endif
  2063. } else {
  2064. /* Old method, based on PCI ID */
  2065. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  2066. printk("GDT-HA %d: Name: %s\n",
  2067. hanum,ha->binfo.type_string);
  2068. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2069. if (ha->oem_id == OEM_ID_INTEL)
  2070. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  2071. else
  2072. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  2073. #else
  2074. if (ha->oem_id == OEM_ID_INTEL)
  2075. strcpy(ha->oem_name,"Intel ");
  2076. else
  2077. strcpy(ha->oem_name,"ICP ");
  2078. #endif
  2079. }
  2080. /* scanning for host drives */
  2081. for (i = 0; i < cdev_cnt; ++i)
  2082. gdth_analyse_hdrive(hanum,i);
  2083. TRACE(("gdth_search_drives() OK\n"));
  2084. return 1;
  2085. }
  2086. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  2087. {
  2088. register gdth_ha_str *ha;
  2089. ulong32 drv_cyls;
  2090. int drv_hds, drv_secs;
  2091. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  2092. if (hdrive >= MAX_HDRIVES)
  2093. return 0;
  2094. ha = HADATA(gdth_ctr_tab[hanum]);
  2095. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  2096. return 0;
  2097. ha->hdr[hdrive].present = TRUE;
  2098. ha->hdr[hdrive].size = ha->info;
  2099. /* evaluate mapping (sectors per head, heads per cylinder) */
  2100. ha->hdr[hdrive].size &= ~SECS32;
  2101. if (ha->info2 == 0) {
  2102. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2103. } else {
  2104. drv_hds = ha->info2 & 0xff;
  2105. drv_secs = (ha->info2 >> 8) & 0xff;
  2106. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2107. }
  2108. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2109. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2110. /* round size */
  2111. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2112. if (ha->cache_feat & GDT_64BIT) {
  2113. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2114. && ha->info2 != 0) {
  2115. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2116. }
  2117. }
  2118. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2119. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2120. /* get informations about device */
  2121. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2122. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2123. hdrive,ha->info));
  2124. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2125. }
  2126. /* cluster info */
  2127. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2128. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2129. hdrive,ha->info));
  2130. if (!shared_access)
  2131. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2132. }
  2133. /* R/W attributes */
  2134. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2135. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2136. hdrive,ha->info));
  2137. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2138. }
  2139. return 1;
  2140. }
  2141. /* command queueing/sending functions */
  2142. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2143. {
  2144. register gdth_ha_str *ha;
  2145. register Scsi_Cmnd *pscp;
  2146. register Scsi_Cmnd *nscp;
  2147. ulong flags;
  2148. unchar b, t;
  2149. TRACE(("gdth_putq() priority %d\n",priority));
  2150. ha = HADATA(gdth_ctr_tab[hanum]);
  2151. spin_lock_irqsave(&ha->smp_lock, flags);
  2152. if (scp->done != gdth_scsi_done) {
  2153. scp->SCp.this_residual = (int)priority;
  2154. b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
  2155. t = scp->device->id;
  2156. if (priority >= DEFAULT_PRI) {
  2157. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2158. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  2159. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  2160. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2161. }
  2162. }
  2163. }
  2164. if (ha->req_first==NULL) {
  2165. ha->req_first = scp; /* queue was empty */
  2166. scp->SCp.ptr = NULL;
  2167. } else { /* queue not empty */
  2168. pscp = ha->req_first;
  2169. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2170. /* priority: 0-highest,..,0xff-lowest */
  2171. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2172. pscp = nscp;
  2173. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2174. }
  2175. pscp->SCp.ptr = (char *)scp;
  2176. scp->SCp.ptr = (char *)nscp;
  2177. }
  2178. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2179. #ifdef GDTH_STATISTICS
  2180. flags = 0;
  2181. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2182. ++flags;
  2183. if (max_rq < flags) {
  2184. max_rq = flags;
  2185. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2186. }
  2187. #endif
  2188. }
  2189. static void gdth_next(int hanum)
  2190. {
  2191. register gdth_ha_str *ha;
  2192. register Scsi_Cmnd *pscp;
  2193. register Scsi_Cmnd *nscp;
  2194. unchar b, t, l, firsttime;
  2195. unchar this_cmd, next_cmd;
  2196. ulong flags = 0;
  2197. int cmd_index;
  2198. TRACE(("gdth_next() hanum %d\n",hanum));
  2199. ha = HADATA(gdth_ctr_tab[hanum]);
  2200. if (!gdth_polling)
  2201. spin_lock_irqsave(&ha->smp_lock, flags);
  2202. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2203. this_cmd = firsttime = TRUE;
  2204. next_cmd = gdth_polling ? FALSE:TRUE;
  2205. cmd_index = 0;
  2206. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2207. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2208. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2209. if (nscp->done != gdth_scsi_done) {
  2210. b = virt_ctr ?
  2211. NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2212. t = nscp->device->id;
  2213. l = nscp->device->lun;
  2214. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2215. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2216. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2217. continue;
  2218. }
  2219. } else
  2220. b = t = l = 0;
  2221. if (firsttime) {
  2222. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2223. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2224. if (!gdth_polling) {
  2225. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2226. return;
  2227. }
  2228. while (gdth_test_busy(hanum))
  2229. gdth_delay(1);
  2230. }
  2231. firsttime = FALSE;
  2232. }
  2233. if (nscp->done != gdth_scsi_done) {
  2234. if (nscp->SCp.phase == -1) {
  2235. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2236. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2237. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2238. b, t, l));
  2239. /* TEST_UNIT_READY -> set scan mode */
  2240. if ((ha->scan_mode & 0x0f) == 0) {
  2241. if (b == 0 && t == 0 && l == 0) {
  2242. ha->scan_mode |= 1;
  2243. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2244. }
  2245. } else if ((ha->scan_mode & 0x0f) == 1) {
  2246. if (b == 0 && ((t == 0 && l == 1) ||
  2247. (t == 1 && l == 0))) {
  2248. nscp->SCp.sent_command = GDT_SCAN_START;
  2249. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2250. | SCSIRAWSERVICE;
  2251. ha->scan_mode = 0x12;
  2252. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2253. ha->scan_mode));
  2254. } else {
  2255. ha->scan_mode &= 0x10;
  2256. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2257. }
  2258. } else if (ha->scan_mode == 0x12) {
  2259. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2260. nscp->SCp.phase = SCSIRAWSERVICE;
  2261. nscp->SCp.sent_command = GDT_SCAN_END;
  2262. ha->scan_mode &= 0x10;
  2263. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2264. ha->scan_mode));
  2265. }
  2266. }
  2267. }
  2268. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2269. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2270. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2271. /* always GDT_CLUST_INFO! */
  2272. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2273. }
  2274. }
  2275. }
  2276. if (nscp->SCp.sent_command != -1) {
  2277. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2278. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2279. this_cmd = FALSE;
  2280. next_cmd = FALSE;
  2281. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2282. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2283. this_cmd = FALSE;
  2284. next_cmd = FALSE;
  2285. } else {
  2286. memset((char*)nscp->sense_buffer,0,16);
  2287. nscp->sense_buffer[0] = 0x70;
  2288. nscp->sense_buffer[2] = NOT_READY;
  2289. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2290. if (!nscp->SCp.have_data_in)
  2291. nscp->SCp.have_data_in++;
  2292. else
  2293. nscp->scsi_done(nscp);
  2294. }
  2295. } else if (nscp->done == gdth_scsi_done) {
  2296. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2297. this_cmd = FALSE;
  2298. next_cmd = FALSE;
  2299. } else if (b != ha->virt_bus) {
  2300. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2301. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2302. this_cmd = FALSE;
  2303. else
  2304. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2305. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2306. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2307. nscp->cmnd[0], b, t, l));
  2308. nscp->result = DID_BAD_TARGET << 16;
  2309. if (!nscp->SCp.have_data_in)
  2310. nscp->SCp.have_data_in++;
  2311. else
  2312. nscp->scsi_done(nscp);
  2313. } else {
  2314. switch (nscp->cmnd[0]) {
  2315. case TEST_UNIT_READY:
  2316. case INQUIRY:
  2317. case REQUEST_SENSE:
  2318. case READ_CAPACITY:
  2319. case VERIFY:
  2320. case START_STOP:
  2321. case MODE_SENSE:
  2322. case SERVICE_ACTION_IN:
  2323. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2324. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2325. nscp->cmnd[4],nscp->cmnd[5]));
  2326. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2327. /* return UNIT_ATTENTION */
  2328. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2329. nscp->cmnd[0], t));
  2330. ha->hdr[t].media_changed = FALSE;
  2331. memset((char*)nscp->sense_buffer,0,16);
  2332. nscp->sense_buffer[0] = 0x70;
  2333. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2334. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2335. if (!nscp->SCp.have_data_in)
  2336. nscp->SCp.have_data_in++;
  2337. else
  2338. nscp->scsi_done(nscp);
  2339. } else if (gdth_internal_cache_cmd(hanum,nscp))
  2340. nscp->scsi_done(nscp);
  2341. break;
  2342. case ALLOW_MEDIUM_REMOVAL:
  2343. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2344. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2345. nscp->cmnd[4],nscp->cmnd[5]));
  2346. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2347. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2348. nscp->result = DID_OK << 16;
  2349. nscp->sense_buffer[0] = 0;
  2350. if (!nscp->SCp.have_data_in)
  2351. nscp->SCp.have_data_in++;
  2352. else
  2353. nscp->scsi_done(nscp);
  2354. } else {
  2355. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2356. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2357. nscp->cmnd[4],nscp->cmnd[3]));
  2358. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2359. this_cmd = FALSE;
  2360. }
  2361. break;
  2362. case RESERVE:
  2363. case RELEASE:
  2364. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2365. "RESERVE" : "RELEASE"));
  2366. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2367. this_cmd = FALSE;
  2368. break;
  2369. case READ_6:
  2370. case WRITE_6:
  2371. case READ_10:
  2372. case WRITE_10:
  2373. case READ_16:
  2374. case WRITE_16:
  2375. if (ha->hdr[t].media_changed) {
  2376. /* return UNIT_ATTENTION */
  2377. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2378. nscp->cmnd[0], t));
  2379. ha->hdr[t].media_changed = FALSE;
  2380. memset((char*)nscp->sense_buffer,0,16);
  2381. nscp->sense_buffer[0] = 0x70;
  2382. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2383. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2384. if (!nscp->SCp.have_data_in)
  2385. nscp->SCp.have_data_in++;
  2386. else
  2387. nscp->scsi_done(nscp);
  2388. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2389. this_cmd = FALSE;
  2390. break;
  2391. default:
  2392. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2393. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2394. nscp->cmnd[4],nscp->cmnd[5]));
  2395. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2396. hanum, nscp->cmnd[0]);
  2397. nscp->result = DID_ABORT << 16;
  2398. if (!nscp->SCp.have_data_in)
  2399. nscp->SCp.have_data_in++;
  2400. else
  2401. nscp->scsi_done(nscp);
  2402. break;
  2403. }
  2404. }
  2405. if (!this_cmd)
  2406. break;
  2407. if (nscp == ha->req_first)
  2408. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2409. else
  2410. pscp->SCp.ptr = nscp->SCp.ptr;
  2411. if (!next_cmd)
  2412. break;
  2413. }
  2414. if (ha->cmd_cnt > 0) {
  2415. gdth_release_event(hanum);
  2416. }
  2417. if (!gdth_polling)
  2418. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2419. if (gdth_polling && ha->cmd_cnt > 0) {
  2420. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2421. printk("GDT-HA %d: Command %d timed out !\n",
  2422. hanum,cmd_index);
  2423. }
  2424. }
  2425. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2426. char *buffer,ushort count)
  2427. {
  2428. ushort cpcount,i;
  2429. ushort cpsum,cpnow;
  2430. struct scatterlist *sl;
  2431. gdth_ha_str *ha;
  2432. char *address;
  2433. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2434. ha = HADATA(gdth_ctr_tab[hanum]);
  2435. if (scp->use_sg) {
  2436. sl = (struct scatterlist *)scp->request_buffer;
  2437. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2438. unsigned long flags;
  2439. cpnow = (ushort)sl->length;
  2440. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2441. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2442. if (cpsum+cpnow > cpcount)
  2443. cpnow = cpcount - cpsum;
  2444. cpsum += cpnow;
  2445. if (!sl->page) {
  2446. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2447. hanum);
  2448. return;
  2449. }
  2450. local_irq_save(flags);
  2451. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2452. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2453. memcpy(address,buffer,cpnow);
  2454. flush_dcache_page(sl->page);
  2455. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2456. #else
  2457. address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
  2458. memcpy(address,buffer,cpnow);
  2459. flush_dcache_page(sl->page);
  2460. kunmap_atomic(address, KM_BH_IRQ);
  2461. #endif
  2462. local_irq_restore(flags);
  2463. if (cpsum == cpcount)
  2464. break;
  2465. buffer += cpnow;
  2466. }
  2467. } else {
  2468. TRACE(("copy_internal() count %d\n",cpcount));
  2469. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2470. }
  2471. }
  2472. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2473. {
  2474. register gdth_ha_str *ha;
  2475. unchar t;
  2476. gdth_inq_data inq;
  2477. gdth_rdcap_data rdc;
  2478. gdth_sense_data sd;
  2479. gdth_modep_data mpd;
  2480. ha = HADATA(gdth_ctr_tab[hanum]);
  2481. t = scp->device->id;
  2482. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2483. scp->cmnd[0],t));
  2484. scp->result = DID_OK << 16;
  2485. scp->sense_buffer[0] = 0;
  2486. switch (scp->cmnd[0]) {
  2487. case TEST_UNIT_READY:
  2488. case VERIFY:
  2489. case START_STOP:
  2490. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2491. break;
  2492. case INQUIRY:
  2493. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2494. t,ha->hdr[t].devtype));
  2495. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2496. /* you can here set all disks to removable, if you want to do
  2497. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2498. inq.modif_rmb = 0x00;
  2499. if ((ha->hdr[t].devtype & 1) ||
  2500. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2501. inq.modif_rmb = 0x80;
  2502. inq.version = 2;
  2503. inq.resp_aenc = 2;
  2504. inq.add_length= 32;
  2505. strcpy(inq.vendor,ha->oem_name);
  2506. sprintf(inq.product,"Host Drive #%02d",t);
  2507. strcpy(inq.revision," ");
  2508. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2509. break;
  2510. case REQUEST_SENSE:
  2511. TRACE2(("Request sense hdrive %d\n",t));
  2512. sd.errorcode = 0x70;
  2513. sd.segno = 0x00;
  2514. sd.key = NO_SENSE;
  2515. sd.info = 0;
  2516. sd.add_length= 0;
  2517. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2518. break;
  2519. case MODE_SENSE:
  2520. TRACE2(("Mode sense hdrive %d\n",t));
  2521. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2522. mpd.hd.data_length = sizeof(gdth_modep_data);
  2523. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2524. mpd.hd.bd_length = sizeof(mpd.bd);
  2525. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2526. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2527. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2528. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2529. break;
  2530. case READ_CAPACITY:
  2531. TRACE2(("Read capacity hdrive %d\n",t));
  2532. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2533. rdc.last_block_no = 0xffffffff;
  2534. else
  2535. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2536. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2537. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2538. break;
  2539. case SERVICE_ACTION_IN:
  2540. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2541. (ha->cache_feat & GDT_64BIT)) {
  2542. gdth_rdcap16_data rdc16;
  2543. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2544. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2545. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2546. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2547. } else {
  2548. scp->result = DID_ABORT << 16;
  2549. }
  2550. break;
  2551. default:
  2552. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2553. break;
  2554. }
  2555. if (!scp->SCp.have_data_in)
  2556. scp->SCp.have_data_in++;
  2557. else
  2558. return 1;
  2559. return 0;
  2560. }
  2561. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2562. {
  2563. register gdth_ha_str *ha;
  2564. register gdth_cmd_str *cmdp;
  2565. struct scatterlist *sl;
  2566. ulong32 cnt, blockcnt;
  2567. ulong64 no, blockno;
  2568. dma_addr_t phys_addr;
  2569. int i, cmd_index, read_write, sgcnt, mode64;
  2570. struct page *page;
  2571. ulong offset;
  2572. ha = HADATA(gdth_ctr_tab[hanum]);
  2573. cmdp = ha->pccb;
  2574. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2575. scp->cmnd[0],scp->cmd_len,hdrive));
  2576. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2577. return 0;
  2578. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2579. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2580. not required, should not occur due to error return on
  2581. READ_CAPACITY_16 */
  2582. cmdp->Service = CACHESERVICE;
  2583. cmdp->RequestBuffer = scp;
  2584. /* search free command index */
  2585. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2586. TRACE(("GDT: No free command index found\n"));
  2587. return 0;
  2588. }
  2589. /* if it's the first command, set command semaphore */
  2590. if (ha->cmd_cnt == 0)
  2591. gdth_set_sema0(hanum);
  2592. /* fill command */
  2593. read_write = 0;
  2594. if (scp->SCp.sent_command != -1)
  2595. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2596. else if (scp->cmnd[0] == RESERVE)
  2597. cmdp->OpCode = GDT_RESERVE_DRV;
  2598. else if (scp->cmnd[0] == RELEASE)
  2599. cmdp->OpCode = GDT_RELEASE_DRV;
  2600. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2601. if (scp->cmnd[4] & 1) /* prevent ? */
  2602. cmdp->OpCode = GDT_MOUNT;
  2603. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2604. cmdp->OpCode = GDT_UNMOUNT;
  2605. else
  2606. cmdp->OpCode = GDT_FLUSH;
  2607. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2608. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2609. ) {
  2610. read_write = 1;
  2611. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2612. (ha->cache_feat & GDT_WR_THROUGH)))
  2613. cmdp->OpCode = GDT_WRITE_THR;
  2614. else
  2615. cmdp->OpCode = GDT_WRITE;
  2616. } else {
  2617. read_write = 2;
  2618. cmdp->OpCode = GDT_READ;
  2619. }
  2620. cmdp->BoardNode = LOCALBOARD;
  2621. if (mode64) {
  2622. cmdp->u.cache64.DeviceNo = hdrive;
  2623. cmdp->u.cache64.BlockNo = 1;
  2624. cmdp->u.cache64.sg_canz = 0;
  2625. } else {
  2626. cmdp->u.cache.DeviceNo = hdrive;
  2627. cmdp->u.cache.BlockNo = 1;
  2628. cmdp->u.cache.sg_canz = 0;
  2629. }
  2630. if (read_write) {
  2631. if (scp->cmd_len == 16) {
  2632. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2633. blockno = be64_to_cpu(no);
  2634. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2635. blockcnt = be32_to_cpu(cnt);
  2636. } else if (scp->cmd_len == 10) {
  2637. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2638. blockno = be32_to_cpu(no);
  2639. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2640. blockcnt = be16_to_cpu(cnt);
  2641. } else {
  2642. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2643. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2644. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2645. }
  2646. if (mode64) {
  2647. cmdp->u.cache64.BlockNo = blockno;
  2648. cmdp->u.cache64.BlockCnt = blockcnt;
  2649. } else {
  2650. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2651. cmdp->u.cache.BlockCnt = blockcnt;
  2652. }
  2653. if (scp->use_sg) {
  2654. sl = (struct scatterlist *)scp->request_buffer;
  2655. sgcnt = scp->use_sg;
  2656. scp->SCp.Status = GDTH_MAP_SG;
  2657. scp->SCp.Message = (read_write == 1 ?
  2658. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2659. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2660. if (mode64) {
  2661. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2662. cmdp->u.cache64.sg_canz = sgcnt;
  2663. for (i=0; i<sgcnt; ++i,++sl) {
  2664. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2665. #ifdef GDTH_DMA_STATISTICS
  2666. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2667. ha->dma64_cnt++;
  2668. else
  2669. ha->dma32_cnt++;
  2670. #endif
  2671. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2672. }
  2673. } else {
  2674. cmdp->u.cache.DestAddr= 0xffffffff;
  2675. cmdp->u.cache.sg_canz = sgcnt;
  2676. for (i=0; i<sgcnt; ++i,++sl) {
  2677. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2678. #ifdef GDTH_DMA_STATISTICS
  2679. ha->dma32_cnt++;
  2680. #endif
  2681. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2682. }
  2683. }
  2684. #ifdef GDTH_STATISTICS
  2685. if (max_sg < (ulong32)sgcnt) {
  2686. max_sg = (ulong32)sgcnt;
  2687. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2688. }
  2689. #endif
  2690. } else if (scp->request_bufflen) {
  2691. scp->SCp.Status = GDTH_MAP_SINGLE;
  2692. scp->SCp.Message = (read_write == 1 ?
  2693. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2694. page = virt_to_page(scp->request_buffer);
  2695. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2696. phys_addr = pci_map_page(ha->pdev,page,offset,
  2697. scp->request_bufflen,scp->SCp.Message);
  2698. scp->SCp.dma_handle = phys_addr;
  2699. if (mode64) {
  2700. if (ha->cache_feat & SCATTER_GATHER) {
  2701. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2702. cmdp->u.cache64.sg_canz = 1;
  2703. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2704. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2705. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2706. } else {
  2707. cmdp->u.cache64.DestAddr = phys_addr;
  2708. cmdp->u.cache64.sg_canz= 0;
  2709. }
  2710. } else {
  2711. if (ha->cache_feat & SCATTER_GATHER) {
  2712. cmdp->u.cache.DestAddr = 0xffffffff;
  2713. cmdp->u.cache.sg_canz = 1;
  2714. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2715. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2716. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2717. } else {
  2718. cmdp->u.cache.DestAddr = phys_addr;
  2719. cmdp->u.cache.sg_canz= 0;
  2720. }
  2721. }
  2722. }
  2723. }
  2724. /* evaluate command size, check space */
  2725. if (mode64) {
  2726. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2727. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2728. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2729. cmdp->u.cache64.sg_lst[0].sg_len));
  2730. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2731. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2732. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2733. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2734. } else {
  2735. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2736. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2737. cmdp->u.cache.sg_lst[0].sg_ptr,
  2738. cmdp->u.cache.sg_lst[0].sg_len));
  2739. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2740. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2741. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2742. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2743. }
  2744. if (ha->cmd_len & 3)
  2745. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2746. if (ha->cmd_cnt > 0) {
  2747. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2748. ha->ic_all_size) {
  2749. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2750. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2751. return 0;
  2752. }
  2753. }
  2754. /* copy command */
  2755. gdth_copy_command(hanum);
  2756. return cmd_index;
  2757. }
  2758. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2759. {
  2760. register gdth_ha_str *ha;
  2761. register gdth_cmd_str *cmdp;
  2762. struct scatterlist *sl;
  2763. ushort i;
  2764. dma_addr_t phys_addr, sense_paddr;
  2765. int cmd_index, sgcnt, mode64;
  2766. unchar t,l;
  2767. struct page *page;
  2768. ulong offset;
  2769. ha = HADATA(gdth_ctr_tab[hanum]);
  2770. t = scp->device->id;
  2771. l = scp->device->lun;
  2772. cmdp = ha->pccb;
  2773. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2774. scp->cmnd[0],b,t,l));
  2775. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2776. return 0;
  2777. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2778. cmdp->Service = SCSIRAWSERVICE;
  2779. cmdp->RequestBuffer = scp;
  2780. /* search free command index */
  2781. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2782. TRACE(("GDT: No free command index found\n"));
  2783. return 0;
  2784. }
  2785. /* if it's the first command, set command semaphore */
  2786. if (ha->cmd_cnt == 0)
  2787. gdth_set_sema0(hanum);
  2788. /* fill command */
  2789. if (scp->SCp.sent_command != -1) {
  2790. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2791. cmdp->BoardNode = LOCALBOARD;
  2792. if (mode64) {
  2793. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2794. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2795. cmdp->OpCode, cmdp->u.raw64.direction));
  2796. /* evaluate command size */
  2797. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2798. } else {
  2799. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2800. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2801. cmdp->OpCode, cmdp->u.raw.direction));
  2802. /* evaluate command size */
  2803. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2804. }
  2805. } else {
  2806. page = virt_to_page(scp->sense_buffer);
  2807. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2808. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2809. 16,PCI_DMA_FROMDEVICE);
  2810. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2811. /* high part, if 64bit */
  2812. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2813. cmdp->OpCode = GDT_WRITE; /* always */
  2814. cmdp->BoardNode = LOCALBOARD;
  2815. if (mode64) {
  2816. cmdp->u.raw64.reserved = 0;
  2817. cmdp->u.raw64.mdisc_time = 0;
  2818. cmdp->u.raw64.mcon_time = 0;
  2819. cmdp->u.raw64.clen = scp->cmd_len;
  2820. cmdp->u.raw64.target = t;
  2821. cmdp->u.raw64.lun = l;
  2822. cmdp->u.raw64.bus = b;
  2823. cmdp->u.raw64.priority = 0;
  2824. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2825. cmdp->u.raw64.sense_len = 16;
  2826. cmdp->u.raw64.sense_data = sense_paddr;
  2827. cmdp->u.raw64.direction =
  2828. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2829. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2830. } else {
  2831. cmdp->u.raw.reserved = 0;
  2832. cmdp->u.raw.mdisc_time = 0;
  2833. cmdp->u.raw.mcon_time = 0;
  2834. cmdp->u.raw.clen = scp->cmd_len;
  2835. cmdp->u.raw.target = t;
  2836. cmdp->u.raw.lun = l;
  2837. cmdp->u.raw.bus = b;
  2838. cmdp->u.raw.priority = 0;
  2839. cmdp->u.raw.link_p = 0;
  2840. cmdp->u.raw.sdlen = scp->request_bufflen;
  2841. cmdp->u.raw.sense_len = 16;
  2842. cmdp->u.raw.sense_data = sense_paddr;
  2843. cmdp->u.raw.direction =
  2844. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2845. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2846. }
  2847. if (scp->use_sg) {
  2848. sl = (struct scatterlist *)scp->request_buffer;
  2849. sgcnt = scp->use_sg;
  2850. scp->SCp.Status = GDTH_MAP_SG;
  2851. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2852. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2853. if (mode64) {
  2854. cmdp->u.raw64.sdata = (ulong64)-1;
  2855. cmdp->u.raw64.sg_ranz = sgcnt;
  2856. for (i=0; i<sgcnt; ++i,++sl) {
  2857. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2858. #ifdef GDTH_DMA_STATISTICS
  2859. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2860. ha->dma64_cnt++;
  2861. else
  2862. ha->dma32_cnt++;
  2863. #endif
  2864. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2865. }
  2866. } else {
  2867. cmdp->u.raw.sdata = 0xffffffff;
  2868. cmdp->u.raw.sg_ranz = sgcnt;
  2869. for (i=0; i<sgcnt; ++i,++sl) {
  2870. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2871. #ifdef GDTH_DMA_STATISTICS
  2872. ha->dma32_cnt++;
  2873. #endif
  2874. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2875. }
  2876. }
  2877. #ifdef GDTH_STATISTICS
  2878. if (max_sg < sgcnt) {
  2879. max_sg = sgcnt;
  2880. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2881. }
  2882. #endif
  2883. } else if (scp->request_bufflen) {
  2884. scp->SCp.Status = GDTH_MAP_SINGLE;
  2885. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2886. page = virt_to_page(scp->request_buffer);
  2887. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2888. phys_addr = pci_map_page(ha->pdev,page,offset,
  2889. scp->request_bufflen,scp->SCp.Message);
  2890. scp->SCp.dma_handle = phys_addr;
  2891. if (mode64) {
  2892. if (ha->raw_feat & SCATTER_GATHER) {
  2893. cmdp->u.raw64.sdata = (ulong64)-1;
  2894. cmdp->u.raw64.sg_ranz= 1;
  2895. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2896. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2897. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2898. } else {
  2899. cmdp->u.raw64.sdata = phys_addr;
  2900. cmdp->u.raw64.sg_ranz= 0;
  2901. }
  2902. } else {
  2903. if (ha->raw_feat & SCATTER_GATHER) {
  2904. cmdp->u.raw.sdata = 0xffffffff;
  2905. cmdp->u.raw.sg_ranz= 1;
  2906. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2907. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2908. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2909. } else {
  2910. cmdp->u.raw.sdata = phys_addr;
  2911. cmdp->u.raw.sg_ranz= 0;
  2912. }
  2913. }
  2914. }
  2915. if (mode64) {
  2916. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2917. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2918. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2919. cmdp->u.raw64.sg_lst[0].sg_len));
  2920. /* evaluate command size */
  2921. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2922. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2923. } else {
  2924. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2925. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2926. cmdp->u.raw.sg_lst[0].sg_ptr,
  2927. cmdp->u.raw.sg_lst[0].sg_len));
  2928. /* evaluate command size */
  2929. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2930. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2931. }
  2932. }
  2933. /* check space */
  2934. if (ha->cmd_len & 3)
  2935. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2936. if (ha->cmd_cnt > 0) {
  2937. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2938. ha->ic_all_size) {
  2939. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2940. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2941. return 0;
  2942. }
  2943. }
  2944. /* copy command */
  2945. gdth_copy_command(hanum);
  2946. return cmd_index;
  2947. }
  2948. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2949. {
  2950. register gdth_ha_str *ha;
  2951. register gdth_cmd_str *cmdp;
  2952. int cmd_index;
  2953. ha = HADATA(gdth_ctr_tab[hanum]);
  2954. cmdp= ha->pccb;
  2955. TRACE2(("gdth_special_cmd(): "));
  2956. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2957. return 0;
  2958. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2959. cmdp->RequestBuffer = scp;
  2960. /* search free command index */
  2961. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2962. TRACE(("GDT: No free command index found\n"));
  2963. return 0;
  2964. }
  2965. /* if it's the first command, set command semaphore */
  2966. if (ha->cmd_cnt == 0)
  2967. gdth_set_sema0(hanum);
  2968. /* evaluate command size, check space */
  2969. if (cmdp->OpCode == GDT_IOCTL) {
  2970. TRACE2(("IOCTL\n"));
  2971. ha->cmd_len =
  2972. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2973. } else if (cmdp->Service == CACHESERVICE) {
  2974. TRACE2(("cache command %d\n",cmdp->OpCode));
  2975. if (ha->cache_feat & GDT_64BIT)
  2976. ha->cmd_len =
  2977. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2978. else
  2979. ha->cmd_len =
  2980. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2981. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2982. TRACE2(("raw command %d\n",cmdp->OpCode));
  2983. if (ha->raw_feat & GDT_64BIT)
  2984. ha->cmd_len =
  2985. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2986. else
  2987. ha->cmd_len =
  2988. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  2989. }
  2990. if (ha->cmd_len & 3)
  2991. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2992. if (ha->cmd_cnt > 0) {
  2993. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2994. ha->ic_all_size) {
  2995. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  2996. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2997. return 0;
  2998. }
  2999. }
  3000. /* copy command */
  3001. gdth_copy_command(hanum);
  3002. return cmd_index;
  3003. }
  3004. /* Controller event handling functions */
  3005. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  3006. ushort idx, gdth_evt_data *evt)
  3007. {
  3008. gdth_evt_str *e;
  3009. struct timeval tv;
  3010. /* no GDTH_LOCK_HA() ! */
  3011. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  3012. if (source == 0) /* no source -> no event */
  3013. return NULL;
  3014. if (ebuffer[elastidx].event_source == source &&
  3015. ebuffer[elastidx].event_idx == idx &&
  3016. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  3017. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  3018. (char *)&evt->eu, evt->size)) ||
  3019. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  3020. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  3021. (char *)&evt->event_string)))) {
  3022. e = &ebuffer[elastidx];
  3023. do_gettimeofday(&tv);
  3024. e->last_stamp = tv.tv_sec;
  3025. ++e->same_count;
  3026. } else {
  3027. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  3028. ++elastidx;
  3029. if (elastidx == MAX_EVENTS)
  3030. elastidx = 0;
  3031. if (elastidx == eoldidx) { /* reached mark ? */
  3032. ++eoldidx;
  3033. if (eoldidx == MAX_EVENTS)
  3034. eoldidx = 0;
  3035. }
  3036. }
  3037. e = &ebuffer[elastidx];
  3038. e->event_source = source;
  3039. e->event_idx = idx;
  3040. do_gettimeofday(&tv);
  3041. e->first_stamp = e->last_stamp = tv.tv_sec;
  3042. e->same_count = 1;
  3043. e->event_data = *evt;
  3044. e->application = 0;
  3045. }
  3046. return e;
  3047. }
  3048. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  3049. {
  3050. gdth_evt_str *e;
  3051. int eindex;
  3052. ulong flags;
  3053. TRACE2(("gdth_read_event() handle %d\n", handle));
  3054. spin_lock_irqsave(&ha->smp_lock, flags);
  3055. if (handle == -1)
  3056. eindex = eoldidx;
  3057. else
  3058. eindex = handle;
  3059. estr->event_source = 0;
  3060. if (eindex >= MAX_EVENTS) {
  3061. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3062. return eindex;
  3063. }
  3064. e = &ebuffer[eindex];
  3065. if (e->event_source != 0) {
  3066. if (eindex != elastidx) {
  3067. if (++eindex == MAX_EVENTS)
  3068. eindex = 0;
  3069. } else {
  3070. eindex = -1;
  3071. }
  3072. memcpy(estr, e, sizeof(gdth_evt_str));
  3073. }
  3074. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3075. return eindex;
  3076. }
  3077. static void gdth_readapp_event(gdth_ha_str *ha,
  3078. unchar application, gdth_evt_str *estr)
  3079. {
  3080. gdth_evt_str *e;
  3081. int eindex;
  3082. ulong flags;
  3083. unchar found = FALSE;
  3084. TRACE2(("gdth_readapp_event() app. %d\n", application));
  3085. spin_lock_irqsave(&ha->smp_lock, flags);
  3086. eindex = eoldidx;
  3087. for (;;) {
  3088. e = &ebuffer[eindex];
  3089. if (e->event_source == 0)
  3090. break;
  3091. if ((e->application & application) == 0) {
  3092. e->application |= application;
  3093. found = TRUE;
  3094. break;
  3095. }
  3096. if (eindex == elastidx)
  3097. break;
  3098. if (++eindex == MAX_EVENTS)
  3099. eindex = 0;
  3100. }
  3101. if (found)
  3102. memcpy(estr, e, sizeof(gdth_evt_str));
  3103. else
  3104. estr->event_source = 0;
  3105. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3106. }
  3107. static void gdth_clear_events(void)
  3108. {
  3109. TRACE(("gdth_clear_events()"));
  3110. eoldidx = elastidx = 0;
  3111. ebuffer[0].event_source = 0;
  3112. }
  3113. /* SCSI interface functions */
  3114. static irqreturn_t gdth_interrupt(int irq,void *dev_id)
  3115. {
  3116. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3117. register gdth_ha_str *ha;
  3118. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3119. gdt6_dpram_str __iomem *dp6_ptr;
  3120. gdt2_dpram_str __iomem *dp2_ptr;
  3121. Scsi_Cmnd *scp;
  3122. int hanum, rval, i;
  3123. unchar IStatus;
  3124. ushort Service;
  3125. ulong flags = 0;
  3126. #ifdef INT_COAL
  3127. int coalesced = FALSE;
  3128. int next = FALSE;
  3129. gdth_coal_status *pcs = NULL;
  3130. int act_int_coal = 0;
  3131. #endif
  3132. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3133. /* if polling and not from gdth_wait() -> return */
  3134. if (gdth_polling) {
  3135. if (!gdth_from_wait) {
  3136. return IRQ_HANDLED;
  3137. }
  3138. }
  3139. if (!gdth_polling)
  3140. spin_lock_irqsave(&ha2->smp_lock, flags);
  3141. wait_index = 0;
  3142. /* search controller */
  3143. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3144. /* spurious interrupt */
  3145. if (!gdth_polling)
  3146. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3147. return IRQ_HANDLED;
  3148. }
  3149. ha = HADATA(gdth_ctr_tab[hanum]);
  3150. #ifdef GDTH_STATISTICS
  3151. ++act_ints;
  3152. #endif
  3153. #ifdef INT_COAL
  3154. /* See if the fw is returning coalesced status */
  3155. if (IStatus == COALINDEX) {
  3156. /* Coalesced status. Setup the initial status
  3157. buffer pointer and flags */
  3158. pcs = ha->coal_stat;
  3159. coalesced = TRUE;
  3160. next = TRUE;
  3161. }
  3162. do {
  3163. if (coalesced) {
  3164. /* For coalesced requests all status
  3165. information is found in the status buffer */
  3166. IStatus = (unchar)(pcs->status & 0xff);
  3167. }
  3168. #endif
  3169. if (ha->type == GDT_EISA) {
  3170. if (IStatus & 0x80) { /* error flag */
  3171. IStatus &= ~0x80;
  3172. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3173. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3174. } else /* no error */
  3175. ha->status = S_OK;
  3176. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3177. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3178. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3179. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3180. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3181. } else if (ha->type == GDT_ISA) {
  3182. dp2_ptr = ha->brd;
  3183. if (IStatus & 0x80) { /* error flag */
  3184. IStatus &= ~0x80;
  3185. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3186. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3187. } else /* no error */
  3188. ha->status = S_OK;
  3189. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3190. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3191. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3192. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3193. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3194. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3195. } else if (ha->type == GDT_PCI) {
  3196. dp6_ptr = ha->brd;
  3197. if (IStatus & 0x80) { /* error flag */
  3198. IStatus &= ~0x80;
  3199. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3200. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3201. } else /* no error */
  3202. ha->status = S_OK;
  3203. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3204. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3205. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3206. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3207. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3208. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3209. } else if (ha->type == GDT_PCINEW) {
  3210. if (IStatus & 0x80) { /* error flag */
  3211. IStatus &= ~0x80;
  3212. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3213. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3214. } else
  3215. ha->status = S_OK;
  3216. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3217. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3218. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3219. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3220. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3221. } else if (ha->type == GDT_PCIMPR) {
  3222. dp6m_ptr = ha->brd;
  3223. if (IStatus & 0x80) { /* error flag */
  3224. IStatus &= ~0x80;
  3225. #ifdef INT_COAL
  3226. if (coalesced)
  3227. ha->status = pcs->ext_status && 0xffff;
  3228. else
  3229. #endif
  3230. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3231. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3232. } else /* no error */
  3233. ha->status = S_OK;
  3234. #ifdef INT_COAL
  3235. /* get information */
  3236. if (coalesced) {
  3237. ha->info = pcs->info0;
  3238. ha->info2 = pcs->info1;
  3239. ha->service = (pcs->ext_status >> 16) && 0xffff;
  3240. } else
  3241. #endif
  3242. {
  3243. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3244. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3245. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3246. }
  3247. /* event string */
  3248. if (IStatus == ASYNCINDEX) {
  3249. if (ha->service != SCREENSERVICE &&
  3250. (ha->fw_vers & 0xff) >= 0x1a) {
  3251. ha->dvr.severity = gdth_readb
  3252. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3253. for (i = 0; i < 256; ++i) {
  3254. ha->dvr.event_string[i] = gdth_readb
  3255. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3256. if (ha->dvr.event_string[i] == 0)
  3257. break;
  3258. }
  3259. }
  3260. }
  3261. #ifdef INT_COAL
  3262. /* Make sure that non coalesced interrupts get cleared
  3263. before being handled by gdth_async_event/gdth_sync_event */
  3264. if (!coalesced)
  3265. #endif
  3266. {
  3267. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3268. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3269. }
  3270. } else {
  3271. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3272. if (!gdth_polling)
  3273. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3274. return IRQ_HANDLED;
  3275. }
  3276. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3277. IStatus,ha->status,ha->info));
  3278. if (gdth_from_wait) {
  3279. wait_hanum = hanum;
  3280. wait_index = (int)IStatus;
  3281. }
  3282. if (IStatus == ASYNCINDEX) {
  3283. TRACE2(("gdth_interrupt() async. event\n"));
  3284. gdth_async_event(hanum);
  3285. if (!gdth_polling)
  3286. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3287. gdth_next(hanum);
  3288. return IRQ_HANDLED;
  3289. }
  3290. if (IStatus == SPEZINDEX) {
  3291. TRACE2(("Service unknown or not initialized !\n"));
  3292. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3293. ha->dvr.eu.driver.ionode = hanum;
  3294. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3295. if (!gdth_polling)
  3296. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3297. return IRQ_HANDLED;
  3298. }
  3299. scp = ha->cmd_tab[IStatus-2].cmnd;
  3300. Service = ha->cmd_tab[IStatus-2].service;
  3301. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3302. if (scp == UNUSED_CMND) {
  3303. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3304. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3305. ha->dvr.eu.driver.ionode = hanum;
  3306. ha->dvr.eu.driver.index = IStatus;
  3307. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3308. if (!gdth_polling)
  3309. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3310. return IRQ_HANDLED;
  3311. }
  3312. if (scp == INTERNAL_CMND) {
  3313. TRACE(("gdth_interrupt() answer to internal command\n"));
  3314. if (!gdth_polling)
  3315. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3316. return IRQ_HANDLED;
  3317. }
  3318. TRACE(("gdth_interrupt() sync. status\n"));
  3319. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3320. if (!gdth_polling)
  3321. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3322. if (rval == 2) {
  3323. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3324. } else if (rval == 1) {
  3325. scp->scsi_done(scp);
  3326. }
  3327. #ifdef INT_COAL
  3328. if (coalesced) {
  3329. /* go to the next status in the status buffer */
  3330. ++pcs;
  3331. #ifdef GDTH_STATISTICS
  3332. ++act_int_coal;
  3333. if (act_int_coal > max_int_coal) {
  3334. max_int_coal = act_int_coal;
  3335. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3336. }
  3337. #endif
  3338. /* see if there is another status */
  3339. if (pcs->status == 0)
  3340. /* Stop the coalesce loop */
  3341. next = FALSE;
  3342. }
  3343. } while (next);
  3344. /* coalescing only for new GDT_PCIMPR controllers available */
  3345. if (ha->type == GDT_PCIMPR && coalesced) {
  3346. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3347. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3348. }
  3349. #endif
  3350. gdth_next(hanum);
  3351. return IRQ_HANDLED;
  3352. }
  3353. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3354. {
  3355. register gdth_ha_str *ha;
  3356. gdth_msg_str *msg;
  3357. gdth_cmd_str *cmdp;
  3358. unchar b, t;
  3359. ha = HADATA(gdth_ctr_tab[hanum]);
  3360. cmdp = ha->pccb;
  3361. TRACE(("gdth_sync_event() serv %d status %d\n",
  3362. service,ha->status));
  3363. if (service == SCREENSERVICE) {
  3364. msg = ha->pmsg;
  3365. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3366. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3367. if (msg->msg_len > MSGLEN+1)
  3368. msg->msg_len = MSGLEN+1;
  3369. if (msg->msg_len)
  3370. if (!(msg->msg_answer && msg->msg_ext)) {
  3371. msg->msg_text[msg->msg_len] = '\0';
  3372. printk("%s",msg->msg_text);
  3373. }
  3374. if (msg->msg_ext && !msg->msg_answer) {
  3375. while (gdth_test_busy(hanum))
  3376. gdth_delay(0);
  3377. cmdp->Service = SCREENSERVICE;
  3378. cmdp->RequestBuffer = SCREEN_CMND;
  3379. gdth_get_cmd_index(hanum);
  3380. gdth_set_sema0(hanum);
  3381. cmdp->OpCode = GDT_READ;
  3382. cmdp->BoardNode = LOCALBOARD;
  3383. cmdp->u.screen.reserved = 0;
  3384. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3385. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3386. ha->cmd_offs_dpmem = 0;
  3387. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3388. + sizeof(ulong64);
  3389. ha->cmd_cnt = 0;
  3390. gdth_copy_command(hanum);
  3391. gdth_release_event(hanum);
  3392. return 0;
  3393. }
  3394. if (msg->msg_answer && msg->msg_alen) {
  3395. /* default answers (getchar() not possible) */
  3396. if (msg->msg_alen == 1) {
  3397. msg->msg_alen = 0;
  3398. msg->msg_len = 1;
  3399. msg->msg_text[0] = 0;
  3400. } else {
  3401. msg->msg_alen -= 2;
  3402. msg->msg_len = 2;
  3403. msg->msg_text[0] = 1;
  3404. msg->msg_text[1] = 0;
  3405. }
  3406. msg->msg_ext = 0;
  3407. msg->msg_answer = 0;
  3408. while (gdth_test_busy(hanum))
  3409. gdth_delay(0);
  3410. cmdp->Service = SCREENSERVICE;
  3411. cmdp->RequestBuffer = SCREEN_CMND;
  3412. gdth_get_cmd_index(hanum);
  3413. gdth_set_sema0(hanum);
  3414. cmdp->OpCode = GDT_WRITE;
  3415. cmdp->BoardNode = LOCALBOARD;
  3416. cmdp->u.screen.reserved = 0;
  3417. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3418. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3419. ha->cmd_offs_dpmem = 0;
  3420. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3421. + sizeof(ulong64);
  3422. ha->cmd_cnt = 0;
  3423. gdth_copy_command(hanum);
  3424. gdth_release_event(hanum);
  3425. return 0;
  3426. }
  3427. printk("\n");
  3428. } else {
  3429. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3430. t = scp->device->id;
  3431. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3432. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3433. }
  3434. /* cache or raw service */
  3435. if (ha->status == S_BSY) {
  3436. TRACE2(("Controller busy -> retry !\n"));
  3437. if (scp->SCp.sent_command == GDT_MOUNT)
  3438. scp->SCp.sent_command = GDT_CLUST_INFO;
  3439. /* retry */
  3440. return 2;
  3441. }
  3442. if (scp->SCp.Status == GDTH_MAP_SG)
  3443. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3444. scp->use_sg,scp->SCp.Message);
  3445. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3446. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3447. scp->request_bufflen,scp->SCp.Message);
  3448. if (scp->SCp.buffer) {
  3449. dma_addr_t addr;
  3450. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3451. if (scp->host_scribble)
  3452. addr += (dma_addr_t)
  3453. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3454. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3455. }
  3456. if (ha->status == S_OK) {
  3457. scp->SCp.Status = S_OK;
  3458. scp->SCp.Message = ha->info;
  3459. if (scp->SCp.sent_command != -1) {
  3460. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3461. scp->SCp.sent_command));
  3462. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3463. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3464. ha->hdr[t].cluster_type = (unchar)ha->info;
  3465. if (!(ha->hdr[t].cluster_type &
  3466. CLUSTER_MOUNTED)) {
  3467. /* NOT MOUNTED -> MOUNT */
  3468. scp->SCp.sent_command = GDT_MOUNT;
  3469. if (ha->hdr[t].cluster_type &
  3470. CLUSTER_RESERVED) {
  3471. /* cluster drive RESERVED (on the other node) */
  3472. scp->SCp.phase = -2; /* reservation conflict */
  3473. }
  3474. } else {
  3475. scp->SCp.sent_command = -1;
  3476. }
  3477. } else {
  3478. if (scp->SCp.sent_command == GDT_MOUNT) {
  3479. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3480. ha->hdr[t].media_changed = TRUE;
  3481. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3482. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3483. ha->hdr[t].media_changed = TRUE;
  3484. }
  3485. scp->SCp.sent_command = -1;
  3486. }
  3487. /* retry */
  3488. scp->SCp.this_residual = HIGH_PRI;
  3489. return 2;
  3490. } else {
  3491. /* RESERVE/RELEASE ? */
  3492. if (scp->cmnd[0] == RESERVE) {
  3493. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3494. } else if (scp->cmnd[0] == RELEASE) {
  3495. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3496. }
  3497. scp->result = DID_OK << 16;
  3498. scp->sense_buffer[0] = 0;
  3499. }
  3500. } else {
  3501. scp->SCp.Status = ha->status;
  3502. scp->SCp.Message = ha->info;
  3503. if (scp->SCp.sent_command != -1) {
  3504. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3505. scp->SCp.sent_command, ha->status));
  3506. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3507. scp->SCp.sent_command == GDT_SCAN_END) {
  3508. scp->SCp.sent_command = -1;
  3509. /* retry */
  3510. scp->SCp.this_residual = HIGH_PRI;
  3511. return 2;
  3512. }
  3513. memset((char*)scp->sense_buffer,0,16);
  3514. scp->sense_buffer[0] = 0x70;
  3515. scp->sense_buffer[2] = NOT_READY;
  3516. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3517. } else if (service == CACHESERVICE) {
  3518. if (ha->status == S_CACHE_UNKNOWN &&
  3519. (ha->hdr[t].cluster_type &
  3520. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3521. /* bus reset -> force GDT_CLUST_INFO */
  3522. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3523. }
  3524. memset((char*)scp->sense_buffer,0,16);
  3525. if (ha->status == (ushort)S_CACHE_RESERV) {
  3526. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3527. } else {
  3528. scp->sense_buffer[0] = 0x70;
  3529. scp->sense_buffer[2] = NOT_READY;
  3530. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3531. }
  3532. if (scp->done != gdth_scsi_done) {
  3533. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3534. ha->dvr.eu.sync.ionode = hanum;
  3535. ha->dvr.eu.sync.service = service;
  3536. ha->dvr.eu.sync.status = ha->status;
  3537. ha->dvr.eu.sync.info = ha->info;
  3538. ha->dvr.eu.sync.hostdrive = t;
  3539. if (ha->status >= 0x8000)
  3540. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3541. else
  3542. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3543. }
  3544. } else {
  3545. /* sense buffer filled from controller firmware (DMA) */
  3546. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3547. scp->result = DID_BAD_TARGET << 16;
  3548. } else {
  3549. scp->result = (DID_OK << 16) | ha->info;
  3550. }
  3551. }
  3552. }
  3553. if (!scp->SCp.have_data_in)
  3554. scp->SCp.have_data_in++;
  3555. else
  3556. return 1;
  3557. }
  3558. return 0;
  3559. }
  3560. static char *async_cache_tab[] = {
  3561. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3562. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3563. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3564. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3565. /* 2*/ "\005\000\002\006\004"
  3566. "GDT HA %u, Host Drive %lu not ready",
  3567. /* 3*/ "\005\000\002\006\004"
  3568. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3569. /* 4*/ "\005\000\002\006\004"
  3570. "GDT HA %u, mirror update on Host Drive %lu failed",
  3571. /* 5*/ "\005\000\002\006\004"
  3572. "GDT HA %u, Mirror Drive %lu failed",
  3573. /* 6*/ "\005\000\002\006\004"
  3574. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3575. /* 7*/ "\005\000\002\006\004"
  3576. "GDT HA %u, Host Drive %lu write protected",
  3577. /* 8*/ "\005\000\002\006\004"
  3578. "GDT HA %u, media changed in Host Drive %lu",
  3579. /* 9*/ "\005\000\002\006\004"
  3580. "GDT HA %u, Host Drive %lu is offline",
  3581. /*10*/ "\005\000\002\006\004"
  3582. "GDT HA %u, media change of Mirror Drive %lu",
  3583. /*11*/ "\005\000\002\006\004"
  3584. "GDT HA %u, Mirror Drive %lu is write protected",
  3585. /*12*/ "\005\000\002\006\004"
  3586. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3587. /*13*/ "\007\000\002\006\002\010\002"
  3588. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3589. /*14*/ "\005\000\002\006\002"
  3590. "GDT HA %u, Array Drive %u: FAIL state entered",
  3591. /*15*/ "\005\000\002\006\002"
  3592. "GDT HA %u, Array Drive %u: error",
  3593. /*16*/ "\007\000\002\006\002\010\002"
  3594. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3595. /*17*/ "\005\000\002\006\002"
  3596. "GDT HA %u, Array Drive %u: parity build failed",
  3597. /*18*/ "\005\000\002\006\002"
  3598. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3599. /*19*/ "\005\000\002\010\002"
  3600. "GDT HA %u, Test of Hot Fix %u failed",
  3601. /*20*/ "\005\000\002\006\002"
  3602. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3603. /*21*/ "\005\000\002\006\002"
  3604. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3605. /*22*/ "\007\000\002\006\002\010\002"
  3606. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3607. /*23*/ "\005\000\002\006\002"
  3608. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3609. /*24*/ "\005\000\002\010\002"
  3610. "GDT HA %u, mirror update on Cache Drive %u completed",
  3611. /*25*/ "\005\000\002\010\002"
  3612. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3613. /*26*/ "\005\000\002\006\002"
  3614. "GDT HA %u, Array Drive %u: drive rebuild started",
  3615. /*27*/ "\005\000\002\012\001"
  3616. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3617. /*28*/ "\005\000\002\012\001"
  3618. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3619. /*29*/ "\007\000\002\012\001\013\001"
  3620. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3621. /*30*/ "\007\000\002\012\001\013\001"
  3622. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3623. /*31*/ "\007\000\002\012\001\013\001"
  3624. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3625. /*32*/ "\007\000\002\012\001\013\001"
  3626. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3627. /*33*/ "\007\000\002\012\001\013\001"
  3628. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3629. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3630. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3631. /*35*/ "\007\000\002\012\001\013\001"
  3632. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3633. /*36*/ "\007\000\002\012\001\013\001"
  3634. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3635. /*37*/ "\007\000\002\012\001\006\004"
  3636. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3637. /*38*/ "\007\000\002\012\001\013\001"
  3638. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3639. /*39*/ "\007\000\002\012\001\013\001"
  3640. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3641. /*40*/ "\007\000\002\012\001\013\001"
  3642. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3643. /*41*/ "\007\000\002\012\001\013\001"
  3644. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3645. /*42*/ "\005\000\002\006\002"
  3646. "GDT HA %u, Array Drive %u: drive build started",
  3647. /*43*/ "\003\000\002"
  3648. "GDT HA %u, DRAM parity error detected",
  3649. /*44*/ "\005\000\002\006\002"
  3650. "GDT HA %u, Mirror Drive %u: update started",
  3651. /*45*/ "\007\000\002\006\002\010\002"
  3652. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3653. /*46*/ "\005\000\002\006\002"
  3654. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3655. /*47*/ "\005\000\002\006\002"
  3656. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3657. /*48*/ "\005\000\002\006\002"
  3658. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3659. /*49*/ "\005\000\002\006\002"
  3660. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3661. /*50*/ "\007\000\002\012\001\013\001"
  3662. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3663. /*51*/ "\005\000\002\006\002"
  3664. "GDT HA %u, Array Drive %u: expand started",
  3665. /*52*/ "\005\000\002\006\002"
  3666. "GDT HA %u, Array Drive %u: expand finished successfully",
  3667. /*53*/ "\005\000\002\006\002"
  3668. "GDT HA %u, Array Drive %u: expand failed",
  3669. /*54*/ "\003\000\002"
  3670. "GDT HA %u, CPU temperature critical",
  3671. /*55*/ "\003\000\002"
  3672. "GDT HA %u, CPU temperature OK",
  3673. /*56*/ "\005\000\002\006\004"
  3674. "GDT HA %u, Host drive %lu created",
  3675. /*57*/ "\005\000\002\006\002"
  3676. "GDT HA %u, Array Drive %u: expand restarted",
  3677. /*58*/ "\005\000\002\006\002"
  3678. "GDT HA %u, Array Drive %u: expand stopped",
  3679. /*59*/ "\005\000\002\010\002"
  3680. "GDT HA %u, Mirror Drive %u: drive build quited",
  3681. /*60*/ "\005\000\002\006\002"
  3682. "GDT HA %u, Array Drive %u: parity build quited",
  3683. /*61*/ "\005\000\002\006\002"
  3684. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3685. /*62*/ "\005\000\002\006\002"
  3686. "GDT HA %u, Array Drive %u: parity verify started",
  3687. /*63*/ "\005\000\002\006\002"
  3688. "GDT HA %u, Array Drive %u: parity verify done",
  3689. /*64*/ "\005\000\002\006\002"
  3690. "GDT HA %u, Array Drive %u: parity verify failed",
  3691. /*65*/ "\005\000\002\006\002"
  3692. "GDT HA %u, Array Drive %u: parity error detected",
  3693. /*66*/ "\005\000\002\006\002"
  3694. "GDT HA %u, Array Drive %u: parity verify quited",
  3695. /*67*/ "\005\000\002\006\002"
  3696. "GDT HA %u, Host Drive %u reserved",
  3697. /*68*/ "\005\000\002\006\002"
  3698. "GDT HA %u, Host Drive %u mounted and released",
  3699. /*69*/ "\005\000\002\006\002"
  3700. "GDT HA %u, Host Drive %u released",
  3701. /*70*/ "\003\000\002"
  3702. "GDT HA %u, DRAM error detected and corrected with ECC",
  3703. /*71*/ "\003\000\002"
  3704. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3705. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3706. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3707. /*73*/ "\005\000\002\006\002"
  3708. "GDT HA %u, Host drive %u resetted locally",
  3709. /*74*/ "\005\000\002\006\002"
  3710. "GDT HA %u, Host drive %u resetted remotely",
  3711. /*75*/ "\003\000\002"
  3712. "GDT HA %u, async. status 75 unknown",
  3713. };
  3714. static int gdth_async_event(int hanum)
  3715. {
  3716. gdth_ha_str *ha;
  3717. gdth_cmd_str *cmdp;
  3718. int cmd_index;
  3719. ha = HADATA(gdth_ctr_tab[hanum]);
  3720. cmdp= ha->pccb;
  3721. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3722. hanum,ha->service));
  3723. if (ha->service == SCREENSERVICE) {
  3724. if (ha->status == MSG_REQUEST) {
  3725. while (gdth_test_busy(hanum))
  3726. gdth_delay(0);
  3727. cmdp->Service = SCREENSERVICE;
  3728. cmdp->RequestBuffer = SCREEN_CMND;
  3729. cmd_index = gdth_get_cmd_index(hanum);
  3730. gdth_set_sema0(hanum);
  3731. cmdp->OpCode = GDT_READ;
  3732. cmdp->BoardNode = LOCALBOARD;
  3733. cmdp->u.screen.reserved = 0;
  3734. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3735. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3736. ha->cmd_offs_dpmem = 0;
  3737. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3738. + sizeof(ulong64);
  3739. ha->cmd_cnt = 0;
  3740. gdth_copy_command(hanum);
  3741. if (ha->type == GDT_EISA)
  3742. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3743. else if (ha->type == GDT_ISA)
  3744. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3745. else
  3746. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3747. (ushort)((ha->brd_phys>>3)&0x1f));
  3748. gdth_release_event(hanum);
  3749. }
  3750. } else {
  3751. if (ha->type == GDT_PCIMPR &&
  3752. (ha->fw_vers & 0xff) >= 0x1a) {
  3753. ha->dvr.size = 0;
  3754. ha->dvr.eu.async.ionode = hanum;
  3755. ha->dvr.eu.async.status = ha->status;
  3756. /* severity and event_string already set! */
  3757. } else {
  3758. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3759. ha->dvr.eu.async.ionode = hanum;
  3760. ha->dvr.eu.async.service = ha->service;
  3761. ha->dvr.eu.async.status = ha->status;
  3762. ha->dvr.eu.async.info = ha->info;
  3763. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3764. }
  3765. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3766. gdth_log_event( &ha->dvr, NULL );
  3767. /* new host drive from expand? */
  3768. if (ha->service == CACHESERVICE && ha->status == 56) {
  3769. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3770. (ushort)ha->info));
  3771. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3772. }
  3773. }
  3774. return 1;
  3775. }
  3776. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3777. {
  3778. gdth_stackframe stack;
  3779. char *f = NULL;
  3780. int i,j;
  3781. TRACE2(("gdth_log_event()\n"));
  3782. if (dvr->size == 0) {
  3783. if (buffer == NULL) {
  3784. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3785. } else {
  3786. sprintf(buffer,"Adapter %d: %s\n",
  3787. dvr->eu.async.ionode,dvr->event_string);
  3788. }
  3789. } else if (dvr->eu.async.service == CACHESERVICE &&
  3790. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3791. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3792. dvr->eu.async.status));
  3793. f = async_cache_tab[dvr->eu.async.status];
  3794. /* i: parameter to push, j: stack element to fill */
  3795. for (j=0,i=1; i < f[0]; i+=2) {
  3796. switch (f[i+1]) {
  3797. case 4:
  3798. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3799. break;
  3800. case 2:
  3801. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3802. break;
  3803. case 1:
  3804. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3805. break;
  3806. default:
  3807. break;
  3808. }
  3809. }
  3810. if (buffer == NULL) {
  3811. printk(&f[(int)f[0]],stack);
  3812. printk("\n");
  3813. } else {
  3814. sprintf(buffer,&f[(int)f[0]],stack);
  3815. }
  3816. } else {
  3817. if (buffer == NULL) {
  3818. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3819. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3820. } else {
  3821. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3822. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3823. }
  3824. }
  3825. }
  3826. #ifdef GDTH_STATISTICS
  3827. static void gdth_timeout(ulong data)
  3828. {
  3829. ulong32 i;
  3830. Scsi_Cmnd *nscp;
  3831. gdth_ha_str *ha;
  3832. ulong flags;
  3833. int hanum = 0;
  3834. ha = HADATA(gdth_ctr_tab[hanum]);
  3835. spin_lock_irqsave(&ha->smp_lock, flags);
  3836. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3837. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3838. ++act_stats;
  3839. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3840. ++act_rq;
  3841. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3842. act_ints, act_ios, act_stats, act_rq));
  3843. act_ints = act_ios = 0;
  3844. gdth_timer.expires = jiffies + 30 * HZ;
  3845. add_timer(&gdth_timer);
  3846. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3847. }
  3848. #endif
  3849. static void __init internal_setup(char *str,int *ints)
  3850. {
  3851. int i, argc;
  3852. char *cur_str, *argv;
  3853. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3854. str ? str:"NULL", ints ? ints[0]:0));
  3855. /* read irq[] from ints[] */
  3856. if (ints) {
  3857. argc = ints[0];
  3858. if (argc > 0) {
  3859. if (argc > MAXHA)
  3860. argc = MAXHA;
  3861. for (i = 0; i < argc; ++i)
  3862. irq[i] = ints[i+1];
  3863. }
  3864. }
  3865. /* analyse string */
  3866. argv = str;
  3867. while (argv && (cur_str = strchr(argv, ':'))) {
  3868. int val = 0, c = *++cur_str;
  3869. if (c == 'n' || c == 'N')
  3870. val = 0;
  3871. else if (c == 'y' || c == 'Y')
  3872. val = 1;
  3873. else
  3874. val = (int)simple_strtoul(cur_str, NULL, 0);
  3875. if (!strncmp(argv, "disable:", 8))
  3876. disable = val;
  3877. else if (!strncmp(argv, "reserve_mode:", 13))
  3878. reserve_mode = val;
  3879. else if (!strncmp(argv, "reverse_scan:", 13))
  3880. reverse_scan = val;
  3881. else if (!strncmp(argv, "hdr_channel:", 12))
  3882. hdr_channel = val;
  3883. else if (!strncmp(argv, "max_ids:", 8))
  3884. max_ids = val;
  3885. else if (!strncmp(argv, "rescan:", 7))
  3886. rescan = val;
  3887. else if (!strncmp(argv, "virt_ctr:", 9))
  3888. virt_ctr = val;
  3889. else if (!strncmp(argv, "shared_access:", 14))
  3890. shared_access = val;
  3891. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3892. probe_eisa_isa = val;
  3893. else if (!strncmp(argv, "reserve_list:", 13)) {
  3894. reserve_list[0] = val;
  3895. for (i = 1; i < MAX_RES_ARGS; i++) {
  3896. cur_str = strchr(cur_str, ',');
  3897. if (!cur_str)
  3898. break;
  3899. if (!isdigit((int)*++cur_str)) {
  3900. --cur_str;
  3901. break;
  3902. }
  3903. reserve_list[i] =
  3904. (int)simple_strtoul(cur_str, NULL, 0);
  3905. }
  3906. if (!cur_str)
  3907. break;
  3908. argv = ++cur_str;
  3909. continue;
  3910. }
  3911. if ((argv = strchr(argv, ',')))
  3912. ++argv;
  3913. }
  3914. }
  3915. int __init option_setup(char *str)
  3916. {
  3917. int ints[MAXHA];
  3918. char *cur = str;
  3919. int i = 1;
  3920. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3921. while (cur && isdigit(*cur) && i <= MAXHA) {
  3922. ints[i++] = simple_strtoul(cur, NULL, 0);
  3923. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3924. }
  3925. ints[0] = i - 1;
  3926. internal_setup(cur, ints);
  3927. return 1;
  3928. }
  3929. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  3930. static int __init gdth_detect(struct scsi_host_template *shtp)
  3931. #else
  3932. static int __init gdth_detect(Scsi_Host_Template *shtp)
  3933. #endif
  3934. {
  3935. struct Scsi_Host *shp;
  3936. gdth_pci_str pcistr[MAXHA];
  3937. gdth_ha_str *ha;
  3938. ulong32 isa_bios;
  3939. ushort eisa_slot;
  3940. int i,hanum,cnt,ctr,err;
  3941. unchar b;
  3942. #ifdef DEBUG_GDTH
  3943. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3944. DebugState);
  3945. printk(" Destination of debugging information: ");
  3946. #ifdef __SERIAL__
  3947. #ifdef __COM2__
  3948. printk("Serial port COM2\n");
  3949. #else
  3950. printk("Serial port COM1\n");
  3951. #endif
  3952. #else
  3953. printk("Console\n");
  3954. #endif
  3955. gdth_delay(3000);
  3956. #endif
  3957. TRACE(("gdth_detect()\n"));
  3958. if (disable) {
  3959. printk("GDT-HA: Controller driver disabled from command line !\n");
  3960. return 0;
  3961. }
  3962. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
  3963. /* initializations */
  3964. gdth_polling = TRUE; b = 0;
  3965. gdth_clear_events();
  3966. /* As default we do not probe for EISA or ISA controllers */
  3967. if (probe_eisa_isa) {
  3968. /* scanning for controllers, at first: ISA controller */
  3969. for (isa_bios=0xc8000UL; isa_bios<=0xd8000UL; isa_bios+=0x8000UL) {
  3970. dma_addr_t scratch_dma_handle;
  3971. scratch_dma_handle = 0;
  3972. if (gdth_ctr_count >= MAXHA)
  3973. break;
  3974. if (gdth_search_isa(isa_bios)) { /* controller found */
  3975. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  3976. if (shp == NULL)
  3977. continue;
  3978. ha = HADATA(shp);
  3979. if (!gdth_init_isa(isa_bios,ha)) {
  3980. scsi_unregister(shp);
  3981. continue;
  3982. }
  3983. #ifdef __ia64__
  3984. break;
  3985. #else
  3986. /* controller found and initialized */
  3987. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  3988. isa_bios,ha->irq,ha->drq);
  3989. if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
  3990. printk("GDT-ISA: Unable to allocate IRQ\n");
  3991. scsi_unregister(shp);
  3992. continue;
  3993. }
  3994. if (request_dma(ha->drq,"gdth")) {
  3995. printk("GDT-ISA: Unable to allocate DMA channel\n");
  3996. free_irq(ha->irq,ha);
  3997. scsi_unregister(shp);
  3998. continue;
  3999. }
  4000. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4001. enable_dma(ha->drq);
  4002. shp->unchecked_isa_dma = 1;
  4003. shp->irq = ha->irq;
  4004. shp->dma_channel = ha->drq;
  4005. hanum = gdth_ctr_count;
  4006. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4007. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4008. NUMDATA(shp)->hanum = (ushort)hanum;
  4009. NUMDATA(shp)->busnum= 0;
  4010. ha->pccb = CMDDATA(shp);
  4011. ha->ccb_phys = 0L;
  4012. ha->pdev = NULL;
  4013. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4014. &scratch_dma_handle);
  4015. ha->scratch_phys = scratch_dma_handle;
  4016. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4017. &scratch_dma_handle);
  4018. ha->msg_phys = scratch_dma_handle;
  4019. #ifdef INT_COAL
  4020. ha->coal_stat = (gdth_coal_status *)
  4021. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4022. MAXOFFSETS, &scratch_dma_handle);
  4023. ha->coal_stat_phys = scratch_dma_handle;
  4024. #endif
  4025. ha->scratch_busy = FALSE;
  4026. ha->req_first = NULL;
  4027. ha->tid_cnt = MAX_HDRIVES;
  4028. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4029. ha->tid_cnt = max_ids;
  4030. for (i=0; i<GDTH_MAXCMDS; ++i)
  4031. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4032. ha->scan_mode = rescan ? 0x10 : 0;
  4033. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4034. !gdth_search_drives(hanum)) {
  4035. printk("GDT-ISA: Error during device scan\n");
  4036. --gdth_ctr_count;
  4037. --gdth_ctr_vcount;
  4038. #ifdef INT_COAL
  4039. if (ha->coal_stat)
  4040. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4041. MAXOFFSETS, ha->coal_stat,
  4042. ha->coal_stat_phys);
  4043. #endif
  4044. if (ha->pscratch)
  4045. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4046. ha->pscratch, ha->scratch_phys);
  4047. if (ha->pmsg)
  4048. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4049. ha->pmsg, ha->msg_phys);
  4050. free_irq(ha->irq,ha);
  4051. scsi_unregister(shp);
  4052. continue;
  4053. }
  4054. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4055. hdr_channel = ha->bus_cnt;
  4056. ha->virt_bus = hdr_channel;
  4057. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4058. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4059. shp->highmem_io = 0;
  4060. #endif
  4061. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4062. shp->max_cmd_len = 16;
  4063. shp->max_id = ha->tid_cnt;
  4064. shp->max_lun = MAXLUN;
  4065. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4066. if (virt_ctr) {
  4067. virt_ctr = 1;
  4068. /* register addit. SCSI channels as virtual controllers */
  4069. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4070. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4071. shp->unchecked_isa_dma = 1;
  4072. shp->irq = ha->irq;
  4073. shp->dma_channel = ha->drq;
  4074. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4075. NUMDATA(shp)->hanum = (ushort)hanum;
  4076. NUMDATA(shp)->busnum = b;
  4077. }
  4078. }
  4079. spin_lock_init(&ha->smp_lock);
  4080. gdth_enable_int(hanum);
  4081. #endif /* !__ia64__ */
  4082. }
  4083. }
  4084. /* scanning for EISA controllers */
  4085. for (eisa_slot=0x1000; eisa_slot<=0x8000; eisa_slot+=0x1000) {
  4086. dma_addr_t scratch_dma_handle;
  4087. scratch_dma_handle = 0;
  4088. if (gdth_ctr_count >= MAXHA)
  4089. break;
  4090. if (gdth_search_eisa(eisa_slot)) { /* controller found */
  4091. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4092. if (shp == NULL)
  4093. continue;
  4094. ha = HADATA(shp);
  4095. if (!gdth_init_eisa(eisa_slot,ha)) {
  4096. scsi_unregister(shp);
  4097. continue;
  4098. }
  4099. /* controller found and initialized */
  4100. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  4101. eisa_slot>>12,ha->irq);
  4102. if (request_irq(ha->irq,gdth_interrupt,IRQF_DISABLED,"gdth",ha)) {
  4103. printk("GDT-EISA: Unable to allocate IRQ\n");
  4104. scsi_unregister(shp);
  4105. continue;
  4106. }
  4107. shp->unchecked_isa_dma = 0;
  4108. shp->irq = ha->irq;
  4109. shp->dma_channel = 0xff;
  4110. hanum = gdth_ctr_count;
  4111. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4112. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4113. NUMDATA(shp)->hanum = (ushort)hanum;
  4114. NUMDATA(shp)->busnum= 0;
  4115. TRACE2(("EISA detect Bus 0: hanum %d\n",
  4116. NUMDATA(shp)->hanum));
  4117. ha->pccb = CMDDATA(shp);
  4118. ha->ccb_phys = 0L;
  4119. ha->pdev = NULL;
  4120. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4121. &scratch_dma_handle);
  4122. ha->scratch_phys = scratch_dma_handle;
  4123. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4124. &scratch_dma_handle);
  4125. ha->msg_phys = scratch_dma_handle;
  4126. #ifdef INT_COAL
  4127. ha->coal_stat = (gdth_coal_status *)
  4128. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4129. MAXOFFSETS, &scratch_dma_handle);
  4130. ha->coal_stat_phys = scratch_dma_handle;
  4131. #endif
  4132. ha->ccb_phys =
  4133. pci_map_single(ha->pdev,ha->pccb,
  4134. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4135. ha->scratch_busy = FALSE;
  4136. ha->req_first = NULL;
  4137. ha->tid_cnt = MAX_HDRIVES;
  4138. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4139. ha->tid_cnt = max_ids;
  4140. for (i=0; i<GDTH_MAXCMDS; ++i)
  4141. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4142. ha->scan_mode = rescan ? 0x10 : 0;
  4143. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4144. !gdth_search_drives(hanum)) {
  4145. printk("GDT-EISA: Error during device scan\n");
  4146. --gdth_ctr_count;
  4147. --gdth_ctr_vcount;
  4148. #ifdef INT_COAL
  4149. if (ha->coal_stat)
  4150. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4151. MAXOFFSETS, ha->coal_stat,
  4152. ha->coal_stat_phys);
  4153. #endif
  4154. if (ha->pscratch)
  4155. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4156. ha->pscratch, ha->scratch_phys);
  4157. if (ha->pmsg)
  4158. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4159. ha->pmsg, ha->msg_phys);
  4160. if (ha->ccb_phys)
  4161. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4162. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4163. free_irq(ha->irq,ha);
  4164. scsi_unregister(shp);
  4165. continue;
  4166. }
  4167. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4168. hdr_channel = ha->bus_cnt;
  4169. ha->virt_bus = hdr_channel;
  4170. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && \
  4171. LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4172. shp->highmem_io = 0;
  4173. #endif
  4174. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  4175. shp->max_cmd_len = 16;
  4176. shp->max_id = ha->tid_cnt;
  4177. shp->max_lun = MAXLUN;
  4178. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4179. if (virt_ctr) {
  4180. virt_ctr = 1;
  4181. /* register addit. SCSI channels as virtual controllers */
  4182. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4183. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4184. shp->unchecked_isa_dma = 0;
  4185. shp->irq = ha->irq;
  4186. shp->dma_channel = 0xff;
  4187. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4188. NUMDATA(shp)->hanum = (ushort)hanum;
  4189. NUMDATA(shp)->busnum = b;
  4190. }
  4191. }
  4192. spin_lock_init(&ha->smp_lock);
  4193. gdth_enable_int(hanum);
  4194. }
  4195. }
  4196. }
  4197. /* scanning for PCI controllers */
  4198. cnt = gdth_search_pci(pcistr);
  4199. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4200. gdth_sort_pci(pcistr,cnt);
  4201. for (ctr = 0; ctr < cnt; ++ctr) {
  4202. dma_addr_t scratch_dma_handle;
  4203. scratch_dma_handle = 0;
  4204. if (gdth_ctr_count >= MAXHA)
  4205. break;
  4206. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4207. if (shp == NULL)
  4208. continue;
  4209. ha = HADATA(shp);
  4210. if (!gdth_init_pci(&pcistr[ctr],ha)) {
  4211. scsi_unregister(shp);
  4212. continue;
  4213. }
  4214. /* controller found and initialized */
  4215. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4216. pcistr[ctr].bus,PCI_SLOT(pcistr[ctr].device_fn),ha->irq);
  4217. if (request_irq(ha->irq, gdth_interrupt,
  4218. IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
  4219. {
  4220. printk("GDT-PCI: Unable to allocate IRQ\n");
  4221. scsi_unregister(shp);
  4222. continue;
  4223. }
  4224. shp->unchecked_isa_dma = 0;
  4225. shp->irq = ha->irq;
  4226. shp->dma_channel = 0xff;
  4227. hanum = gdth_ctr_count;
  4228. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4229. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4230. NUMDATA(shp)->hanum = (ushort)hanum;
  4231. NUMDATA(shp)->busnum= 0;
  4232. ha->pccb = CMDDATA(shp);
  4233. ha->ccb_phys = 0L;
  4234. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4235. &scratch_dma_handle);
  4236. ha->scratch_phys = scratch_dma_handle;
  4237. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4238. &scratch_dma_handle);
  4239. ha->msg_phys = scratch_dma_handle;
  4240. #ifdef INT_COAL
  4241. ha->coal_stat = (gdth_coal_status *)
  4242. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4243. MAXOFFSETS, &scratch_dma_handle);
  4244. ha->coal_stat_phys = scratch_dma_handle;
  4245. #endif
  4246. ha->scratch_busy = FALSE;
  4247. ha->req_first = NULL;
  4248. ha->tid_cnt = pcistr[ctr].device_id >= 0x200 ? MAXID : MAX_HDRIVES;
  4249. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4250. ha->tid_cnt = max_ids;
  4251. for (i=0; i<GDTH_MAXCMDS; ++i)
  4252. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4253. ha->scan_mode = rescan ? 0x10 : 0;
  4254. err = FALSE;
  4255. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4256. !gdth_search_drives(hanum)) {
  4257. err = TRUE;
  4258. } else {
  4259. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4260. hdr_channel = ha->bus_cnt;
  4261. ha->virt_bus = hdr_channel;
  4262. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4263. scsi_set_pci_device(shp, pcistr[ctr].pdev);
  4264. #endif
  4265. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
  4266. /* 64-bit DMA only supported from FW >= x.43 */
  4267. (!ha->dma64_support)) {
  4268. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4269. printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
  4270. err = TRUE;
  4271. }
  4272. } else {
  4273. shp->max_cmd_len = 16;
  4274. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4275. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4276. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4277. printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
  4278. err = TRUE;
  4279. }
  4280. }
  4281. }
  4282. if (err) {
  4283. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4284. --gdth_ctr_count;
  4285. --gdth_ctr_vcount;
  4286. #ifdef INT_COAL
  4287. if (ha->coal_stat)
  4288. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4289. MAXOFFSETS, ha->coal_stat,
  4290. ha->coal_stat_phys);
  4291. #endif
  4292. if (ha->pscratch)
  4293. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4294. ha->pscratch, ha->scratch_phys);
  4295. if (ha->pmsg)
  4296. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4297. ha->pmsg, ha->msg_phys);
  4298. free_irq(ha->irq,ha);
  4299. scsi_unregister(shp);
  4300. continue;
  4301. }
  4302. shp->max_id = ha->tid_cnt;
  4303. shp->max_lun = MAXLUN;
  4304. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4305. if (virt_ctr) {
  4306. virt_ctr = 1;
  4307. /* register addit. SCSI channels as virtual controllers */
  4308. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4309. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4310. shp->unchecked_isa_dma = 0;
  4311. shp->irq = ha->irq;
  4312. shp->dma_channel = 0xff;
  4313. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4314. NUMDATA(shp)->hanum = (ushort)hanum;
  4315. NUMDATA(shp)->busnum = b;
  4316. }
  4317. }
  4318. spin_lock_init(&ha->smp_lock);
  4319. gdth_enable_int(hanum);
  4320. }
  4321. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4322. if (gdth_ctr_count > 0) {
  4323. #ifdef GDTH_STATISTICS
  4324. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4325. init_timer(&gdth_timer);
  4326. gdth_timer.expires = jiffies + HZ;
  4327. gdth_timer.data = 0L;
  4328. gdth_timer.function = gdth_timeout;
  4329. add_timer(&gdth_timer);
  4330. #endif
  4331. major = register_chrdev(0,"gdth",&gdth_fops);
  4332. notifier_disabled = 0;
  4333. register_reboot_notifier(&gdth_notifier);
  4334. }
  4335. gdth_polling = FALSE;
  4336. return gdth_ctr_vcount;
  4337. }
  4338. static int gdth_release(struct Scsi_Host *shp)
  4339. {
  4340. int hanum;
  4341. gdth_ha_str *ha;
  4342. TRACE2(("gdth_release()\n"));
  4343. if (NUMDATA(shp)->busnum == 0) {
  4344. hanum = NUMDATA(shp)->hanum;
  4345. ha = HADATA(gdth_ctr_tab[hanum]);
  4346. if (ha->sdev) {
  4347. scsi_free_host_dev(ha->sdev);
  4348. ha->sdev = NULL;
  4349. }
  4350. gdth_flush(hanum);
  4351. if (shp->irq) {
  4352. free_irq(shp->irq,ha);
  4353. }
  4354. #ifndef __ia64__
  4355. if (shp->dma_channel != 0xff) {
  4356. free_dma(shp->dma_channel);
  4357. }
  4358. #endif
  4359. #ifdef INT_COAL
  4360. if (ha->coal_stat)
  4361. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4362. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4363. #endif
  4364. if (ha->pscratch)
  4365. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4366. ha->pscratch, ha->scratch_phys);
  4367. if (ha->pmsg)
  4368. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4369. ha->pmsg, ha->msg_phys);
  4370. if (ha->ccb_phys)
  4371. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4372. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4373. gdth_ctr_released++;
  4374. TRACE2(("gdth_release(): HA %d of %d\n",
  4375. gdth_ctr_released, gdth_ctr_count));
  4376. if (gdth_ctr_released == gdth_ctr_count) {
  4377. #ifdef GDTH_STATISTICS
  4378. del_timer(&gdth_timer);
  4379. #endif
  4380. unregister_chrdev(major,"gdth");
  4381. unregister_reboot_notifier(&gdth_notifier);
  4382. }
  4383. }
  4384. scsi_unregister(shp);
  4385. return 0;
  4386. }
  4387. static const char *gdth_ctr_name(int hanum)
  4388. {
  4389. gdth_ha_str *ha;
  4390. TRACE2(("gdth_ctr_name()\n"));
  4391. ha = HADATA(gdth_ctr_tab[hanum]);
  4392. if (ha->type == GDT_EISA) {
  4393. switch (ha->stype) {
  4394. case GDT3_ID:
  4395. return("GDT3000/3020");
  4396. case GDT3A_ID:
  4397. return("GDT3000A/3020A/3050A");
  4398. case GDT3B_ID:
  4399. return("GDT3000B/3010A");
  4400. }
  4401. } else if (ha->type == GDT_ISA) {
  4402. return("GDT2000/2020");
  4403. } else if (ha->type == GDT_PCI) {
  4404. switch (ha->stype) {
  4405. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4406. return("GDT6000/6020/6050");
  4407. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4408. return("GDT6000B/6010");
  4409. }
  4410. }
  4411. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4412. return("");
  4413. }
  4414. static const char *gdth_info(struct Scsi_Host *shp)
  4415. {
  4416. int hanum;
  4417. gdth_ha_str *ha;
  4418. TRACE2(("gdth_info()\n"));
  4419. hanum = NUMDATA(shp)->hanum;
  4420. ha = HADATA(gdth_ctr_tab[hanum]);
  4421. return ((const char *)ha->binfo.type_string);
  4422. }
  4423. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4424. {
  4425. int i, hanum;
  4426. gdth_ha_str *ha;
  4427. ulong flags;
  4428. Scsi_Cmnd *cmnd;
  4429. unchar b;
  4430. TRACE2(("gdth_eh_bus_reset()\n"));
  4431. hanum = NUMDATA(scp->device->host)->hanum;
  4432. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4433. ha = HADATA(gdth_ctr_tab[hanum]);
  4434. /* clear command tab */
  4435. spin_lock_irqsave(&ha->smp_lock, flags);
  4436. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4437. cmnd = ha->cmd_tab[i].cmnd;
  4438. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4439. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4440. }
  4441. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4442. if (b == ha->virt_bus) {
  4443. /* host drives */
  4444. for (i = 0; i < MAX_HDRIVES; ++i) {
  4445. if (ha->hdr[i].present) {
  4446. spin_lock_irqsave(&ha->smp_lock, flags);
  4447. gdth_polling = TRUE;
  4448. while (gdth_test_busy(hanum))
  4449. gdth_delay(0);
  4450. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4451. GDT_CLUST_RESET, i, 0, 0))
  4452. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4453. gdth_polling = FALSE;
  4454. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4455. }
  4456. }
  4457. } else {
  4458. /* raw devices */
  4459. spin_lock_irqsave(&ha->smp_lock, flags);
  4460. for (i = 0; i < MAXID; ++i)
  4461. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4462. gdth_polling = TRUE;
  4463. while (gdth_test_busy(hanum))
  4464. gdth_delay(0);
  4465. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4466. BUS_L2P(ha,b), 0, 0);
  4467. gdth_polling = FALSE;
  4468. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4469. }
  4470. return SUCCESS;
  4471. }
  4472. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4473. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4474. #else
  4475. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4476. #endif
  4477. {
  4478. unchar b, t;
  4479. int hanum;
  4480. gdth_ha_str *ha;
  4481. struct scsi_device *sd;
  4482. unsigned capacity;
  4483. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4484. sd = sdev;
  4485. capacity = cap;
  4486. #else
  4487. sd = disk->device;
  4488. capacity = disk->capacity;
  4489. #endif
  4490. hanum = NUMDATA(sd->host)->hanum;
  4491. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4492. t = sd->id;
  4493. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4494. ha = HADATA(gdth_ctr_tab[hanum]);
  4495. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4496. /* raw device or host drive without mapping information */
  4497. TRACE2(("Evaluate mapping\n"));
  4498. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4499. } else {
  4500. ip[0] = ha->hdr[t].heads;
  4501. ip[1] = ha->hdr[t].secs;
  4502. ip[2] = capacity / ip[0] / ip[1];
  4503. }
  4504. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4505. ip[0],ip[1],ip[2]));
  4506. return 0;
  4507. }
  4508. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *))
  4509. {
  4510. int hanum;
  4511. int priority;
  4512. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4513. scp->scsi_done = (void *)done;
  4514. scp->SCp.have_data_in = 1;
  4515. scp->SCp.phase = -1;
  4516. scp->SCp.sent_command = -1;
  4517. scp->SCp.Status = GDTH_MAP_NONE;
  4518. scp->SCp.buffer = (struct scatterlist *)NULL;
  4519. hanum = NUMDATA(scp->device->host)->hanum;
  4520. #ifdef GDTH_STATISTICS
  4521. ++act_ios;
  4522. #endif
  4523. priority = DEFAULT_PRI;
  4524. if (scp->done == gdth_scsi_done)
  4525. priority = scp->SCp.this_residual;
  4526. else
  4527. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4528. gdth_putq( hanum, scp, priority );
  4529. gdth_next( hanum );
  4530. return 0;
  4531. }
  4532. static int gdth_open(struct inode *inode, struct file *filep)
  4533. {
  4534. gdth_ha_str *ha;
  4535. int i;
  4536. for (i = 0; i < gdth_ctr_count; i++) {
  4537. ha = HADATA(gdth_ctr_tab[i]);
  4538. if (!ha->sdev)
  4539. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4540. }
  4541. TRACE(("gdth_open()\n"));
  4542. return 0;
  4543. }
  4544. static int gdth_close(struct inode *inode, struct file *filep)
  4545. {
  4546. TRACE(("gdth_close()\n"));
  4547. return 0;
  4548. }
  4549. static int ioc_event(void __user *arg)
  4550. {
  4551. gdth_ioctl_event evt;
  4552. gdth_ha_str *ha;
  4553. ulong flags;
  4554. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4555. evt.ionode >= gdth_ctr_count)
  4556. return -EFAULT;
  4557. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4558. if (evt.erase == 0xff) {
  4559. if (evt.event.event_source == ES_TEST)
  4560. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4561. else if (evt.event.event_source == ES_DRIVER)
  4562. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4563. else if (evt.event.event_source == ES_SYNC)
  4564. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4565. else
  4566. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4567. spin_lock_irqsave(&ha->smp_lock, flags);
  4568. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4569. &evt.event.event_data);
  4570. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4571. } else if (evt.erase == 0xfe) {
  4572. gdth_clear_events();
  4573. } else if (evt.erase == 0) {
  4574. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4575. } else {
  4576. gdth_readapp_event(ha, evt.erase, &evt.event);
  4577. }
  4578. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4579. return -EFAULT;
  4580. return 0;
  4581. }
  4582. static int ioc_lockdrv(void __user *arg)
  4583. {
  4584. gdth_ioctl_lockdrv ldrv;
  4585. unchar i, j;
  4586. ulong flags;
  4587. gdth_ha_str *ha;
  4588. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4589. ldrv.ionode >= gdth_ctr_count)
  4590. return -EFAULT;
  4591. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4592. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4593. j = ldrv.drives[i];
  4594. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4595. continue;
  4596. if (ldrv.lock) {
  4597. spin_lock_irqsave(&ha->smp_lock, flags);
  4598. ha->hdr[j].lock = 1;
  4599. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4600. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4601. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4602. } else {
  4603. spin_lock_irqsave(&ha->smp_lock, flags);
  4604. ha->hdr[j].lock = 0;
  4605. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4606. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4607. gdth_next(ldrv.ionode);
  4608. }
  4609. }
  4610. return 0;
  4611. }
  4612. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4613. {
  4614. gdth_ioctl_reset res;
  4615. gdth_cmd_str cmd;
  4616. int hanum;
  4617. gdth_ha_str *ha;
  4618. int rval;
  4619. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4620. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4621. return -EFAULT;
  4622. hanum = res.ionode;
  4623. ha = HADATA(gdth_ctr_tab[hanum]);
  4624. if (!ha->hdr[res.number].present)
  4625. return 0;
  4626. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4627. cmd.Service = CACHESERVICE;
  4628. cmd.OpCode = GDT_CLUST_RESET;
  4629. if (ha->cache_feat & GDT_64BIT)
  4630. cmd.u.cache64.DeviceNo = res.number;
  4631. else
  4632. cmd.u.cache.DeviceNo = res.number;
  4633. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  4634. if (rval < 0)
  4635. return rval;
  4636. res.status = rval;
  4637. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4638. return -EFAULT;
  4639. return 0;
  4640. }
  4641. static int ioc_general(void __user *arg, char *cmnd)
  4642. {
  4643. gdth_ioctl_general gen;
  4644. char *buf = NULL;
  4645. ulong64 paddr;
  4646. int hanum;
  4647. gdth_ha_str *ha;
  4648. int rval;
  4649. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4650. gen.ionode >= gdth_ctr_count)
  4651. return -EFAULT;
  4652. hanum = gen.ionode;
  4653. ha = HADATA(gdth_ctr_tab[hanum]);
  4654. if (gen.data_len + gen.sense_len != 0) {
  4655. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4656. FALSE, &paddr)))
  4657. return -EFAULT;
  4658. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4659. gen.data_len + gen.sense_len)) {
  4660. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4661. return -EFAULT;
  4662. }
  4663. if (gen.command.OpCode == GDT_IOCTL) {
  4664. gen.command.u.ioctl.p_param = paddr;
  4665. } else if (gen.command.Service == CACHESERVICE) {
  4666. if (ha->cache_feat & GDT_64BIT) {
  4667. /* copy elements from 32-bit IOCTL structure */
  4668. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4669. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4670. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4671. /* addresses */
  4672. if (ha->cache_feat & SCATTER_GATHER) {
  4673. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4674. gen.command.u.cache64.sg_canz = 1;
  4675. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4676. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4677. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4678. } else {
  4679. gen.command.u.cache64.DestAddr = paddr;
  4680. gen.command.u.cache64.sg_canz = 0;
  4681. }
  4682. } else {
  4683. if (ha->cache_feat & SCATTER_GATHER) {
  4684. gen.command.u.cache.DestAddr = 0xffffffff;
  4685. gen.command.u.cache.sg_canz = 1;
  4686. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4687. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4688. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4689. } else {
  4690. gen.command.u.cache.DestAddr = paddr;
  4691. gen.command.u.cache.sg_canz = 0;
  4692. }
  4693. }
  4694. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4695. if (ha->raw_feat & GDT_64BIT) {
  4696. /* copy elements from 32-bit IOCTL structure */
  4697. char cmd[16];
  4698. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4699. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4700. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4701. gen.command.u.raw64.target = gen.command.u.raw.target;
  4702. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4703. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4704. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4705. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4706. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4707. /* addresses */
  4708. if (ha->raw_feat & SCATTER_GATHER) {
  4709. gen.command.u.raw64.sdata = (ulong64)-1;
  4710. gen.command.u.raw64.sg_ranz = 1;
  4711. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4712. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4713. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4714. } else {
  4715. gen.command.u.raw64.sdata = paddr;
  4716. gen.command.u.raw64.sg_ranz = 0;
  4717. }
  4718. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4719. } else {
  4720. if (ha->raw_feat & SCATTER_GATHER) {
  4721. gen.command.u.raw.sdata = 0xffffffff;
  4722. gen.command.u.raw.sg_ranz = 1;
  4723. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4724. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4725. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4726. } else {
  4727. gen.command.u.raw.sdata = paddr;
  4728. gen.command.u.raw.sg_ranz = 0;
  4729. }
  4730. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4731. }
  4732. } else {
  4733. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4734. return -EFAULT;
  4735. }
  4736. }
  4737. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  4738. if (rval < 0)
  4739. return rval;
  4740. gen.status = rval;
  4741. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4742. gen.data_len + gen.sense_len)) {
  4743. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4744. return -EFAULT;
  4745. }
  4746. if (copy_to_user(arg, &gen,
  4747. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4748. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4749. return -EFAULT;
  4750. }
  4751. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4752. return 0;
  4753. }
  4754. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4755. {
  4756. gdth_ioctl_rescan *rsc;
  4757. gdth_cmd_str *cmd;
  4758. gdth_ha_str *ha;
  4759. unchar i;
  4760. int hanum, rc = -ENOMEM;
  4761. u32 cluster_type = 0;
  4762. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4763. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4764. if (!rsc || !cmd)
  4765. goto free_fail;
  4766. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4767. rsc->ionode >= gdth_ctr_count) {
  4768. rc = -EFAULT;
  4769. goto free_fail;
  4770. }
  4771. hanum = rsc->ionode;
  4772. ha = HADATA(gdth_ctr_tab[hanum]);
  4773. memset(cmd, 0, sizeof(gdth_cmd_str));
  4774. for (i = 0; i < MAX_HDRIVES; ++i) {
  4775. if (!ha->hdr[i].present) {
  4776. rsc->hdr_list[i].bus = 0xff;
  4777. continue;
  4778. }
  4779. rsc->hdr_list[i].bus = ha->virt_bus;
  4780. rsc->hdr_list[i].target = i;
  4781. rsc->hdr_list[i].lun = 0;
  4782. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4783. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4784. cmd->Service = CACHESERVICE;
  4785. cmd->OpCode = GDT_CLUST_INFO;
  4786. if (ha->cache_feat & GDT_64BIT)
  4787. cmd->u.cache64.DeviceNo = i;
  4788. else
  4789. cmd->u.cache.DeviceNo = i;
  4790. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  4791. rsc->hdr_list[i].cluster_type = cluster_type;
  4792. }
  4793. }
  4794. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4795. rc = -EFAULT;
  4796. else
  4797. rc = 0;
  4798. free_fail:
  4799. kfree(rsc);
  4800. kfree(cmd);
  4801. return rc;
  4802. }
  4803. static int ioc_rescan(void __user *arg, char *cmnd)
  4804. {
  4805. gdth_ioctl_rescan *rsc;
  4806. gdth_cmd_str *cmd;
  4807. ushort i, status, hdr_cnt;
  4808. ulong32 info;
  4809. int hanum, cyls, hds, secs;
  4810. int rc = -ENOMEM;
  4811. ulong flags;
  4812. gdth_ha_str *ha;
  4813. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4814. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4815. if (!cmd || !rsc)
  4816. goto free_fail;
  4817. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4818. rsc->ionode >= gdth_ctr_count) {
  4819. rc = -EFAULT;
  4820. goto free_fail;
  4821. }
  4822. hanum = rsc->ionode;
  4823. ha = HADATA(gdth_ctr_tab[hanum]);
  4824. memset(cmd, 0, sizeof(gdth_cmd_str));
  4825. if (rsc->flag == 0) {
  4826. /* old method: re-init. cache service */
  4827. cmd->Service = CACHESERVICE;
  4828. if (ha->cache_feat & GDT_64BIT) {
  4829. cmd->OpCode = GDT_X_INIT_HOST;
  4830. cmd->u.cache64.DeviceNo = LINUX_OS;
  4831. } else {
  4832. cmd->OpCode = GDT_INIT;
  4833. cmd->u.cache.DeviceNo = LINUX_OS;
  4834. }
  4835. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4836. i = 0;
  4837. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4838. } else {
  4839. i = rsc->hdr_no;
  4840. hdr_cnt = i + 1;
  4841. }
  4842. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4843. cmd->Service = CACHESERVICE;
  4844. cmd->OpCode = GDT_INFO;
  4845. if (ha->cache_feat & GDT_64BIT)
  4846. cmd->u.cache64.DeviceNo = i;
  4847. else
  4848. cmd->u.cache.DeviceNo = i;
  4849. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4850. spin_lock_irqsave(&ha->smp_lock, flags);
  4851. rsc->hdr_list[i].bus = ha->virt_bus;
  4852. rsc->hdr_list[i].target = i;
  4853. rsc->hdr_list[i].lun = 0;
  4854. if (status != S_OK) {
  4855. ha->hdr[i].present = FALSE;
  4856. } else {
  4857. ha->hdr[i].present = TRUE;
  4858. ha->hdr[i].size = info;
  4859. /* evaluate mapping */
  4860. ha->hdr[i].size &= ~SECS32;
  4861. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4862. ha->hdr[i].heads = hds;
  4863. ha->hdr[i].secs = secs;
  4864. /* round size */
  4865. ha->hdr[i].size = cyls * hds * secs;
  4866. }
  4867. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4868. if (status != S_OK)
  4869. continue;
  4870. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4871. /* but we need ha->info2, not yet stored in scp->SCp */
  4872. /* devtype, cluster info, R/W attribs */
  4873. cmd->Service = CACHESERVICE;
  4874. cmd->OpCode = GDT_DEVTYPE;
  4875. if (ha->cache_feat & GDT_64BIT)
  4876. cmd->u.cache64.DeviceNo = i;
  4877. else
  4878. cmd->u.cache.DeviceNo = i;
  4879. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4880. spin_lock_irqsave(&ha->smp_lock, flags);
  4881. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4882. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4883. cmd->Service = CACHESERVICE;
  4884. cmd->OpCode = GDT_CLUST_INFO;
  4885. if (ha->cache_feat & GDT_64BIT)
  4886. cmd->u.cache64.DeviceNo = i;
  4887. else
  4888. cmd->u.cache.DeviceNo = i;
  4889. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4890. spin_lock_irqsave(&ha->smp_lock, flags);
  4891. ha->hdr[i].cluster_type =
  4892. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4893. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4894. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4895. cmd->Service = CACHESERVICE;
  4896. cmd->OpCode = GDT_RW_ATTRIBS;
  4897. if (ha->cache_feat & GDT_64BIT)
  4898. cmd->u.cache64.DeviceNo = i;
  4899. else
  4900. cmd->u.cache.DeviceNo = i;
  4901. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4902. spin_lock_irqsave(&ha->smp_lock, flags);
  4903. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4904. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4905. }
  4906. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4907. rc = -EFAULT;
  4908. else
  4909. rc = 0;
  4910. free_fail:
  4911. kfree(rsc);
  4912. kfree(cmd);
  4913. return rc;
  4914. }
  4915. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4916. unsigned int cmd, unsigned long arg)
  4917. {
  4918. gdth_ha_str *ha;
  4919. Scsi_Cmnd *scp;
  4920. ulong flags;
  4921. char cmnd[MAX_COMMAND_SIZE];
  4922. void __user *argp = (void __user *)arg;
  4923. memset(cmnd, 0xff, 12);
  4924. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4925. switch (cmd) {
  4926. case GDTIOCTL_CTRCNT:
  4927. {
  4928. int cnt = gdth_ctr_count;
  4929. if (put_user(cnt, (int __user *)argp))
  4930. return -EFAULT;
  4931. break;
  4932. }
  4933. case GDTIOCTL_DRVERS:
  4934. {
  4935. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4936. if (put_user(ver, (int __user *)argp))
  4937. return -EFAULT;
  4938. break;
  4939. }
  4940. case GDTIOCTL_OSVERS:
  4941. {
  4942. gdth_ioctl_osvers osv;
  4943. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4944. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4945. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4946. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4947. return -EFAULT;
  4948. break;
  4949. }
  4950. case GDTIOCTL_CTRTYPE:
  4951. {
  4952. gdth_ioctl_ctrtype ctrt;
  4953. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4954. ctrt.ionode >= gdth_ctr_count)
  4955. return -EFAULT;
  4956. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4957. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4958. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4959. } else {
  4960. if (ha->type != GDT_PCIMPR) {
  4961. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4962. } else {
  4963. ctrt.type =
  4964. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4965. if (ha->stype >= 0x300)
  4966. ctrt.ext_type = 0x6000 | ha->subdevice_id;
  4967. else
  4968. ctrt.ext_type = 0x6000 | ha->stype;
  4969. }
  4970. ctrt.device_id = ha->stype;
  4971. ctrt.sub_device_id = ha->subdevice_id;
  4972. }
  4973. ctrt.info = ha->brd_phys;
  4974. ctrt.oem_id = ha->oem_id;
  4975. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4976. return -EFAULT;
  4977. break;
  4978. }
  4979. case GDTIOCTL_GENERAL:
  4980. return ioc_general(argp, cmnd);
  4981. case GDTIOCTL_EVENT:
  4982. return ioc_event(argp);
  4983. case GDTIOCTL_LOCKDRV:
  4984. return ioc_lockdrv(argp);
  4985. case GDTIOCTL_LOCKCHN:
  4986. {
  4987. gdth_ioctl_lockchn lchn;
  4988. unchar i, j;
  4989. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4990. lchn.ionode >= gdth_ctr_count)
  4991. return -EFAULT;
  4992. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  4993. i = lchn.channel;
  4994. if (i < ha->bus_cnt) {
  4995. if (lchn.lock) {
  4996. spin_lock_irqsave(&ha->smp_lock, flags);
  4997. ha->raw[i].lock = 1;
  4998. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4999. for (j = 0; j < ha->tid_cnt; ++j) {
  5000. gdth_wait_completion(lchn.ionode, i, j);
  5001. gdth_stop_timeout(lchn.ionode, i, j);
  5002. }
  5003. } else {
  5004. spin_lock_irqsave(&ha->smp_lock, flags);
  5005. ha->raw[i].lock = 0;
  5006. spin_unlock_irqrestore(&ha->smp_lock, flags);
  5007. for (j = 0; j < ha->tid_cnt; ++j) {
  5008. gdth_start_timeout(lchn.ionode, i, j);
  5009. gdth_next(lchn.ionode);
  5010. }
  5011. }
  5012. }
  5013. break;
  5014. }
  5015. case GDTIOCTL_RESCAN:
  5016. return ioc_rescan(argp, cmnd);
  5017. case GDTIOCTL_HDRLIST:
  5018. return ioc_hdrlist(argp, cmnd);
  5019. case GDTIOCTL_RESET_BUS:
  5020. {
  5021. gdth_ioctl_reset res;
  5022. int hanum, rval;
  5023. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  5024. res.ionode >= gdth_ctr_count)
  5025. return -EFAULT;
  5026. hanum = res.ionode;
  5027. ha = HADATA(gdth_ctr_tab[hanum]);
  5028. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5029. scp = kmalloc(sizeof(*scp), GFP_KERNEL);
  5030. if (!scp)
  5031. return -ENOMEM;
  5032. memset(scp, 0, sizeof(*scp));
  5033. scp->device = ha->sdev;
  5034. scp->cmd_len = 12;
  5035. scp->use_sg = 0;
  5036. scp->device->channel = virt_ctr ? 0 : res.number;
  5037. rval = gdth_eh_bus_reset(scp);
  5038. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5039. kfree(scp);
  5040. #else
  5041. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  5042. if (!scp)
  5043. return -ENOMEM;
  5044. scp->cmd_len = 12;
  5045. scp->use_sg = 0;
  5046. scp->channel = virt_ctr ? 0 : res.number;
  5047. rval = gdth_eh_bus_reset(scp);
  5048. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  5049. scsi_release_command(scp);
  5050. #endif
  5051. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  5052. return -EFAULT;
  5053. break;
  5054. }
  5055. case GDTIOCTL_RESET_DRV:
  5056. return ioc_resetdrv(argp, cmnd);
  5057. default:
  5058. break;
  5059. }
  5060. return 0;
  5061. }
  5062. /* flush routine */
  5063. static void gdth_flush(int hanum)
  5064. {
  5065. int i;
  5066. gdth_ha_str *ha;
  5067. gdth_cmd_str gdtcmd;
  5068. char cmnd[MAX_COMMAND_SIZE];
  5069. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5070. TRACE2(("gdth_flush() hanum %d\n",hanum));
  5071. ha = HADATA(gdth_ctr_tab[hanum]);
  5072. for (i = 0; i < MAX_HDRIVES; ++i) {
  5073. if (ha->hdr[i].present) {
  5074. gdtcmd.BoardNode = LOCALBOARD;
  5075. gdtcmd.Service = CACHESERVICE;
  5076. gdtcmd.OpCode = GDT_FLUSH;
  5077. if (ha->cache_feat & GDT_64BIT) {
  5078. gdtcmd.u.cache64.DeviceNo = i;
  5079. gdtcmd.u.cache64.BlockNo = 1;
  5080. gdtcmd.u.cache64.sg_canz = 0;
  5081. } else {
  5082. gdtcmd.u.cache.DeviceNo = i;
  5083. gdtcmd.u.cache.BlockNo = 1;
  5084. gdtcmd.u.cache.sg_canz = 0;
  5085. }
  5086. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  5087. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
  5088. }
  5089. }
  5090. }
  5091. /* shutdown routine */
  5092. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  5093. {
  5094. int hanum;
  5095. #ifndef __alpha__
  5096. gdth_cmd_str gdtcmd;
  5097. char cmnd[MAX_COMMAND_SIZE];
  5098. #endif
  5099. if (notifier_disabled)
  5100. return NOTIFY_OK;
  5101. TRACE2(("gdth_halt() event %d\n",(int)event));
  5102. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  5103. return NOTIFY_DONE;
  5104. notifier_disabled = 1;
  5105. printk("GDT-HA: Flushing all host drives .. ");
  5106. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  5107. gdth_flush(hanum);
  5108. #ifndef __alpha__
  5109. /* controller reset */
  5110. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  5111. gdtcmd.BoardNode = LOCALBOARD;
  5112. gdtcmd.Service = CACHESERVICE;
  5113. gdtcmd.OpCode = GDT_RESET;
  5114. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  5115. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
  5116. #endif
  5117. }
  5118. printk("Done.\n");
  5119. #ifdef GDTH_STATISTICS
  5120. del_timer(&gdth_timer);
  5121. #endif
  5122. return NOTIFY_OK;
  5123. }
  5124. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5125. /* configure lun */
  5126. static int gdth_slave_configure(struct scsi_device *sdev)
  5127. {
  5128. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  5129. sdev->skip_ms_page_3f = 1;
  5130. sdev->skip_ms_page_8 = 1;
  5131. return 0;
  5132. }
  5133. #endif
  5134. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5135. static struct scsi_host_template driver_template = {
  5136. #else
  5137. static Scsi_Host_Template driver_template = {
  5138. #endif
  5139. .proc_name = "gdth",
  5140. .proc_info = gdth_proc_info,
  5141. .name = "GDT SCSI Disk Array Controller",
  5142. .detect = gdth_detect,
  5143. .release = gdth_release,
  5144. .info = gdth_info,
  5145. .queuecommand = gdth_queuecommand,
  5146. .eh_bus_reset_handler = gdth_eh_bus_reset,
  5147. .bios_param = gdth_bios_param,
  5148. .can_queue = GDTH_MAXCMDS,
  5149. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  5150. .slave_configure = gdth_slave_configure,
  5151. #endif
  5152. .this_id = -1,
  5153. .sg_tablesize = GDTH_MAXSG,
  5154. .cmd_per_lun = GDTH_MAXC_P_L,
  5155. .unchecked_isa_dma = 1,
  5156. .use_clustering = ENABLE_CLUSTERING,
  5157. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  5158. .use_new_eh_code = 1,
  5159. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  5160. .highmem_io = 1,
  5161. #endif
  5162. #endif
  5163. };
  5164. #include "scsi_module.c"
  5165. #ifndef MODULE
  5166. __setup("gdth=", option_setup);
  5167. #endif