aic94xx_hwi.h 11 KB

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  1. /*
  2. * Aic94xx SAS/SATA driver hardware interface header file.
  3. *
  4. * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
  5. * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
  6. *
  7. * This file is licensed under GPLv2.
  8. *
  9. * This file is part of the aic94xx driver.
  10. *
  11. * The aic94xx driver is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; version 2 of the
  14. * License.
  15. *
  16. * The aic94xx driver is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with the aic94xx driver; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  24. *
  25. */
  26. #ifndef _AIC94XX_HWI_H_
  27. #define _AIC94XX_HWI_H_
  28. #include <linux/interrupt.h>
  29. #include <linux/pci.h>
  30. #include <linux/dma-mapping.h>
  31. #include <scsi/libsas.h>
  32. #include "aic94xx.h"
  33. #include "aic94xx_sas.h"
  34. /* Define ASD_MAX_PHYS to the maximum phys ever. Currently 8. */
  35. #define ASD_MAX_PHYS 8
  36. #define ASD_PCBA_SN_SIZE 12
  37. /* Those are to be further named properly, the "RAZORx" part, and
  38. * subsequently included in include/linux/pci_ids.h.
  39. */
  40. #define PCI_DEVICE_ID_ADAPTEC2_RAZOR10 0x410
  41. #define PCI_DEVICE_ID_ADAPTEC2_RAZOR12 0x412
  42. #define PCI_DEVICE_ID_ADAPTEC2_RAZOR1E 0x41E
  43. #define PCI_DEVICE_ID_ADAPTEC2_RAZOR30 0x430
  44. #define PCI_DEVICE_ID_ADAPTEC2_RAZOR32 0x432
  45. #define PCI_DEVICE_ID_ADAPTEC2_RAZOR3E 0x43E
  46. #define PCI_DEVICE_ID_ADAPTEC2_RAZOR3F 0x43F
  47. struct asd_ha_addrspace {
  48. void __iomem *addr;
  49. unsigned long start; /* pci resource start */
  50. unsigned long len; /* pci resource len */
  51. unsigned long flags; /* pci resource flags */
  52. /* addresses internal to the host adapter */
  53. u32 swa_base; /* mmspace 1 (MBAR1) uses this only */
  54. u32 swb_base;
  55. u32 swc_base;
  56. };
  57. struct bios_struct {
  58. int present;
  59. u8 maj;
  60. u8 min;
  61. u32 bld;
  62. };
  63. struct unit_element_struct {
  64. u16 num;
  65. u16 size;
  66. void *area;
  67. };
  68. struct flash_struct {
  69. u32 bar;
  70. int present;
  71. int wide;
  72. u8 manuf;
  73. u8 dev_id;
  74. u8 sec_prot;
  75. u32 dir_offs;
  76. };
  77. struct asd_phy_desc {
  78. /* From CTRL-A settings, then set to what is appropriate */
  79. u8 sas_addr[SAS_ADDR_SIZE];
  80. u8 max_sas_lrate;
  81. u8 min_sas_lrate;
  82. u8 max_sata_lrate;
  83. u8 min_sata_lrate;
  84. u8 flags;
  85. #define ASD_CRC_DIS 1
  86. #define ASD_SATA_SPINUP_HOLD 2
  87. u8 phy_control_0; /* mode 5 reg 0x160 */
  88. u8 phy_control_1; /* mode 5 reg 0x161 */
  89. u8 phy_control_2; /* mode 5 reg 0x162 */
  90. u8 phy_control_3; /* mode 5 reg 0x163 */
  91. };
  92. struct asd_dma_tok {
  93. void *vaddr;
  94. dma_addr_t dma_handle;
  95. size_t size;
  96. };
  97. struct hw_profile {
  98. struct bios_struct bios;
  99. struct unit_element_struct ue;
  100. struct flash_struct flash;
  101. u8 sas_addr[SAS_ADDR_SIZE];
  102. char pcba_sn[ASD_PCBA_SN_SIZE+1];
  103. u8 enabled_phys; /* mask of enabled phys */
  104. struct asd_phy_desc phy_desc[ASD_MAX_PHYS];
  105. u32 max_scbs; /* absolute sequencer scb queue size */
  106. struct asd_dma_tok *scb_ext;
  107. u32 max_ddbs;
  108. struct asd_dma_tok *ddb_ext;
  109. spinlock_t ddb_lock;
  110. void *ddb_bitmap;
  111. int num_phys; /* ENABLEABLE */
  112. int max_phys; /* REPORTED + ENABLEABLE */
  113. unsigned addr_range; /* max # of addrs; max # of possible ports */
  114. unsigned port_name_base;
  115. unsigned dev_name_base;
  116. unsigned sata_name_base;
  117. };
  118. struct asd_ascb {
  119. struct list_head list;
  120. struct asd_ha_struct *ha;
  121. struct scb *scb; /* equals dma_scb->vaddr */
  122. struct asd_dma_tok dma_scb;
  123. struct asd_dma_tok *sg_arr;
  124. void (*tasklet_complete)(struct asd_ascb *, struct done_list_struct *);
  125. u8 uldd_timer:1;
  126. /* internally generated command */
  127. struct timer_list timer;
  128. struct completion completion;
  129. u8 tag_valid:1;
  130. __be16 tag; /* error recovery only */
  131. /* If this is an Empty SCB, index of first edb in seq->edb_arr. */
  132. int edb_index;
  133. /* Used by the timer timeout function. */
  134. int tc_index;
  135. void *uldd_task;
  136. };
  137. #define ASD_DL_SIZE_BITS 0x8
  138. #define ASD_DL_SIZE (1<<(2+ASD_DL_SIZE_BITS))
  139. #define ASD_DEF_DL_TOGGLE 0x01
  140. struct asd_seq_data {
  141. spinlock_t pend_q_lock;
  142. u16 scbpro;
  143. int pending;
  144. struct list_head pend_q;
  145. int can_queue; /* per adapter */
  146. struct asd_dma_tok next_scb; /* next scb to be delivered to CSEQ */
  147. spinlock_t tc_index_lock;
  148. void **tc_index_array;
  149. void *tc_index_bitmap;
  150. int tc_index_bitmap_bits;
  151. struct tasklet_struct dl_tasklet;
  152. struct done_list_struct *dl; /* array of done list entries, equals */
  153. struct asd_dma_tok *actual_dl; /* actual_dl->vaddr */
  154. int dl_toggle;
  155. int dl_next;
  156. int num_edbs;
  157. struct asd_dma_tok **edb_arr;
  158. int num_escbs;
  159. struct asd_ascb **escb_arr; /* array of pointers to escbs */
  160. };
  161. /* This is the Host Adapter structure. It describes the hardware
  162. * SAS adapter.
  163. */
  164. struct asd_ha_struct {
  165. struct pci_dev *pcidev;
  166. const char *name;
  167. struct sas_ha_struct sas_ha;
  168. u8 revision_id;
  169. int iospace;
  170. spinlock_t iolock;
  171. struct asd_ha_addrspace io_handle[2];
  172. struct hw_profile hw_prof;
  173. struct asd_phy phys[ASD_MAX_PHYS];
  174. struct asd_sas_port ports[ASD_MAX_PHYS];
  175. struct dma_pool *scb_pool;
  176. struct asd_seq_data seq; /* sequencer related */
  177. };
  178. /* ---------- Common macros ---------- */
  179. #define ASD_BUSADDR_LO(__dma_handle) ((u32)(__dma_handle))
  180. #define ASD_BUSADDR_HI(__dma_handle) (((sizeof(dma_addr_t))==8) \
  181. ? ((u32)((__dma_handle) >> 32)) \
  182. : ((u32)0))
  183. #define dev_to_asd_ha(__dev) pci_get_drvdata(to_pci_dev(__dev))
  184. #define SCB_SITE_VALID(__site_no) (((__site_no) & 0xF0FF) != 0x00FF \
  185. && ((__site_no) & 0xF0FF) > 0x001F)
  186. /* For each bit set in __lseq_mask, set __lseq to equal the bit
  187. * position of the set bit and execute the statement following.
  188. * __mc is the temporary mask, used as a mask "counter".
  189. */
  190. #define for_each_sequencer(__lseq_mask, __mc, __lseq) \
  191. for ((__mc)=(__lseq_mask),(__lseq)=0;(__mc)!=0;(__lseq++),(__mc)>>=1)\
  192. if (((__mc) & 1))
  193. #define for_each_phy(__lseq_mask, __mc, __lseq) \
  194. for ((__mc)=(__lseq_mask),(__lseq)=0;(__mc)!=0;(__lseq++),(__mc)>>=1)\
  195. if (((__mc) & 1))
  196. #define PHY_ENABLED(_HA, _I) ((_HA)->hw_prof.enabled_phys & (1<<(_I)))
  197. /* ---------- DMA allocs ---------- */
  198. static inline struct asd_dma_tok *asd_dmatok_alloc(gfp_t flags)
  199. {
  200. return kmem_cache_alloc(asd_dma_token_cache, flags);
  201. }
  202. static inline void asd_dmatok_free(struct asd_dma_tok *token)
  203. {
  204. kmem_cache_free(asd_dma_token_cache, token);
  205. }
  206. static inline struct asd_dma_tok *asd_alloc_coherent(struct asd_ha_struct *
  207. asd_ha, size_t size,
  208. gfp_t flags)
  209. {
  210. struct asd_dma_tok *token = asd_dmatok_alloc(flags);
  211. if (token) {
  212. token->size = size;
  213. token->vaddr = dma_alloc_coherent(&asd_ha->pcidev->dev,
  214. token->size,
  215. &token->dma_handle,
  216. flags);
  217. if (!token->vaddr) {
  218. asd_dmatok_free(token);
  219. token = NULL;
  220. }
  221. }
  222. return token;
  223. }
  224. static inline void asd_free_coherent(struct asd_ha_struct *asd_ha,
  225. struct asd_dma_tok *token)
  226. {
  227. if (token) {
  228. dma_free_coherent(&asd_ha->pcidev->dev, token->size,
  229. token->vaddr, token->dma_handle);
  230. asd_dmatok_free(token);
  231. }
  232. }
  233. static inline void asd_init_ascb(struct asd_ha_struct *asd_ha,
  234. struct asd_ascb *ascb)
  235. {
  236. INIT_LIST_HEAD(&ascb->list);
  237. ascb->scb = ascb->dma_scb.vaddr;
  238. ascb->ha = asd_ha;
  239. ascb->timer.function = NULL;
  240. init_timer(&ascb->timer);
  241. ascb->tc_index = -1;
  242. init_completion(&ascb->completion);
  243. }
  244. /* Must be called with the tc_index_lock held!
  245. */
  246. static inline void asd_tc_index_release(struct asd_seq_data *seq, int index)
  247. {
  248. seq->tc_index_array[index] = NULL;
  249. clear_bit(index, seq->tc_index_bitmap);
  250. }
  251. /* Must be called with the tc_index_lock held!
  252. */
  253. static inline int asd_tc_index_get(struct asd_seq_data *seq, void *ptr)
  254. {
  255. int index;
  256. index = find_first_zero_bit(seq->tc_index_bitmap,
  257. seq->tc_index_bitmap_bits);
  258. if (index == seq->tc_index_bitmap_bits)
  259. return -1;
  260. seq->tc_index_array[index] = ptr;
  261. set_bit(index, seq->tc_index_bitmap);
  262. return index;
  263. }
  264. /* Must be called with the tc_index_lock held!
  265. */
  266. static inline void *asd_tc_index_find(struct asd_seq_data *seq, int index)
  267. {
  268. return seq->tc_index_array[index];
  269. }
  270. /**
  271. * asd_ascb_free -- free a single aSCB after is has completed
  272. * @ascb: pointer to the aSCB of interest
  273. *
  274. * This frees an aSCB after it has been executed/completed by
  275. * the sequencer.
  276. */
  277. static inline void asd_ascb_free(struct asd_ascb *ascb)
  278. {
  279. if (ascb) {
  280. struct asd_ha_struct *asd_ha = ascb->ha;
  281. unsigned long flags;
  282. BUG_ON(!list_empty(&ascb->list));
  283. spin_lock_irqsave(&ascb->ha->seq.tc_index_lock, flags);
  284. asd_tc_index_release(&ascb->ha->seq, ascb->tc_index);
  285. spin_unlock_irqrestore(&ascb->ha->seq.tc_index_lock, flags);
  286. dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr,
  287. ascb->dma_scb.dma_handle);
  288. kmem_cache_free(asd_ascb_cache, ascb);
  289. }
  290. }
  291. /**
  292. * asd_ascb_list_free -- free a list of ascbs
  293. * @ascb_list: a list of ascbs
  294. *
  295. * This function will free a list of ascbs allocated by asd_ascb_alloc_list.
  296. * It is used when say the scb queueing function returned QUEUE_FULL,
  297. * and we do not need the ascbs any more.
  298. */
  299. static inline void asd_ascb_free_list(struct asd_ascb *ascb_list)
  300. {
  301. LIST_HEAD(list);
  302. struct list_head *n, *pos;
  303. __list_add(&list, ascb_list->list.prev, &ascb_list->list);
  304. list_for_each_safe(pos, n, &list) {
  305. list_del_init(pos);
  306. asd_ascb_free(list_entry(pos, struct asd_ascb, list));
  307. }
  308. }
  309. /* ---------- Function declarations ---------- */
  310. int asd_init_hw(struct asd_ha_struct *asd_ha);
  311. irqreturn_t asd_hw_isr(int irq, void *dev_id);
  312. struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct
  313. *asd_ha, int *num,
  314. gfp_t gfp_mask);
  315. int asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
  316. int num);
  317. int asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
  318. int num);
  319. int asd_init_post_escbs(struct asd_ha_struct *asd_ha);
  320. void asd_build_control_phy(struct asd_ascb *ascb, int phy_id, u8 subfunc);
  321. void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op);
  322. void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op);
  323. int asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask);
  324. void asd_build_initiate_link_adm_task(struct asd_ascb *ascb, int phy_id,
  325. u8 subfunc);
  326. void asd_ascb_timedout(unsigned long data);
  327. int asd_chip_hardrst(struct asd_ha_struct *asd_ha);
  328. #endif