aerdrv.h 3.1 KB

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  1. /*
  2. * Copyright (C) 2006 Intel Corp.
  3. * Tom Long Nguyen (tom.l.nguyen@intel.com)
  4. * Zhang Yanmin (yanmin.zhang@intel.com)
  5. *
  6. */
  7. #ifndef _AERDRV_H_
  8. #define _AERDRV_H_
  9. #include <linux/pcieport_if.h>
  10. #include <linux/aer.h>
  11. #define AER_NONFATAL 0
  12. #define AER_FATAL 1
  13. #define AER_CORRECTABLE 2
  14. #define AER_UNCORRECTABLE 4
  15. #define AER_ERROR_MASK 0x001fffff
  16. #define AER_ERROR(d) (d & AER_ERROR_MASK)
  17. #define OSC_METHOD_RUN_SUCCESS 0
  18. #define OSC_METHOD_NOT_SUPPORTED 1
  19. #define OSC_METHOD_RUN_FAILURE 2
  20. /* Root Error Status Register Bits */
  21. #define ROOT_ERR_STATUS_MASKS 0x0f
  22. #define SYSTEM_ERROR_INTR_ON_MESG_MASK (PCI_EXP_RTCTL_SECEE| \
  23. PCI_EXP_RTCTL_SENFEE| \
  24. PCI_EXP_RTCTL_SEFEE)
  25. #define ROOT_PORT_INTR_ON_MESG_MASK (PCI_ERR_ROOT_CMD_COR_EN| \
  26. PCI_ERR_ROOT_CMD_NONFATAL_EN| \
  27. PCI_ERR_ROOT_CMD_FATAL_EN)
  28. #define ERR_COR_ID(d) (d & 0xffff)
  29. #define ERR_UNCOR_ID(d) (d >> 16)
  30. #define AER_SUCCESS 0
  31. #define AER_UNSUCCESS 1
  32. #define AER_ERROR_SOURCES_MAX 100
  33. #define AER_LOG_TLP_MASKS (PCI_ERR_UNC_POISON_TLP| \
  34. PCI_ERR_UNC_ECRC| \
  35. PCI_ERR_UNC_UNSUP| \
  36. PCI_ERR_UNC_COMP_ABORT| \
  37. PCI_ERR_UNC_UNX_COMP| \
  38. PCI_ERR_UNC_MALF_TLP)
  39. /* AER Error Info Flags */
  40. #define AER_TLP_HEADER_VALID_FLAG 0x00000001
  41. #define AER_MULTI_ERROR_VALID_FLAG 0x00000002
  42. #define ERR_CORRECTABLE_ERROR_MASK 0x000031c1
  43. #define ERR_UNCORRECTABLE_ERROR_MASK 0x001ff010
  44. struct header_log_regs {
  45. unsigned int dw0;
  46. unsigned int dw1;
  47. unsigned int dw2;
  48. unsigned int dw3;
  49. };
  50. struct aer_err_info {
  51. int severity; /* 0:NONFATAL | 1:FATAL | 2:COR */
  52. int flags;
  53. unsigned int status; /* COR/UNCOR Error Status */
  54. struct header_log_regs tlp; /* TLP Header */
  55. };
  56. struct aer_err_source {
  57. unsigned int status;
  58. unsigned int id;
  59. };
  60. struct aer_rpc {
  61. struct pcie_device *rpd; /* Root Port device */
  62. struct work_struct dpc_handler;
  63. struct aer_err_source e_sources[AER_ERROR_SOURCES_MAX];
  64. unsigned short prod_idx; /* Error Producer Index */
  65. unsigned short cons_idx; /* Error Consumer Index */
  66. int isr;
  67. spinlock_t e_lock; /*
  68. * Lock access to Error Status/ID Regs
  69. * and error producer/consumer index
  70. */
  71. struct mutex rpc_mutex; /*
  72. * only one thread could do
  73. * recovery on the same
  74. * root port hierachy
  75. */
  76. wait_queue_head_t wait_release;
  77. };
  78. struct aer_broadcast_data {
  79. enum pci_channel_state state;
  80. enum pci_ers_result result;
  81. };
  82. static inline pci_ers_result_t merge_result(enum pci_ers_result orig,
  83. enum pci_ers_result new)
  84. {
  85. switch (orig) {
  86. case PCI_ERS_RESULT_CAN_RECOVER:
  87. case PCI_ERS_RESULT_RECOVERED:
  88. orig = new;
  89. break;
  90. case PCI_ERS_RESULT_DISCONNECT:
  91. if (new == PCI_ERS_RESULT_NEED_RESET)
  92. orig = new;
  93. break;
  94. default:
  95. break;
  96. }
  97. return orig;
  98. }
  99. extern struct bus_type pcie_port_bus_type;
  100. extern void aer_enable_rootport(struct aer_rpc *rpc);
  101. extern void aer_delete_rootport(struct aer_rpc *rpc);
  102. extern int aer_init(struct pcie_device *dev);
  103. extern void aer_isr(void *context);
  104. extern void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
  105. extern int aer_osc_setup(struct pci_dev *dev);
  106. #endif //_AERDRV_H_