zd_rf_rf2959.c 8.3 KB

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  1. /* zd_rf_rfmd.c: Functions for the RFMD RF controller
  2. *
  3. * This program is free software; you can redistribute it and/or modify
  4. * it under the terms of the GNU General Public License as published by
  5. * the Free Software Foundation; either version 2 of the License, or
  6. * (at your option) any later version.
  7. *
  8. * This program is distributed in the hope that it will be useful,
  9. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program; if not, write to the Free Software
  15. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  16. */
  17. #include <linux/kernel.h>
  18. #include "zd_rf.h"
  19. #include "zd_usb.h"
  20. #include "zd_chip.h"
  21. static u32 rf2959_table[][2] = {
  22. RF_CHANNEL( 1) = { 0x181979, 0x1e6666 },
  23. RF_CHANNEL( 2) = { 0x181989, 0x1e6666 },
  24. RF_CHANNEL( 3) = { 0x181999, 0x1e6666 },
  25. RF_CHANNEL( 4) = { 0x1819a9, 0x1e6666 },
  26. RF_CHANNEL( 5) = { 0x1819b9, 0x1e6666 },
  27. RF_CHANNEL( 6) = { 0x1819c9, 0x1e6666 },
  28. RF_CHANNEL( 7) = { 0x1819d9, 0x1e6666 },
  29. RF_CHANNEL( 8) = { 0x1819e9, 0x1e6666 },
  30. RF_CHANNEL( 9) = { 0x1819f9, 0x1e6666 },
  31. RF_CHANNEL(10) = { 0x181a09, 0x1e6666 },
  32. RF_CHANNEL(11) = { 0x181a19, 0x1e6666 },
  33. RF_CHANNEL(12) = { 0x181a29, 0x1e6666 },
  34. RF_CHANNEL(13) = { 0x181a39, 0x1e6666 },
  35. RF_CHANNEL(14) = { 0x181a60, 0x1c0000 },
  36. };
  37. #if 0
  38. static int bits(u32 rw, int from, int to)
  39. {
  40. rw &= ~(0xffffffffU << (to+1));
  41. rw >>= from;
  42. return rw;
  43. }
  44. static int bit(u32 rw, int bit)
  45. {
  46. return bits(rw, bit, bit);
  47. }
  48. static void dump_regwrite(u32 rw)
  49. {
  50. int reg = bits(rw, 18, 22);
  51. int rw_flag = bits(rw, 23, 23);
  52. PDEBUG("rf2959 %#010x reg %d rw %d", rw, reg, rw_flag);
  53. switch (reg) {
  54. case 0:
  55. PDEBUG("reg0 CFG1 ref_sel %d hybernate %d rf_vco_reg_en %d"
  56. " if_vco_reg_en %d if_vga_en %d",
  57. bits(rw, 14, 15), bit(rw, 3), bit(rw, 2), bit(rw, 1),
  58. bit(rw, 0));
  59. break;
  60. case 1:
  61. PDEBUG("reg1 IFPLL1 pll_en1 %d kv_en1 %d vtc_en1 %d lpf1 %d"
  62. " cpl1 %d pdp1 %d autocal_en1 %d ld_en1 %d ifloopr %d"
  63. " ifloopc %d dac1 %d",
  64. bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
  65. bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
  66. bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0, 3));
  67. break;
  68. case 2:
  69. PDEBUG("reg2 IFPLL2 n1 %d num1 %d",
  70. bits(rw, 6, 17), bits(rw, 0, 5));
  71. break;
  72. case 3:
  73. PDEBUG("reg3 IFPLL3 num %d", bits(rw, 0, 17));
  74. break;
  75. case 4:
  76. PDEBUG("reg4 IFPLL4 dn1 %#04x ct_def1 %d kv_def1 %d",
  77. bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
  78. break;
  79. case 5:
  80. PDEBUG("reg5 RFPLL1 pll_en %d kv_en %d vtc_en %d lpf %d cpl %d"
  81. " pdp %d autocal_en %d ld_en %d rfloopr %d rfloopc %d"
  82. " dac %d",
  83. bit(rw, 17), bit(rw, 16), bit(rw, 15), bit(rw, 14),
  84. bit(rw, 13), bit(rw, 12), bit(rw, 11), bit(rw, 10),
  85. bits(rw, 7, 9), bits(rw, 4, 6), bits(rw, 0,3));
  86. break;
  87. case 6:
  88. PDEBUG("reg6 RFPLL2 n %d num %d",
  89. bits(rw, 6, 17), bits(rw, 0, 5));
  90. break;
  91. case 7:
  92. PDEBUG("reg7 RFPLL3 num2 %d", bits(rw, 0, 17));
  93. break;
  94. case 8:
  95. PDEBUG("reg8 RFPLL4 dn %#06x ct_def %d kv_def %d",
  96. bits(rw, 8, 16), bits(rw, 4, 7), bits(rw, 0, 3));
  97. break;
  98. case 9:
  99. PDEBUG("reg9 CAL1 tvco %d tlock %d m_ct_value %d ld_window %d",
  100. bits(rw, 13, 17), bits(rw, 8, 12), bits(rw, 3, 7),
  101. bits(rw, 0, 2));
  102. break;
  103. case 10:
  104. PDEBUG("reg10 TXRX1 rxdcfbbyps %d pcontrol %d txvgc %d"
  105. " rxlpfbw %d txlpfbw %d txdiffmode %d txenmode %d"
  106. " intbiasen %d tybypass %d",
  107. bit(rw, 17), bits(rw, 15, 16), bits(rw, 10, 14),
  108. bits(rw, 7, 9), bits(rw, 4, 6), bit(rw, 3), bit(rw, 2),
  109. bit(rw, 1), bit(rw, 0));
  110. break;
  111. case 11:
  112. PDEBUG("reg11 PCNT1 mid_bias %d p_desired %d pc_offset %d"
  113. " tx_delay %d",
  114. bits(rw, 15, 17), bits(rw, 9, 14), bits(rw, 3, 8),
  115. bits(rw, 0, 2));
  116. break;
  117. case 12:
  118. PDEBUG("reg12 PCNT2 max_power %d mid_power %d min_power %d",
  119. bits(rw, 12, 17), bits(rw, 6, 11), bits(rw, 0, 5));
  120. break;
  121. case 13:
  122. PDEBUG("reg13 VCOT1 rfpll vco comp %d ifpll vco comp %d"
  123. " lobias %d if_biasbuf %d if_biasvco %d rf_biasbuf %d"
  124. " rf_biasvco %d",
  125. bit(rw, 17), bit(rw, 16), bit(rw, 15),
  126. bits(rw, 8, 9), bits(rw, 5, 7), bits(rw, 3, 4),
  127. bits(rw, 0, 2));
  128. break;
  129. case 14:
  130. PDEBUG("reg14 IQCAL rx_acal %d rx_pcal %d"
  131. " tx_acal %d tx_pcal %d",
  132. bits(rw, 13, 17), bits(rw, 9, 12), bits(rw, 4, 8),
  133. bits(rw, 0, 3));
  134. break;
  135. }
  136. }
  137. #endif /* 0 */
  138. static int rf2959_init_hw(struct zd_rf *rf)
  139. {
  140. int r;
  141. struct zd_chip *chip = zd_rf_to_chip(rf);
  142. static const struct zd_ioreq16 ioreqs[] = {
  143. { CR2, 0x1E }, { CR9, 0x20 }, { CR10, 0x89 },
  144. { CR11, 0x00 }, { CR15, 0xD0 }, { CR17, 0x68 },
  145. { CR19, 0x4a }, { CR20, 0x0c }, { CR21, 0x0E },
  146. { CR23, 0x48 },
  147. /* normal size for cca threshold */
  148. { CR24, 0x14 },
  149. /* { CR24, 0x20 }, */
  150. { CR26, 0x90 }, { CR27, 0x30 }, { CR29, 0x20 },
  151. { CR31, 0xb2 }, { CR32, 0x43 }, { CR33, 0x28 },
  152. { CR38, 0x30 }, { CR34, 0x0f }, { CR35, 0xF0 },
  153. { CR41, 0x2a }, { CR46, 0x7F }, { CR47, 0x1E },
  154. { CR51, 0xc5 }, { CR52, 0xc5 }, { CR53, 0xc5 },
  155. { CR79, 0x58 }, { CR80, 0x30 }, { CR81, 0x30 },
  156. { CR82, 0x00 }, { CR83, 0x24 }, { CR84, 0x04 },
  157. { CR85, 0x00 }, { CR86, 0x10 }, { CR87, 0x2A },
  158. { CR88, 0x10 }, { CR89, 0x24 }, { CR90, 0x18 },
  159. /* { CR91, 0x18 }, */
  160. /* should solve continous CTS frame problems */
  161. { CR91, 0x00 },
  162. { CR92, 0x0a }, { CR93, 0x00 }, { CR94, 0x01 },
  163. { CR95, 0x00 }, { CR96, 0x40 }, { CR97, 0x37 },
  164. { CR98, 0x05 }, { CR99, 0x28 }, { CR100, 0x00 },
  165. { CR101, 0x13 }, { CR102, 0x27 }, { CR103, 0x27 },
  166. { CR104, 0x18 }, { CR105, 0x12 },
  167. /* normal size */
  168. { CR106, 0x1a },
  169. /* { CR106, 0x22 }, */
  170. { CR107, 0x24 }, { CR108, 0x0a }, { CR109, 0x13 },
  171. { CR110, 0x2F }, { CR111, 0x27 }, { CR112, 0x27 },
  172. { CR113, 0x27 }, { CR114, 0x27 }, { CR115, 0x40 },
  173. { CR116, 0x40 }, { CR117, 0xF0 }, { CR118, 0xF0 },
  174. { CR119, 0x16 },
  175. /* no TX continuation */
  176. { CR122, 0x00 },
  177. /* { CR122, 0xff }, */
  178. { CR127, 0x03 }, { CR131, 0x08 }, { CR138, 0x28 },
  179. { CR148, 0x44 }, { CR150, 0x10 }, { CR169, 0xBB },
  180. { CR170, 0xBB },
  181. };
  182. static const u32 rv[] = {
  183. 0x000007, /* REG0(CFG1) */
  184. 0x07dd43, /* REG1(IFPLL1) */
  185. 0x080959, /* REG2(IFPLL2) */
  186. 0x0e6666,
  187. 0x116a57, /* REG4 */
  188. 0x17dd43, /* REG5 */
  189. 0x1819f9, /* REG6 */
  190. 0x1e6666,
  191. 0x214554,
  192. 0x25e7fa,
  193. 0x27fffa,
  194. /* The Zydas driver somehow forgets to set this value. It's
  195. * only set for Japan. We are using internal power control
  196. * for now.
  197. */
  198. 0x294128, /* internal power */
  199. /* 0x28252c, */ /* External control TX power */
  200. /* CR31_CCK, CR51_6-36M, CR52_48M, CR53_54M */
  201. 0x2c0000,
  202. 0x300000,
  203. 0x340000, /* REG13(0xD) */
  204. 0x381e0f, /* REG14(0xE) */
  205. /* Bogus, RF2959's data sheet doesn't know register 27, which is
  206. * actually referenced here. The commented 0x11 is 17.
  207. */
  208. 0x6c180f, /* REG27(0x11) */
  209. };
  210. r = zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  211. if (r)
  212. return r;
  213. return zd_rfwritev_locked(chip, rv, ARRAY_SIZE(rv), RF_RV_BITS);
  214. }
  215. static int rf2959_set_channel(struct zd_rf *rf, u8 channel)
  216. {
  217. int i, r;
  218. u32 *rv = rf2959_table[channel-1];
  219. struct zd_chip *chip = zd_rf_to_chip(rf);
  220. for (i = 0; i < 2; i++) {
  221. r = zd_rfwrite_locked(chip, rv[i], RF_RV_BITS);
  222. if (r)
  223. return r;
  224. }
  225. return 0;
  226. }
  227. static int rf2959_switch_radio_on(struct zd_rf *rf)
  228. {
  229. static const struct zd_ioreq16 ioreqs[] = {
  230. { CR10, 0x89 },
  231. { CR11, 0x00 },
  232. };
  233. struct zd_chip *chip = zd_rf_to_chip(rf);
  234. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  235. }
  236. static int rf2959_switch_radio_off(struct zd_rf *rf)
  237. {
  238. static const struct zd_ioreq16 ioreqs[] = {
  239. { CR10, 0x15 },
  240. { CR11, 0x81 },
  241. };
  242. struct zd_chip *chip = zd_rf_to_chip(rf);
  243. return zd_iowrite16a_locked(chip, ioreqs, ARRAY_SIZE(ioreqs));
  244. }
  245. int zd_rf_init_rf2959(struct zd_rf *rf)
  246. {
  247. struct zd_chip *chip = zd_rf_to_chip(rf);
  248. if (chip->is_zd1211b) {
  249. dev_err(zd_chip_dev(chip),
  250. "RF2959 is currently not supported for ZD1211B"
  251. " devices\n");
  252. return -ENODEV;
  253. }
  254. rf->init_hw = rf2959_init_hw;
  255. rf->set_channel = rf2959_set_channel;
  256. rf->switch_radio_on = rf2959_switch_radio_on;
  257. rf->switch_radio_off = rf2959_switch_radio_off;
  258. return 0;
  259. }