via-ircc.c 42 KB

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  1. /********************************************************************
  2. Filename: via-ircc.c
  3. Version: 1.0
  4. Description: Driver for the VIA VT8231/VT8233 IrDA chipsets
  5. Author: VIA Technologies,inc
  6. Date : 08/06/2003
  7. Copyright (c) 1998-2003 VIA Technologies, Inc.
  8. This program is free software; you can redistribute it and/or modify it under
  9. the terms of the GNU General Public License as published by the Free Software
  10. Foundation; either version 2, or (at your option) any later version.
  11. This program is distributed in the hope that it will be useful, but WITHOUT
  12. ANY WARRANTIES OR REPRESENTATIONS; without even the implied warranty of
  13. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  14. See the GNU General Public License for more details.
  15. You should have received a copy of the GNU General Public License along with
  16. this program; if not, write to the Free Software Foundation, Inc.,
  17. 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  18. F01 Oct/02/02: Modify code for V0.11(move out back to back transfer)
  19. F02 Oct/28/02: Add SB device ID for 3147 and 3177.
  20. Comment :
  21. jul/09/2002 : only implement two kind of dongle currently.
  22. Oct/02/2002 : work on VT8231 and VT8233 .
  23. Aug/06/2003 : change driver format to pci driver .
  24. 2004-02-16: <sda@bdit.de>
  25. - Removed unneeded 'legacy' pci stuff.
  26. - Make sure SIR mode is set (hw_init()) before calling mode-dependant stuff.
  27. - On speed change from core, don't send SIR frame with new speed.
  28. Use current speed and change speeds later.
  29. - Make module-param dongle_id actually work.
  30. - New dongle_id 17 (0x11): TDFS4500. Single-ended SIR only.
  31. Tested with home-grown PCB on EPIA boards.
  32. - Code cleanup.
  33. ********************************************************************/
  34. #include <linux/module.h>
  35. #include <linux/kernel.h>
  36. #include <linux/types.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/netdevice.h>
  39. #include <linux/ioport.h>
  40. #include <linux/delay.h>
  41. #include <linux/slab.h>
  42. #include <linux/init.h>
  43. #include <linux/rtnetlink.h>
  44. #include <linux/pci.h>
  45. #include <linux/dma-mapping.h>
  46. #include <asm/io.h>
  47. #include <asm/dma.h>
  48. #include <asm/byteorder.h>
  49. #include <linux/pm.h>
  50. #include <net/irda/wrapper.h>
  51. #include <net/irda/irda.h>
  52. #include <net/irda/irda_device.h>
  53. #include "via-ircc.h"
  54. #define VIA_MODULE_NAME "via-ircc"
  55. #define CHIP_IO_EXTENT 0x40
  56. static char *driver_name = VIA_MODULE_NAME;
  57. /* Module parameters */
  58. static int qos_mtt_bits = 0x07; /* 1 ms or more */
  59. static int dongle_id = 0; /* default: probe */
  60. /* We can't guess the type of connected dongle, user *must* supply it. */
  61. module_param(dongle_id, int, 0);
  62. /* FIXME : we should not need this, because instances should be automatically
  63. * managed by the PCI layer. Especially that we seem to only be using the
  64. * first entry. Jean II */
  65. /* Max 4 instances for now */
  66. static struct via_ircc_cb *dev_self[] = { NULL, NULL, NULL, NULL };
  67. /* Some prototypes */
  68. static int via_ircc_open(int i, chipio_t * info, unsigned int id);
  69. static int via_ircc_close(struct via_ircc_cb *self);
  70. static int via_ircc_dma_receive(struct via_ircc_cb *self);
  71. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  72. int iobase);
  73. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  74. struct net_device *dev);
  75. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  76. struct net_device *dev);
  77. static void via_hw_init(struct via_ircc_cb *self);
  78. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 baud);
  79. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id);
  80. static int via_ircc_is_receiving(struct via_ircc_cb *self);
  81. static int via_ircc_read_dongle_id(int iobase);
  82. static int via_ircc_net_open(struct net_device *dev);
  83. static int via_ircc_net_close(struct net_device *dev);
  84. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  85. int cmd);
  86. static struct net_device_stats *via_ircc_net_get_stats(struct net_device
  87. *dev);
  88. static void via_ircc_change_dongle_speed(int iobase, int speed,
  89. int dongle_id);
  90. static int RxTimerHandler(struct via_ircc_cb *self, int iobase);
  91. static void hwreset(struct via_ircc_cb *self);
  92. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase);
  93. static int upload_rxdata(struct via_ircc_cb *self, int iobase);
  94. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id);
  95. static void __devexit via_remove_one (struct pci_dev *pdev);
  96. /* FIXME : Should use udelay() instead, even if we are x86 only - Jean II */
  97. static void iodelay(int udelay)
  98. {
  99. u8 data;
  100. int i;
  101. for (i = 0; i < udelay; i++) {
  102. data = inb(0x80);
  103. }
  104. }
  105. static struct pci_device_id via_pci_tbl[] = {
  106. { PCI_VENDOR_ID_VIA, 0x8231, PCI_ANY_ID, PCI_ANY_ID,0,0,0 },
  107. { PCI_VENDOR_ID_VIA, 0x3109, PCI_ANY_ID, PCI_ANY_ID,0,0,1 },
  108. { PCI_VENDOR_ID_VIA, 0x3074, PCI_ANY_ID, PCI_ANY_ID,0,0,2 },
  109. { PCI_VENDOR_ID_VIA, 0x3147, PCI_ANY_ID, PCI_ANY_ID,0,0,3 },
  110. { PCI_VENDOR_ID_VIA, 0x3177, PCI_ANY_ID, PCI_ANY_ID,0,0,4 },
  111. { 0, }
  112. };
  113. MODULE_DEVICE_TABLE(pci,via_pci_tbl);
  114. static struct pci_driver via_driver = {
  115. .name = VIA_MODULE_NAME,
  116. .id_table = via_pci_tbl,
  117. .probe = via_init_one,
  118. .remove = __devexit_p(via_remove_one),
  119. };
  120. /*
  121. * Function via_ircc_init ()
  122. *
  123. * Initialize chip. Just find out chip type and resource.
  124. */
  125. static int __init via_ircc_init(void)
  126. {
  127. int rc;
  128. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  129. rc = pci_register_driver(&via_driver);
  130. if (rc < 0) {
  131. IRDA_DEBUG(0, "%s(): error rc = %d, returning -ENODEV...\n",
  132. __FUNCTION__, rc);
  133. return -ENODEV;
  134. }
  135. return 0;
  136. }
  137. static int __devinit via_init_one (struct pci_dev *pcidev, const struct pci_device_id *id)
  138. {
  139. int rc;
  140. u8 temp,oldPCI_40,oldPCI_44,bTmp,bTmp1;
  141. u16 Chipset,FirDRQ1,FirDRQ0,FirIRQ,FirIOBase;
  142. chipio_t info;
  143. IRDA_DEBUG(2, "%s(): Device ID=(0X%X)\n", __FUNCTION__, id->device);
  144. rc = pci_enable_device (pcidev);
  145. if (rc) {
  146. IRDA_DEBUG(0, "%s(): error rc = %d\n", __FUNCTION__, rc);
  147. return -ENODEV;
  148. }
  149. // South Bridge exist
  150. if ( ReadLPCReg(0x20) != 0x3C )
  151. Chipset=0x3096;
  152. else
  153. Chipset=0x3076;
  154. if (Chipset==0x3076) {
  155. IRDA_DEBUG(2, "%s(): Chipset = 3076\n", __FUNCTION__);
  156. WriteLPCReg(7,0x0c );
  157. temp=ReadLPCReg(0x30);//check if BIOS Enable Fir
  158. if((temp&0x01)==1) { // BIOS close or no FIR
  159. WriteLPCReg(0x1d, 0x82 );
  160. WriteLPCReg(0x23,0x18);
  161. temp=ReadLPCReg(0xF0);
  162. if((temp&0x01)==0) {
  163. temp=(ReadLPCReg(0x74)&0x03); //DMA
  164. FirDRQ0=temp + 4;
  165. temp=(ReadLPCReg(0x74)&0x0C) >> 2;
  166. FirDRQ1=temp + 4;
  167. } else {
  168. temp=(ReadLPCReg(0x74)&0x0C) >> 2; //DMA
  169. FirDRQ0=temp + 4;
  170. FirDRQ1=FirDRQ0;
  171. }
  172. FirIRQ=(ReadLPCReg(0x70)&0x0f); //IRQ
  173. FirIOBase=ReadLPCReg(0x60 ) << 8; //IO Space :high byte
  174. FirIOBase=FirIOBase| ReadLPCReg(0x61) ; //low byte
  175. FirIOBase=FirIOBase ;
  176. info.fir_base=FirIOBase;
  177. info.irq=FirIRQ;
  178. info.dma=FirDRQ1;
  179. info.dma2=FirDRQ0;
  180. pci_read_config_byte(pcidev,0x40,&bTmp);
  181. pci_write_config_byte(pcidev,0x40,((bTmp | 0x08) & 0xfe));
  182. pci_read_config_byte(pcidev,0x42,&bTmp);
  183. pci_write_config_byte(pcidev,0x42,(bTmp | 0xf0));
  184. pci_write_config_byte(pcidev,0x5a,0xc0);
  185. WriteLPCReg(0x28, 0x70 );
  186. if (via_ircc_open(0, &info,0x3076) == 0)
  187. rc=0;
  188. } else
  189. rc = -ENODEV; //IR not turn on
  190. } else { //Not VT1211
  191. IRDA_DEBUG(2, "%s(): Chipset = 3096\n", __FUNCTION__);
  192. pci_read_config_byte(pcidev,0x67,&bTmp);//check if BIOS Enable Fir
  193. if((bTmp&0x01)==1) { // BIOS enable FIR
  194. //Enable Double DMA clock
  195. pci_read_config_byte(pcidev,0x42,&oldPCI_40);
  196. pci_write_config_byte(pcidev,0x42,oldPCI_40 | 0x80);
  197. pci_read_config_byte(pcidev,0x40,&oldPCI_40);
  198. pci_write_config_byte(pcidev,0x40,oldPCI_40 & 0xf7);
  199. pci_read_config_byte(pcidev,0x44,&oldPCI_44);
  200. pci_write_config_byte(pcidev,0x44,0x4e);
  201. //---------- read configuration from Function0 of south bridge
  202. if((bTmp&0x02)==0) {
  203. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  204. FirDRQ0 = (bTmp1 & 0x30) >> 4;
  205. pci_read_config_byte(pcidev,0x44,&bTmp1);
  206. FirDRQ1 = (bTmp1 & 0xc0) >> 6;
  207. } else {
  208. pci_read_config_byte(pcidev,0x44,&bTmp1); //DMA
  209. FirDRQ0 = (bTmp1 & 0x30) >> 4 ;
  210. FirDRQ1=0;
  211. }
  212. pci_read_config_byte(pcidev,0x47,&bTmp1); //IRQ
  213. FirIRQ = bTmp1 & 0x0f;
  214. pci_read_config_byte(pcidev,0x69,&bTmp);
  215. FirIOBase = bTmp << 8;//hight byte
  216. pci_read_config_byte(pcidev,0x68,&bTmp);
  217. FirIOBase = (FirIOBase | bTmp ) & 0xfff0;
  218. //-------------------------
  219. info.fir_base=FirIOBase;
  220. info.irq=FirIRQ;
  221. info.dma=FirDRQ1;
  222. info.dma2=FirDRQ0;
  223. if (via_ircc_open(0, &info,0x3096) == 0)
  224. rc=0;
  225. } else
  226. rc = -ENODEV; //IR not turn on !!!!!
  227. }//Not VT1211
  228. IRDA_DEBUG(2, "%s(): End - rc = %d\n", __FUNCTION__, rc);
  229. return rc;
  230. }
  231. /*
  232. * Function via_ircc_clean ()
  233. *
  234. * Close all configured chips
  235. *
  236. */
  237. static void via_ircc_clean(void)
  238. {
  239. int i;
  240. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  241. for (i=0; i < ARRAY_SIZE(dev_self); i++) {
  242. if (dev_self[i])
  243. via_ircc_close(dev_self[i]);
  244. }
  245. }
  246. static void __devexit via_remove_one (struct pci_dev *pdev)
  247. {
  248. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  249. /* FIXME : This is ugly. We should use pci_get_drvdata(pdev);
  250. * to get our driver instance and call directly via_ircc_close().
  251. * See vlsi_ir for details...
  252. * Jean II */
  253. via_ircc_clean();
  254. /* FIXME : This should be in via_ircc_close(), because here we may
  255. * theoritically disable still configured devices :-( - Jean II */
  256. pci_disable_device(pdev);
  257. }
  258. static void __exit via_ircc_cleanup(void)
  259. {
  260. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  261. /* FIXME : This should be redundant, as pci_unregister_driver()
  262. * should call via_remove_one() on each device.
  263. * Jean II */
  264. via_ircc_clean();
  265. /* Cleanup all instances of the driver */
  266. pci_unregister_driver (&via_driver);
  267. }
  268. /*
  269. * Function via_ircc_open (iobase, irq)
  270. *
  271. * Open driver instance
  272. *
  273. */
  274. static __devinit int via_ircc_open(int i, chipio_t * info, unsigned int id)
  275. {
  276. struct net_device *dev;
  277. struct via_ircc_cb *self;
  278. int err;
  279. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  280. if (i >= ARRAY_SIZE(dev_self))
  281. return -ENOMEM;
  282. /* Allocate new instance of the driver */
  283. dev = alloc_irdadev(sizeof(struct via_ircc_cb));
  284. if (dev == NULL)
  285. return -ENOMEM;
  286. self = dev->priv;
  287. self->netdev = dev;
  288. spin_lock_init(&self->lock);
  289. /* FIXME : We should store our driver instance in the PCI layer,
  290. * using pci_set_drvdata(), not in this array.
  291. * See vlsi_ir for details... - Jean II */
  292. /* FIXME : 'i' is always 0 (see via_init_one()) :-( - Jean II */
  293. /* Need to store self somewhere */
  294. dev_self[i] = self;
  295. self->index = i;
  296. /* Initialize Resource */
  297. self->io.cfg_base = info->cfg_base;
  298. self->io.fir_base = info->fir_base;
  299. self->io.irq = info->irq;
  300. self->io.fir_ext = CHIP_IO_EXTENT;
  301. self->io.dma = info->dma;
  302. self->io.dma2 = info->dma2;
  303. self->io.fifo_size = 32;
  304. self->chip_id = id;
  305. self->st_fifo.len = 0;
  306. self->RxDataReady = 0;
  307. /* Reserve the ioports that we need */
  308. if (!request_region(self->io.fir_base, self->io.fir_ext, driver_name)) {
  309. IRDA_DEBUG(0, "%s(), can't get iobase of 0x%03x\n",
  310. __FUNCTION__, self->io.fir_base);
  311. err = -ENODEV;
  312. goto err_out1;
  313. }
  314. /* Initialize QoS for this device */
  315. irda_init_max_qos_capabilies(&self->qos);
  316. /* Check if user has supplied the dongle id or not */
  317. if (!dongle_id)
  318. dongle_id = via_ircc_read_dongle_id(self->io.fir_base);
  319. self->io.dongle_id = dongle_id;
  320. /* The only value we must override it the baudrate */
  321. /* Maximum speeds and capabilities are dongle-dependant. */
  322. switch( self->io.dongle_id ){
  323. case 0x0d:
  324. self->qos.baud_rate.bits =
  325. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200 |
  326. IR_576000 | IR_1152000 | (IR_4000000 << 8);
  327. break;
  328. default:
  329. self->qos.baud_rate.bits =
  330. IR_9600 | IR_19200 | IR_38400 | IR_57600 | IR_115200;
  331. break;
  332. }
  333. /* Following was used for testing:
  334. *
  335. * self->qos.baud_rate.bits = IR_9600;
  336. *
  337. * Is is no good, as it prohibits (error-prone) speed-changes.
  338. */
  339. self->qos.min_turn_time.bits = qos_mtt_bits;
  340. irda_qos_bits_to_value(&self->qos);
  341. /* Max DMA buffer size needed = (data_size + 6) * (window_size) + 6; */
  342. self->rx_buff.truesize = 14384 + 2048;
  343. self->tx_buff.truesize = 14384 + 2048;
  344. /* Allocate memory if needed */
  345. self->rx_buff.head =
  346. dma_alloc_coherent(NULL, self->rx_buff.truesize,
  347. &self->rx_buff_dma, GFP_KERNEL);
  348. if (self->rx_buff.head == NULL) {
  349. err = -ENOMEM;
  350. goto err_out2;
  351. }
  352. memset(self->rx_buff.head, 0, self->rx_buff.truesize);
  353. self->tx_buff.head =
  354. dma_alloc_coherent(NULL, self->tx_buff.truesize,
  355. &self->tx_buff_dma, GFP_KERNEL);
  356. if (self->tx_buff.head == NULL) {
  357. err = -ENOMEM;
  358. goto err_out3;
  359. }
  360. memset(self->tx_buff.head, 0, self->tx_buff.truesize);
  361. self->rx_buff.in_frame = FALSE;
  362. self->rx_buff.state = OUTSIDE_FRAME;
  363. self->tx_buff.data = self->tx_buff.head;
  364. self->rx_buff.data = self->rx_buff.head;
  365. /* Reset Tx queue info */
  366. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  367. self->tx_fifo.tail = self->tx_buff.head;
  368. /* Keep track of module usage */
  369. SET_MODULE_OWNER(dev);
  370. /* Override the network functions we need to use */
  371. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  372. dev->open = via_ircc_net_open;
  373. dev->stop = via_ircc_net_close;
  374. dev->do_ioctl = via_ircc_net_ioctl;
  375. dev->get_stats = via_ircc_net_get_stats;
  376. err = register_netdev(dev);
  377. if (err)
  378. goto err_out4;
  379. IRDA_MESSAGE("IrDA: Registered device %s (via-ircc)\n", dev->name);
  380. /* Initialise the hardware..
  381. */
  382. self->io.speed = 9600;
  383. via_hw_init(self);
  384. return 0;
  385. err_out4:
  386. dma_free_coherent(NULL, self->tx_buff.truesize,
  387. self->tx_buff.head, self->tx_buff_dma);
  388. err_out3:
  389. dma_free_coherent(NULL, self->rx_buff.truesize,
  390. self->rx_buff.head, self->rx_buff_dma);
  391. err_out2:
  392. release_region(self->io.fir_base, self->io.fir_ext);
  393. err_out1:
  394. free_netdev(dev);
  395. dev_self[i] = NULL;
  396. return err;
  397. }
  398. /*
  399. * Function via_ircc_close (self)
  400. *
  401. * Close driver instance
  402. *
  403. */
  404. static int via_ircc_close(struct via_ircc_cb *self)
  405. {
  406. int iobase;
  407. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  408. IRDA_ASSERT(self != NULL, return -1;);
  409. iobase = self->io.fir_base;
  410. ResetChip(iobase, 5); //hardware reset.
  411. /* Remove netdevice */
  412. unregister_netdev(self->netdev);
  413. /* Release the PORT that this driver is using */
  414. IRDA_DEBUG(2, "%s(), Releasing Region %03x\n",
  415. __FUNCTION__, self->io.fir_base);
  416. release_region(self->io.fir_base, self->io.fir_ext);
  417. if (self->tx_buff.head)
  418. dma_free_coherent(NULL, self->tx_buff.truesize,
  419. self->tx_buff.head, self->tx_buff_dma);
  420. if (self->rx_buff.head)
  421. dma_free_coherent(NULL, self->rx_buff.truesize,
  422. self->rx_buff.head, self->rx_buff_dma);
  423. dev_self[self->index] = NULL;
  424. free_netdev(self->netdev);
  425. return 0;
  426. }
  427. /*
  428. * Function via_hw_init(self)
  429. *
  430. * Returns non-negative on success.
  431. *
  432. * Formerly via_ircc_setup
  433. */
  434. static void via_hw_init(struct via_ircc_cb *self)
  435. {
  436. int iobase = self->io.fir_base;
  437. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  438. SetMaxRxPacketSize(iobase, 0x0fff); //set to max:4095
  439. // FIFO Init
  440. EnRXFIFOReadyInt(iobase, OFF);
  441. EnRXFIFOHalfLevelInt(iobase, OFF);
  442. EnTXFIFOHalfLevelInt(iobase, OFF);
  443. EnTXFIFOUnderrunEOMInt(iobase, ON);
  444. EnTXFIFOReadyInt(iobase, OFF);
  445. InvertTX(iobase, OFF);
  446. InvertRX(iobase, OFF);
  447. if (ReadLPCReg(0x20) == 0x3c)
  448. WriteLPCReg(0xF0, 0); // for VT1211
  449. /* Int Init */
  450. EnRXSpecInt(iobase, ON);
  451. /* The following is basically hwreset */
  452. /* If this is the case, why not just call hwreset() ? Jean II */
  453. ResetChip(iobase, 5);
  454. EnableDMA(iobase, OFF);
  455. EnableTX(iobase, OFF);
  456. EnableRX(iobase, OFF);
  457. EnRXDMA(iobase, OFF);
  458. EnTXDMA(iobase, OFF);
  459. RXStart(iobase, OFF);
  460. TXStart(iobase, OFF);
  461. InitCard(iobase);
  462. CommonInit(iobase);
  463. SIRFilter(iobase, ON);
  464. SetSIR(iobase, ON);
  465. CRC16(iobase, ON);
  466. EnTXCRC(iobase, 0);
  467. WriteReg(iobase, I_ST_CT_0, 0x00);
  468. SetBaudRate(iobase, 9600);
  469. SetPulseWidth(iobase, 12);
  470. SetSendPreambleCount(iobase, 0);
  471. self->io.speed = 9600;
  472. self->st_fifo.len = 0;
  473. via_ircc_change_dongle_speed(iobase, self->io.speed,
  474. self->io.dongle_id);
  475. WriteReg(iobase, I_ST_CT_0, 0x80);
  476. }
  477. /*
  478. * Function via_ircc_read_dongle_id (void)
  479. *
  480. */
  481. static int via_ircc_read_dongle_id(int iobase)
  482. {
  483. int dongle_id = 9; /* Default to IBM */
  484. IRDA_ERROR("via-ircc: dongle probing not supported, please specify dongle_id module parameter.\n");
  485. return dongle_id;
  486. }
  487. /*
  488. * Function via_ircc_change_dongle_speed (iobase, speed, dongle_id)
  489. * Change speed of the attach dongle
  490. * only implement two type of dongle currently.
  491. */
  492. static void via_ircc_change_dongle_speed(int iobase, int speed,
  493. int dongle_id)
  494. {
  495. u8 mode = 0;
  496. /* speed is unused, as we use IsSIROn()/IsMIROn() */
  497. speed = speed;
  498. IRDA_DEBUG(1, "%s(): change_dongle_speed to %d for 0x%x, %d\n",
  499. __FUNCTION__, speed, iobase, dongle_id);
  500. switch (dongle_id) {
  501. /* Note: The dongle_id's listed here are derived from
  502. * nsc-ircc.c */
  503. case 0x08: /* HP HSDL-2300, HP HSDL-3600/HSDL-3610 */
  504. UseOneRX(iobase, ON); // use one RX pin RX1,RX2
  505. InvertTX(iobase, OFF);
  506. InvertRX(iobase, OFF);
  507. EnRX2(iobase, ON); //sir to rx2
  508. EnGPIOtoRX2(iobase, OFF);
  509. if (IsSIROn(iobase)) { //sir
  510. // Mode select Off
  511. SlowIRRXLowActive(iobase, ON);
  512. udelay(1000);
  513. SlowIRRXLowActive(iobase, OFF);
  514. } else {
  515. if (IsMIROn(iobase)) { //mir
  516. // Mode select On
  517. SlowIRRXLowActive(iobase, OFF);
  518. udelay(20);
  519. } else { // fir
  520. if (IsFIROn(iobase)) { //fir
  521. // Mode select On
  522. SlowIRRXLowActive(iobase, OFF);
  523. udelay(20);
  524. }
  525. }
  526. }
  527. break;
  528. case 0x09: /* IBM31T1100 or Temic TFDS6000/TFDS6500 */
  529. UseOneRX(iobase, ON); //use ONE RX....RX1
  530. InvertTX(iobase, OFF);
  531. InvertRX(iobase, OFF); // invert RX pin
  532. EnRX2(iobase, ON);
  533. EnGPIOtoRX2(iobase, OFF);
  534. if (IsSIROn(iobase)) { //sir
  535. // Mode select On
  536. SlowIRRXLowActive(iobase, ON);
  537. udelay(20);
  538. // Mode select Off
  539. SlowIRRXLowActive(iobase, OFF);
  540. }
  541. if (IsMIROn(iobase)) { //mir
  542. // Mode select On
  543. SlowIRRXLowActive(iobase, OFF);
  544. udelay(20);
  545. // Mode select Off
  546. SlowIRRXLowActive(iobase, ON);
  547. } else { // fir
  548. if (IsFIROn(iobase)) { //fir
  549. // Mode select On
  550. SlowIRRXLowActive(iobase, OFF);
  551. // TX On
  552. WriteTX(iobase, ON);
  553. udelay(20);
  554. // Mode select OFF
  555. SlowIRRXLowActive(iobase, ON);
  556. udelay(20);
  557. // TX Off
  558. WriteTX(iobase, OFF);
  559. }
  560. }
  561. break;
  562. case 0x0d:
  563. UseOneRX(iobase, OFF); // use two RX pin RX1,RX2
  564. InvertTX(iobase, OFF);
  565. InvertRX(iobase, OFF);
  566. SlowIRRXLowActive(iobase, OFF);
  567. if (IsSIROn(iobase)) { //sir
  568. EnGPIOtoRX2(iobase, OFF);
  569. WriteGIO(iobase, OFF);
  570. EnRX2(iobase, OFF); //sir to rx2
  571. } else { // fir mir
  572. EnGPIOtoRX2(iobase, OFF);
  573. WriteGIO(iobase, OFF);
  574. EnRX2(iobase, OFF); //fir to rx
  575. }
  576. break;
  577. case 0x11: /* Temic TFDS4500 */
  578. IRDA_DEBUG(2, "%s: Temic TFDS4500: One RX pin, TX normal, RX inverted.\n", __FUNCTION__);
  579. UseOneRX(iobase, ON); //use ONE RX....RX1
  580. InvertTX(iobase, OFF);
  581. InvertRX(iobase, ON); // invert RX pin
  582. EnRX2(iobase, ON); //sir to rx2
  583. EnGPIOtoRX2(iobase, OFF);
  584. if( IsSIROn(iobase) ){ //sir
  585. // Mode select On
  586. SlowIRRXLowActive(iobase, ON);
  587. udelay(20);
  588. // Mode select Off
  589. SlowIRRXLowActive(iobase, OFF);
  590. } else{
  591. IRDA_DEBUG(0, "%s: Warning: TFDS4500 not running in SIR mode !\n", __FUNCTION__);
  592. }
  593. break;
  594. case 0x0ff: /* Vishay */
  595. if (IsSIROn(iobase))
  596. mode = 0;
  597. else if (IsMIROn(iobase))
  598. mode = 1;
  599. else if (IsFIROn(iobase))
  600. mode = 2;
  601. else if (IsVFIROn(iobase))
  602. mode = 5; //VFIR-16
  603. SI_SetMode(iobase, mode);
  604. break;
  605. default:
  606. IRDA_ERROR("%s: Error: dongle_id %d unsupported !\n",
  607. __FUNCTION__, dongle_id);
  608. }
  609. }
  610. /*
  611. * Function via_ircc_change_speed (self, baud)
  612. *
  613. * Change the speed of the device
  614. *
  615. */
  616. static void via_ircc_change_speed(struct via_ircc_cb *self, __u32 speed)
  617. {
  618. struct net_device *dev = self->netdev;
  619. u16 iobase;
  620. u8 value = 0, bTmp;
  621. iobase = self->io.fir_base;
  622. /* Update accounting for new speed */
  623. self->io.speed = speed;
  624. IRDA_DEBUG(1, "%s: change_speed to %d bps.\n", __FUNCTION__, speed);
  625. WriteReg(iobase, I_ST_CT_0, 0x0);
  626. /* Controller mode sellection */
  627. switch (speed) {
  628. case 2400:
  629. case 9600:
  630. case 19200:
  631. case 38400:
  632. case 57600:
  633. case 115200:
  634. value = (115200/speed)-1;
  635. SetSIR(iobase, ON);
  636. CRC16(iobase, ON);
  637. break;
  638. case 576000:
  639. /* FIXME: this can't be right, as it's the same as 115200,
  640. * and 576000 is MIR, not SIR. */
  641. value = 0;
  642. SetSIR(iobase, ON);
  643. CRC16(iobase, ON);
  644. break;
  645. case 1152000:
  646. value = 0;
  647. SetMIR(iobase, ON);
  648. /* FIXME: CRC ??? */
  649. break;
  650. case 4000000:
  651. value = 0;
  652. SetFIR(iobase, ON);
  653. SetPulseWidth(iobase, 0);
  654. SetSendPreambleCount(iobase, 14);
  655. CRC16(iobase, OFF);
  656. EnTXCRC(iobase, ON);
  657. break;
  658. case 16000000:
  659. value = 0;
  660. SetVFIR(iobase, ON);
  661. /* FIXME: CRC ??? */
  662. break;
  663. default:
  664. value = 0;
  665. break;
  666. }
  667. /* Set baudrate to 0x19[2..7] */
  668. bTmp = (ReadReg(iobase, I_CF_H_1) & 0x03);
  669. bTmp |= value << 2;
  670. WriteReg(iobase, I_CF_H_1, bTmp);
  671. /* Some dongles may need to be informed about speed changes. */
  672. via_ircc_change_dongle_speed(iobase, speed, self->io.dongle_id);
  673. /* Set FIFO size to 64 */
  674. SetFIFO(iobase, 64);
  675. /* Enable IR */
  676. WriteReg(iobase, I_ST_CT_0, 0x80);
  677. // EnTXFIFOHalfLevelInt(iobase,ON);
  678. /* Enable some interrupts so we can receive frames */
  679. //EnAllInt(iobase,ON);
  680. if (IsSIROn(iobase)) {
  681. SIRFilter(iobase, ON);
  682. SIRRecvAny(iobase, ON);
  683. } else {
  684. SIRFilter(iobase, OFF);
  685. SIRRecvAny(iobase, OFF);
  686. }
  687. if (speed > 115200) {
  688. /* Install FIR xmit handler */
  689. dev->hard_start_xmit = via_ircc_hard_xmit_fir;
  690. via_ircc_dma_receive(self);
  691. } else {
  692. /* Install SIR xmit handler */
  693. dev->hard_start_xmit = via_ircc_hard_xmit_sir;
  694. }
  695. netif_wake_queue(dev);
  696. }
  697. /*
  698. * Function via_ircc_hard_xmit (skb, dev)
  699. *
  700. * Transmit the frame!
  701. *
  702. */
  703. static int via_ircc_hard_xmit_sir(struct sk_buff *skb,
  704. struct net_device *dev)
  705. {
  706. struct via_ircc_cb *self;
  707. unsigned long flags;
  708. u16 iobase;
  709. __u32 speed;
  710. self = (struct via_ircc_cb *) dev->priv;
  711. IRDA_ASSERT(self != NULL, return 0;);
  712. iobase = self->io.fir_base;
  713. netif_stop_queue(dev);
  714. /* Check if we need to change the speed */
  715. speed = irda_get_next_speed(skb);
  716. if ((speed != self->io.speed) && (speed != -1)) {
  717. /* Check for empty frame */
  718. if (!skb->len) {
  719. via_ircc_change_speed(self, speed);
  720. dev->trans_start = jiffies;
  721. dev_kfree_skb(skb);
  722. return 0;
  723. } else
  724. self->new_speed = speed;
  725. }
  726. InitCard(iobase);
  727. CommonInit(iobase);
  728. SIRFilter(iobase, ON);
  729. SetSIR(iobase, ON);
  730. CRC16(iobase, ON);
  731. EnTXCRC(iobase, 0);
  732. WriteReg(iobase, I_ST_CT_0, 0x00);
  733. spin_lock_irqsave(&self->lock, flags);
  734. self->tx_buff.data = self->tx_buff.head;
  735. self->tx_buff.len =
  736. async_wrap_skb(skb, self->tx_buff.data,
  737. self->tx_buff.truesize);
  738. self->stats.tx_bytes += self->tx_buff.len;
  739. /* Send this frame with old speed */
  740. SetBaudRate(iobase, self->io.speed);
  741. SetPulseWidth(iobase, 12);
  742. SetSendPreambleCount(iobase, 0);
  743. WriteReg(iobase, I_ST_CT_0, 0x80);
  744. EnableTX(iobase, ON);
  745. EnableRX(iobase, OFF);
  746. ResetChip(iobase, 0);
  747. ResetChip(iobase, 1);
  748. ResetChip(iobase, 2);
  749. ResetChip(iobase, 3);
  750. ResetChip(iobase, 4);
  751. EnAllInt(iobase, ON);
  752. EnTXDMA(iobase, ON);
  753. EnRXDMA(iobase, OFF);
  754. irda_setup_dma(self->io.dma, self->tx_buff_dma, self->tx_buff.len,
  755. DMA_TX_MODE);
  756. SetSendByte(iobase, self->tx_buff.len);
  757. RXStart(iobase, OFF);
  758. TXStart(iobase, ON);
  759. dev->trans_start = jiffies;
  760. spin_unlock_irqrestore(&self->lock, flags);
  761. dev_kfree_skb(skb);
  762. return 0;
  763. }
  764. static int via_ircc_hard_xmit_fir(struct sk_buff *skb,
  765. struct net_device *dev)
  766. {
  767. struct via_ircc_cb *self;
  768. u16 iobase;
  769. __u32 speed;
  770. unsigned long flags;
  771. self = (struct via_ircc_cb *) dev->priv;
  772. iobase = self->io.fir_base;
  773. if (self->st_fifo.len)
  774. return 0;
  775. if (self->chip_id == 0x3076)
  776. iodelay(1500);
  777. else
  778. udelay(1500);
  779. netif_stop_queue(dev);
  780. speed = irda_get_next_speed(skb);
  781. if ((speed != self->io.speed) && (speed != -1)) {
  782. if (!skb->len) {
  783. via_ircc_change_speed(self, speed);
  784. dev->trans_start = jiffies;
  785. dev_kfree_skb(skb);
  786. return 0;
  787. } else
  788. self->new_speed = speed;
  789. }
  790. spin_lock_irqsave(&self->lock, flags);
  791. self->tx_fifo.queue[self->tx_fifo.free].start = self->tx_fifo.tail;
  792. self->tx_fifo.queue[self->tx_fifo.free].len = skb->len;
  793. self->tx_fifo.tail += skb->len;
  794. self->stats.tx_bytes += skb->len;
  795. memcpy(self->tx_fifo.queue[self->tx_fifo.free].start, skb->data,
  796. skb->len);
  797. self->tx_fifo.len++;
  798. self->tx_fifo.free++;
  799. //F01 if (self->tx_fifo.len == 1) {
  800. via_ircc_dma_xmit(self, iobase);
  801. //F01 }
  802. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) netif_wake_queue(self->netdev);
  803. dev->trans_start = jiffies;
  804. dev_kfree_skb(skb);
  805. spin_unlock_irqrestore(&self->lock, flags);
  806. return 0;
  807. }
  808. static int via_ircc_dma_xmit(struct via_ircc_cb *self, u16 iobase)
  809. {
  810. EnTXDMA(iobase, OFF);
  811. self->io.direction = IO_XMIT;
  812. EnPhys(iobase, ON);
  813. EnableTX(iobase, ON);
  814. EnableRX(iobase, OFF);
  815. ResetChip(iobase, 0);
  816. ResetChip(iobase, 1);
  817. ResetChip(iobase, 2);
  818. ResetChip(iobase, 3);
  819. ResetChip(iobase, 4);
  820. EnAllInt(iobase, ON);
  821. EnTXDMA(iobase, ON);
  822. EnRXDMA(iobase, OFF);
  823. irda_setup_dma(self->io.dma,
  824. ((u8 *)self->tx_fifo.queue[self->tx_fifo.ptr].start -
  825. self->tx_buff.head) + self->tx_buff_dma,
  826. self->tx_fifo.queue[self->tx_fifo.ptr].len, DMA_TX_MODE);
  827. IRDA_DEBUG(1, "%s: tx_fifo.ptr=%x,len=%x,tx_fifo.len=%x..\n",
  828. __FUNCTION__, self->tx_fifo.ptr,
  829. self->tx_fifo.queue[self->tx_fifo.ptr].len,
  830. self->tx_fifo.len);
  831. SetSendByte(iobase, self->tx_fifo.queue[self->tx_fifo.ptr].len);
  832. RXStart(iobase, OFF);
  833. TXStart(iobase, ON);
  834. return 0;
  835. }
  836. /*
  837. * Function via_ircc_dma_xmit_complete (self)
  838. *
  839. * The transfer of a frame in finished. This function will only be called
  840. * by the interrupt handler
  841. *
  842. */
  843. static int via_ircc_dma_xmit_complete(struct via_ircc_cb *self)
  844. {
  845. int iobase;
  846. int ret = TRUE;
  847. u8 Tx_status;
  848. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  849. iobase = self->io.fir_base;
  850. /* Disable DMA */
  851. // DisableDmaChannel(self->io.dma);
  852. /* Check for underrrun! */
  853. /* Clear bit, by writing 1 into it */
  854. Tx_status = GetTXStatus(iobase);
  855. if (Tx_status & 0x08) {
  856. self->stats.tx_errors++;
  857. self->stats.tx_fifo_errors++;
  858. hwreset(self);
  859. // how to clear underrrun ?
  860. } else {
  861. self->stats.tx_packets++;
  862. ResetChip(iobase, 3);
  863. ResetChip(iobase, 4);
  864. }
  865. /* Check if we need to change the speed */
  866. if (self->new_speed) {
  867. via_ircc_change_speed(self, self->new_speed);
  868. self->new_speed = 0;
  869. }
  870. /* Finished with this frame, so prepare for next */
  871. if (IsFIROn(iobase)) {
  872. if (self->tx_fifo.len) {
  873. self->tx_fifo.len--;
  874. self->tx_fifo.ptr++;
  875. }
  876. }
  877. IRDA_DEBUG(1,
  878. "%s: tx_fifo.len=%x ,tx_fifo.ptr=%x,tx_fifo.free=%x...\n",
  879. __FUNCTION__,
  880. self->tx_fifo.len, self->tx_fifo.ptr, self->tx_fifo.free);
  881. /* F01_S
  882. // Any frames to be sent back-to-back?
  883. if (self->tx_fifo.len) {
  884. // Not finished yet!
  885. via_ircc_dma_xmit(self, iobase);
  886. ret = FALSE;
  887. } else {
  888. F01_E*/
  889. // Reset Tx FIFO info
  890. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  891. self->tx_fifo.tail = self->tx_buff.head;
  892. //F01 }
  893. // Make sure we have room for more frames
  894. //F01 if (self->tx_fifo.free < (MAX_TX_WINDOW -1 )) {
  895. // Not busy transmitting anymore
  896. // Tell the network layer, that we can accept more frames
  897. netif_wake_queue(self->netdev);
  898. //F01 }
  899. return ret;
  900. }
  901. /*
  902. * Function via_ircc_dma_receive (self)
  903. *
  904. * Set configuration for receive a frame.
  905. *
  906. */
  907. static int via_ircc_dma_receive(struct via_ircc_cb *self)
  908. {
  909. int iobase;
  910. iobase = self->io.fir_base;
  911. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  912. self->tx_fifo.len = self->tx_fifo.ptr = self->tx_fifo.free = 0;
  913. self->tx_fifo.tail = self->tx_buff.head;
  914. self->RxDataReady = 0;
  915. self->io.direction = IO_RECV;
  916. self->rx_buff.data = self->rx_buff.head;
  917. self->st_fifo.len = self->st_fifo.pending_bytes = 0;
  918. self->st_fifo.tail = self->st_fifo.head = 0;
  919. EnPhys(iobase, ON);
  920. EnableTX(iobase, OFF);
  921. EnableRX(iobase, ON);
  922. ResetChip(iobase, 0);
  923. ResetChip(iobase, 1);
  924. ResetChip(iobase, 2);
  925. ResetChip(iobase, 3);
  926. ResetChip(iobase, 4);
  927. EnAllInt(iobase, ON);
  928. EnTXDMA(iobase, OFF);
  929. EnRXDMA(iobase, ON);
  930. irda_setup_dma(self->io.dma2, self->rx_buff_dma,
  931. self->rx_buff.truesize, DMA_RX_MODE);
  932. TXStart(iobase, OFF);
  933. RXStart(iobase, ON);
  934. return 0;
  935. }
  936. /*
  937. * Function via_ircc_dma_receive_complete (self)
  938. *
  939. * Controller Finished with receiving frames,
  940. * and this routine is call by ISR
  941. *
  942. */
  943. static int via_ircc_dma_receive_complete(struct via_ircc_cb *self,
  944. int iobase)
  945. {
  946. struct st_fifo *st_fifo;
  947. struct sk_buff *skb;
  948. int len, i;
  949. u8 status = 0;
  950. iobase = self->io.fir_base;
  951. st_fifo = &self->st_fifo;
  952. if (self->io.speed < 4000000) { //Speed below FIR
  953. len = GetRecvByte(iobase, self);
  954. skb = dev_alloc_skb(len + 1);
  955. if (skb == NULL)
  956. return FALSE;
  957. // Make sure IP header gets aligned
  958. skb_reserve(skb, 1);
  959. skb_put(skb, len - 2);
  960. if (self->chip_id == 0x3076) {
  961. for (i = 0; i < len - 2; i++)
  962. skb->data[i] = self->rx_buff.data[i * 2];
  963. } else {
  964. if (self->chip_id == 0x3096) {
  965. for (i = 0; i < len - 2; i++)
  966. skb->data[i] =
  967. self->rx_buff.data[i];
  968. }
  969. }
  970. // Move to next frame
  971. self->rx_buff.data += len;
  972. self->stats.rx_bytes += len;
  973. self->stats.rx_packets++;
  974. skb->dev = self->netdev;
  975. skb->mac.raw = skb->data;
  976. skb->protocol = htons(ETH_P_IRDA);
  977. netif_rx(skb);
  978. return TRUE;
  979. }
  980. else { //FIR mode
  981. len = GetRecvByte(iobase, self);
  982. if (len == 0)
  983. return TRUE; //interrupt only, data maybe move by RxT
  984. if (((len - 4) < 2) || ((len - 4) > 2048)) {
  985. IRDA_DEBUG(1, "%s(): Trouble:len=%x,CurCount=%x,LastCount=%x..\n",
  986. __FUNCTION__, len, RxCurCount(iobase, self),
  987. self->RxLastCount);
  988. hwreset(self);
  989. return FALSE;
  990. }
  991. IRDA_DEBUG(2, "%s(): fifo.len=%x,len=%x,CurCount=%x..\n",
  992. __FUNCTION__,
  993. st_fifo->len, len - 4, RxCurCount(iobase, self));
  994. st_fifo->entries[st_fifo->tail].status = status;
  995. st_fifo->entries[st_fifo->tail].len = len;
  996. st_fifo->pending_bytes += len;
  997. st_fifo->tail++;
  998. st_fifo->len++;
  999. if (st_fifo->tail > MAX_RX_WINDOW)
  1000. st_fifo->tail = 0;
  1001. self->RxDataReady = 0;
  1002. // It maybe have MAX_RX_WINDOW package receive by
  1003. // receive_complete before Timer IRQ
  1004. /* F01_S
  1005. if (st_fifo->len < (MAX_RX_WINDOW+2 )) {
  1006. RXStart(iobase,ON);
  1007. SetTimer(iobase,4);
  1008. }
  1009. else {
  1010. F01_E */
  1011. EnableRX(iobase, OFF);
  1012. EnRXDMA(iobase, OFF);
  1013. RXStart(iobase, OFF);
  1014. //F01_S
  1015. // Put this entry back in fifo
  1016. if (st_fifo->head > MAX_RX_WINDOW)
  1017. st_fifo->head = 0;
  1018. status = st_fifo->entries[st_fifo->head].status;
  1019. len = st_fifo->entries[st_fifo->head].len;
  1020. st_fifo->head++;
  1021. st_fifo->len--;
  1022. skb = dev_alloc_skb(len + 1 - 4);
  1023. /*
  1024. * if frame size,data ptr,or skb ptr are wrong ,the get next
  1025. * entry.
  1026. */
  1027. if ((skb == NULL) || (skb->data == NULL)
  1028. || (self->rx_buff.data == NULL) || (len < 6)) {
  1029. self->stats.rx_dropped++;
  1030. return TRUE;
  1031. }
  1032. skb_reserve(skb, 1);
  1033. skb_put(skb, len - 4);
  1034. memcpy(skb->data, self->rx_buff.data, len - 4);
  1035. IRDA_DEBUG(2, "%s(): len=%x.rx_buff=%p\n", __FUNCTION__,
  1036. len - 4, self->rx_buff.data);
  1037. // Move to next frame
  1038. self->rx_buff.data += len;
  1039. self->stats.rx_bytes += len;
  1040. self->stats.rx_packets++;
  1041. skb->dev = self->netdev;
  1042. skb->mac.raw = skb->data;
  1043. skb->protocol = htons(ETH_P_IRDA);
  1044. netif_rx(skb);
  1045. //F01_E
  1046. } //FIR
  1047. return TRUE;
  1048. }
  1049. /*
  1050. * if frame is received , but no INT ,then use this routine to upload frame.
  1051. */
  1052. static int upload_rxdata(struct via_ircc_cb *self, int iobase)
  1053. {
  1054. struct sk_buff *skb;
  1055. int len;
  1056. struct st_fifo *st_fifo;
  1057. st_fifo = &self->st_fifo;
  1058. len = GetRecvByte(iobase, self);
  1059. IRDA_DEBUG(2, "%s(): len=%x\n", __FUNCTION__, len);
  1060. if ((len - 4) < 2) {
  1061. self->stats.rx_dropped++;
  1062. return FALSE;
  1063. }
  1064. skb = dev_alloc_skb(len + 1);
  1065. if (skb == NULL) {
  1066. self->stats.rx_dropped++;
  1067. return FALSE;
  1068. }
  1069. skb_reserve(skb, 1);
  1070. skb_put(skb, len - 4 + 1);
  1071. memcpy(skb->data, self->rx_buff.data, len - 4 + 1);
  1072. st_fifo->tail++;
  1073. st_fifo->len++;
  1074. if (st_fifo->tail > MAX_RX_WINDOW)
  1075. st_fifo->tail = 0;
  1076. // Move to next frame
  1077. self->rx_buff.data += len;
  1078. self->stats.rx_bytes += len;
  1079. self->stats.rx_packets++;
  1080. skb->dev = self->netdev;
  1081. skb->mac.raw = skb->data;
  1082. skb->protocol = htons(ETH_P_IRDA);
  1083. netif_rx(skb);
  1084. if (st_fifo->len < (MAX_RX_WINDOW + 2)) {
  1085. RXStart(iobase, ON);
  1086. } else {
  1087. EnableRX(iobase, OFF);
  1088. EnRXDMA(iobase, OFF);
  1089. RXStart(iobase, OFF);
  1090. }
  1091. return TRUE;
  1092. }
  1093. /*
  1094. * Implement back to back receive , use this routine to upload data.
  1095. */
  1096. static int RxTimerHandler(struct via_ircc_cb *self, int iobase)
  1097. {
  1098. struct st_fifo *st_fifo;
  1099. struct sk_buff *skb;
  1100. int len;
  1101. u8 status;
  1102. st_fifo = &self->st_fifo;
  1103. if (CkRxRecv(iobase, self)) {
  1104. // if still receiving ,then return ,don't upload frame
  1105. self->RetryCount = 0;
  1106. SetTimer(iobase, 20);
  1107. self->RxDataReady++;
  1108. return FALSE;
  1109. } else
  1110. self->RetryCount++;
  1111. if ((self->RetryCount >= 1) ||
  1112. ((st_fifo->pending_bytes + 2048) > self->rx_buff.truesize)
  1113. || (st_fifo->len >= (MAX_RX_WINDOW))) {
  1114. while (st_fifo->len > 0) { //upload frame
  1115. // Put this entry back in fifo
  1116. if (st_fifo->head > MAX_RX_WINDOW)
  1117. st_fifo->head = 0;
  1118. status = st_fifo->entries[st_fifo->head].status;
  1119. len = st_fifo->entries[st_fifo->head].len;
  1120. st_fifo->head++;
  1121. st_fifo->len--;
  1122. skb = dev_alloc_skb(len + 1 - 4);
  1123. /*
  1124. * if frame size, data ptr, or skb ptr are wrong,
  1125. * then get next entry.
  1126. */
  1127. if ((skb == NULL) || (skb->data == NULL)
  1128. || (self->rx_buff.data == NULL) || (len < 6)) {
  1129. self->stats.rx_dropped++;
  1130. continue;
  1131. }
  1132. skb_reserve(skb, 1);
  1133. skb_put(skb, len - 4);
  1134. memcpy(skb->data, self->rx_buff.data, len - 4);
  1135. IRDA_DEBUG(2, "%s(): len=%x.head=%x\n", __FUNCTION__,
  1136. len - 4, st_fifo->head);
  1137. // Move to next frame
  1138. self->rx_buff.data += len;
  1139. self->stats.rx_bytes += len;
  1140. self->stats.rx_packets++;
  1141. skb->dev = self->netdev;
  1142. skb->mac.raw = skb->data;
  1143. skb->protocol = htons(ETH_P_IRDA);
  1144. netif_rx(skb);
  1145. } //while
  1146. self->RetryCount = 0;
  1147. IRDA_DEBUG(2,
  1148. "%s(): End of upload HostStatus=%x,RxStatus=%x\n",
  1149. __FUNCTION__,
  1150. GetHostStatus(iobase), GetRXStatus(iobase));
  1151. /*
  1152. * if frame is receive complete at this routine ,then upload
  1153. * frame.
  1154. */
  1155. if ((GetRXStatus(iobase) & 0x10)
  1156. && (RxCurCount(iobase, self) != self->RxLastCount)) {
  1157. upload_rxdata(self, iobase);
  1158. if (irda_device_txqueue_empty(self->netdev))
  1159. via_ircc_dma_receive(self);
  1160. }
  1161. } // timer detect complete
  1162. else
  1163. SetTimer(iobase, 4);
  1164. return TRUE;
  1165. }
  1166. /*
  1167. * Function via_ircc_interrupt (irq, dev_id)
  1168. *
  1169. * An interrupt from the chip has arrived. Time to do some work
  1170. *
  1171. */
  1172. static irqreturn_t via_ircc_interrupt(int irq, void *dev_id)
  1173. {
  1174. struct net_device *dev = (struct net_device *) dev_id;
  1175. struct via_ircc_cb *self;
  1176. int iobase;
  1177. u8 iHostIntType, iRxIntType, iTxIntType;
  1178. if (!dev) {
  1179. IRDA_WARNING("%s: irq %d for unknown device.\n", driver_name,
  1180. irq);
  1181. return IRQ_NONE;
  1182. }
  1183. self = (struct via_ircc_cb *) dev->priv;
  1184. iobase = self->io.fir_base;
  1185. spin_lock(&self->lock);
  1186. iHostIntType = GetHostStatus(iobase);
  1187. IRDA_DEBUG(4, "%s(): iHostIntType %02x: %s %s %s %02x\n",
  1188. __FUNCTION__, iHostIntType,
  1189. (iHostIntType & 0x40) ? "Timer" : "",
  1190. (iHostIntType & 0x20) ? "Tx" : "",
  1191. (iHostIntType & 0x10) ? "Rx" : "",
  1192. (iHostIntType & 0x0e) >> 1);
  1193. if ((iHostIntType & 0x40) != 0) { //Timer Event
  1194. self->EventFlag.TimeOut++;
  1195. ClearTimerInt(iobase, 1);
  1196. if (self->io.direction == IO_XMIT) {
  1197. via_ircc_dma_xmit(self, iobase);
  1198. }
  1199. if (self->io.direction == IO_RECV) {
  1200. /*
  1201. * frame ready hold too long, must reset.
  1202. */
  1203. if (self->RxDataReady > 30) {
  1204. hwreset(self);
  1205. if (irda_device_txqueue_empty(self->netdev)) {
  1206. via_ircc_dma_receive(self);
  1207. }
  1208. } else { // call this to upload frame.
  1209. RxTimerHandler(self, iobase);
  1210. }
  1211. } //RECV
  1212. } //Timer Event
  1213. if ((iHostIntType & 0x20) != 0) { //Tx Event
  1214. iTxIntType = GetTXStatus(iobase);
  1215. IRDA_DEBUG(4, "%s(): iTxIntType %02x: %s %s %s %s\n",
  1216. __FUNCTION__, iTxIntType,
  1217. (iTxIntType & 0x08) ? "FIFO underr." : "",
  1218. (iTxIntType & 0x04) ? "EOM" : "",
  1219. (iTxIntType & 0x02) ? "FIFO ready" : "",
  1220. (iTxIntType & 0x01) ? "Early EOM" : "");
  1221. if (iTxIntType & 0x4) {
  1222. self->EventFlag.EOMessage++; // read and will auto clean
  1223. if (via_ircc_dma_xmit_complete(self)) {
  1224. if (irda_device_txqueue_empty
  1225. (self->netdev)) {
  1226. via_ircc_dma_receive(self);
  1227. }
  1228. } else {
  1229. self->EventFlag.Unknown++;
  1230. }
  1231. } //EOP
  1232. } //Tx Event
  1233. //----------------------------------------
  1234. if ((iHostIntType & 0x10) != 0) { //Rx Event
  1235. /* Check if DMA has finished */
  1236. iRxIntType = GetRXStatus(iobase);
  1237. IRDA_DEBUG(4, "%s(): iRxIntType %02x: %s %s %s %s %s %s %s\n",
  1238. __FUNCTION__, iRxIntType,
  1239. (iRxIntType & 0x80) ? "PHY err." : "",
  1240. (iRxIntType & 0x40) ? "CRC err" : "",
  1241. (iRxIntType & 0x20) ? "FIFO overr." : "",
  1242. (iRxIntType & 0x10) ? "EOF" : "",
  1243. (iRxIntType & 0x08) ? "RxData" : "",
  1244. (iRxIntType & 0x02) ? "RxMaxLen" : "",
  1245. (iRxIntType & 0x01) ? "SIR bad" : "");
  1246. if (!iRxIntType)
  1247. IRDA_DEBUG(3, "%s(): RxIRQ =0\n", __FUNCTION__);
  1248. if (iRxIntType & 0x10) {
  1249. if (via_ircc_dma_receive_complete(self, iobase)) {
  1250. //F01 if(!(IsFIROn(iobase))) via_ircc_dma_receive(self);
  1251. via_ircc_dma_receive(self);
  1252. }
  1253. } // No ERR
  1254. else { //ERR
  1255. IRDA_DEBUG(4, "%s(): RxIRQ ERR:iRxIntType=%x,HostIntType=%x,CurCount=%x,RxLastCount=%x_____\n",
  1256. __FUNCTION__, iRxIntType, iHostIntType,
  1257. RxCurCount(iobase, self),
  1258. self->RxLastCount);
  1259. if (iRxIntType & 0x20) { //FIFO OverRun ERR
  1260. ResetChip(iobase, 0);
  1261. ResetChip(iobase, 1);
  1262. } else { //PHY,CRC ERR
  1263. if (iRxIntType != 0x08)
  1264. hwreset(self); //F01
  1265. }
  1266. via_ircc_dma_receive(self);
  1267. } //ERR
  1268. } //Rx Event
  1269. spin_unlock(&self->lock);
  1270. return IRQ_RETVAL(iHostIntType);
  1271. }
  1272. static void hwreset(struct via_ircc_cb *self)
  1273. {
  1274. int iobase;
  1275. iobase = self->io.fir_base;
  1276. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1277. ResetChip(iobase, 5);
  1278. EnableDMA(iobase, OFF);
  1279. EnableTX(iobase, OFF);
  1280. EnableRX(iobase, OFF);
  1281. EnRXDMA(iobase, OFF);
  1282. EnTXDMA(iobase, OFF);
  1283. RXStart(iobase, OFF);
  1284. TXStart(iobase, OFF);
  1285. InitCard(iobase);
  1286. CommonInit(iobase);
  1287. SIRFilter(iobase, ON);
  1288. SetSIR(iobase, ON);
  1289. CRC16(iobase, ON);
  1290. EnTXCRC(iobase, 0);
  1291. WriteReg(iobase, I_ST_CT_0, 0x00);
  1292. SetBaudRate(iobase, 9600);
  1293. SetPulseWidth(iobase, 12);
  1294. SetSendPreambleCount(iobase, 0);
  1295. WriteReg(iobase, I_ST_CT_0, 0x80);
  1296. /* Restore speed. */
  1297. via_ircc_change_speed(self, self->io.speed);
  1298. self->st_fifo.len = 0;
  1299. }
  1300. /*
  1301. * Function via_ircc_is_receiving (self)
  1302. *
  1303. * Return TRUE is we are currently receiving a frame
  1304. *
  1305. */
  1306. static int via_ircc_is_receiving(struct via_ircc_cb *self)
  1307. {
  1308. int status = FALSE;
  1309. int iobase;
  1310. IRDA_ASSERT(self != NULL, return FALSE;);
  1311. iobase = self->io.fir_base;
  1312. if (CkRxRecv(iobase, self))
  1313. status = TRUE;
  1314. IRDA_DEBUG(2, "%s(): status=%x....\n", __FUNCTION__, status);
  1315. return status;
  1316. }
  1317. /*
  1318. * Function via_ircc_net_open (dev)
  1319. *
  1320. * Start the device
  1321. *
  1322. */
  1323. static int via_ircc_net_open(struct net_device *dev)
  1324. {
  1325. struct via_ircc_cb *self;
  1326. int iobase;
  1327. char hwname[32];
  1328. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1329. IRDA_ASSERT(dev != NULL, return -1;);
  1330. self = (struct via_ircc_cb *) dev->priv;
  1331. self->stats.rx_packets = 0;
  1332. IRDA_ASSERT(self != NULL, return 0;);
  1333. iobase = self->io.fir_base;
  1334. if (request_irq(self->io.irq, via_ircc_interrupt, 0, dev->name, dev)) {
  1335. IRDA_WARNING("%s, unable to allocate irq=%d\n", driver_name,
  1336. self->io.irq);
  1337. return -EAGAIN;
  1338. }
  1339. /*
  1340. * Always allocate the DMA channel after the IRQ, and clean up on
  1341. * failure.
  1342. */
  1343. if (request_dma(self->io.dma, dev->name)) {
  1344. IRDA_WARNING("%s, unable to allocate dma=%d\n", driver_name,
  1345. self->io.dma);
  1346. free_irq(self->io.irq, self);
  1347. return -EAGAIN;
  1348. }
  1349. if (self->io.dma2 != self->io.dma) {
  1350. if (request_dma(self->io.dma2, dev->name)) {
  1351. IRDA_WARNING("%s, unable to allocate dma2=%d\n",
  1352. driver_name, self->io.dma2);
  1353. free_irq(self->io.irq, self);
  1354. return -EAGAIN;
  1355. }
  1356. }
  1357. /* turn on interrupts */
  1358. EnAllInt(iobase, ON);
  1359. EnInternalLoop(iobase, OFF);
  1360. EnExternalLoop(iobase, OFF);
  1361. /* */
  1362. via_ircc_dma_receive(self);
  1363. /* Ready to play! */
  1364. netif_start_queue(dev);
  1365. /*
  1366. * Open new IrLAP layer instance, now that everything should be
  1367. * initialized properly
  1368. */
  1369. sprintf(hwname, "VIA @ 0x%x", iobase);
  1370. self->irlap = irlap_open(dev, &self->qos, hwname);
  1371. self->RxLastCount = 0;
  1372. return 0;
  1373. }
  1374. /*
  1375. * Function via_ircc_net_close (dev)
  1376. *
  1377. * Stop the device
  1378. *
  1379. */
  1380. static int via_ircc_net_close(struct net_device *dev)
  1381. {
  1382. struct via_ircc_cb *self;
  1383. int iobase;
  1384. IRDA_DEBUG(3, "%s()\n", __FUNCTION__);
  1385. IRDA_ASSERT(dev != NULL, return -1;);
  1386. self = (struct via_ircc_cb *) dev->priv;
  1387. IRDA_ASSERT(self != NULL, return 0;);
  1388. /* Stop device */
  1389. netif_stop_queue(dev);
  1390. /* Stop and remove instance of IrLAP */
  1391. if (self->irlap)
  1392. irlap_close(self->irlap);
  1393. self->irlap = NULL;
  1394. iobase = self->io.fir_base;
  1395. EnTXDMA(iobase, OFF);
  1396. EnRXDMA(iobase, OFF);
  1397. DisableDmaChannel(self->io.dma);
  1398. /* Disable interrupts */
  1399. EnAllInt(iobase, OFF);
  1400. free_irq(self->io.irq, dev);
  1401. free_dma(self->io.dma);
  1402. return 0;
  1403. }
  1404. /*
  1405. * Function via_ircc_net_ioctl (dev, rq, cmd)
  1406. *
  1407. * Process IOCTL commands for this device
  1408. *
  1409. */
  1410. static int via_ircc_net_ioctl(struct net_device *dev, struct ifreq *rq,
  1411. int cmd)
  1412. {
  1413. struct if_irda_req *irq = (struct if_irda_req *) rq;
  1414. struct via_ircc_cb *self;
  1415. unsigned long flags;
  1416. int ret = 0;
  1417. IRDA_ASSERT(dev != NULL, return -1;);
  1418. self = dev->priv;
  1419. IRDA_ASSERT(self != NULL, return -1;);
  1420. IRDA_DEBUG(1, "%s(), %s, (cmd=0x%X)\n", __FUNCTION__, dev->name,
  1421. cmd);
  1422. /* Disable interrupts & save flags */
  1423. spin_lock_irqsave(&self->lock, flags);
  1424. switch (cmd) {
  1425. case SIOCSBANDWIDTH: /* Set bandwidth */
  1426. if (!capable(CAP_NET_ADMIN)) {
  1427. ret = -EPERM;
  1428. goto out;
  1429. }
  1430. via_ircc_change_speed(self, irq->ifr_baudrate);
  1431. break;
  1432. case SIOCSMEDIABUSY: /* Set media busy */
  1433. if (!capable(CAP_NET_ADMIN)) {
  1434. ret = -EPERM;
  1435. goto out;
  1436. }
  1437. irda_device_set_media_busy(self->netdev, TRUE);
  1438. break;
  1439. case SIOCGRECEIVING: /* Check if we are receiving right now */
  1440. irq->ifr_receiving = via_ircc_is_receiving(self);
  1441. break;
  1442. default:
  1443. ret = -EOPNOTSUPP;
  1444. }
  1445. out:
  1446. spin_unlock_irqrestore(&self->lock, flags);
  1447. return ret;
  1448. }
  1449. static struct net_device_stats *via_ircc_net_get_stats(struct net_device
  1450. *dev)
  1451. {
  1452. struct via_ircc_cb *self = (struct via_ircc_cb *) dev->priv;
  1453. return &self->stats;
  1454. }
  1455. MODULE_AUTHOR("VIA Technologies,inc");
  1456. MODULE_DESCRIPTION("VIA IrDA Device Driver");
  1457. MODULE_LICENSE("GPL");
  1458. module_init(via_ircc_init);
  1459. module_exit(via_ircc_cleanup);