mii-bitbang.c 8.1 KB

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  1. /*
  2. * Combined Ethernet driver for Motorola MPC8xx and MPC82xx.
  3. *
  4. * Copyright (c) 2003 Intracom S.A.
  5. * by Pantelis Antoniou <panto@intracom.gr>
  6. *
  7. * 2005 (c) MontaVista Software, Inc.
  8. * Vitaly Bordug <vbordug@ru.mvista.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public License
  11. * version 2. This program is licensed "as is" without any warranty of any
  12. * kind, whether express or implied.
  13. */
  14. #include <linux/module.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/sched.h>
  18. #include <linux/string.h>
  19. #include <linux/ptrace.h>
  20. #include <linux/errno.h>
  21. #include <linux/ioport.h>
  22. #include <linux/slab.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/pci.h>
  25. #include <linux/init.h>
  26. #include <linux/delay.h>
  27. #include <linux/netdevice.h>
  28. #include <linux/etherdevice.h>
  29. #include <linux/skbuff.h>
  30. #include <linux/spinlock.h>
  31. #include <linux/mii.h>
  32. #include <linux/ethtool.h>
  33. #include <linux/bitops.h>
  34. #include <linux/platform_device.h>
  35. #include <asm/pgtable.h>
  36. #include <asm/irq.h>
  37. #include <asm/uaccess.h>
  38. #include "fs_enet.h"
  39. static int bitbang_prep_bit(u8 **datp, u8 *mskp,
  40. struct fs_mii_bit *mii_bit)
  41. {
  42. void *dat;
  43. int adv;
  44. u8 msk;
  45. dat = (void*) mii_bit->offset;
  46. adv = mii_bit->bit >> 3;
  47. dat = (char *)dat + adv;
  48. msk = 1 << (7 - (mii_bit->bit & 7));
  49. *datp = dat;
  50. *mskp = msk;
  51. return 0;
  52. }
  53. static inline void bb_set(u8 *p, u8 m)
  54. {
  55. out_8(p, in_8(p) | m);
  56. }
  57. static inline void bb_clr(u8 *p, u8 m)
  58. {
  59. out_8(p, in_8(p) & ~m);
  60. }
  61. static inline int bb_read(u8 *p, u8 m)
  62. {
  63. return (in_8(p) & m) != 0;
  64. }
  65. static inline void mdio_active(struct bb_info *bitbang)
  66. {
  67. bb_set(bitbang->mdio_dir, bitbang->mdio_dir_msk);
  68. }
  69. static inline void mdio_tristate(struct bb_info *bitbang )
  70. {
  71. bb_clr(bitbang->mdio_dir, bitbang->mdio_dir_msk);
  72. }
  73. static inline int mdio_read(struct bb_info *bitbang )
  74. {
  75. return bb_read(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  76. }
  77. static inline void mdio(struct bb_info *bitbang , int what)
  78. {
  79. if (what)
  80. bb_set(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  81. else
  82. bb_clr(bitbang->mdio_dat, bitbang->mdio_dat_msk);
  83. }
  84. static inline void mdc(struct bb_info *bitbang , int what)
  85. {
  86. if (what)
  87. bb_set(bitbang->mdc_dat, bitbang->mdc_msk);
  88. else
  89. bb_clr(bitbang->mdc_dat, bitbang->mdc_msk);
  90. }
  91. static inline void mii_delay(struct bb_info *bitbang )
  92. {
  93. udelay(bitbang->delay);
  94. }
  95. /* Utility to send the preamble, address, and register (common to read and write). */
  96. static void bitbang_pre(struct bb_info *bitbang , int read, u8 addr, u8 reg)
  97. {
  98. int j;
  99. /*
  100. * Send a 32 bit preamble ('1's) with an extra '1' bit for good measure.
  101. * The IEEE spec says this is a PHY optional requirement. The AMD
  102. * 79C874 requires one after power up and one after a MII communications
  103. * error. This means that we are doing more preambles than we need,
  104. * but it is safer and will be much more robust.
  105. */
  106. mdio_active(bitbang);
  107. mdio(bitbang, 1);
  108. for (j = 0; j < 32; j++) {
  109. mdc(bitbang, 0);
  110. mii_delay(bitbang);
  111. mdc(bitbang, 1);
  112. mii_delay(bitbang);
  113. }
  114. /* send the start bit (01) and the read opcode (10) or write (10) */
  115. mdc(bitbang, 0);
  116. mdio(bitbang, 0);
  117. mii_delay(bitbang);
  118. mdc(bitbang, 1);
  119. mii_delay(bitbang);
  120. mdc(bitbang, 0);
  121. mdio(bitbang, 1);
  122. mii_delay(bitbang);
  123. mdc(bitbang, 1);
  124. mii_delay(bitbang);
  125. mdc(bitbang, 0);
  126. mdio(bitbang, read);
  127. mii_delay(bitbang);
  128. mdc(bitbang, 1);
  129. mii_delay(bitbang);
  130. mdc(bitbang, 0);
  131. mdio(bitbang, !read);
  132. mii_delay(bitbang);
  133. mdc(bitbang, 1);
  134. mii_delay(bitbang);
  135. /* send the PHY address */
  136. for (j = 0; j < 5; j++) {
  137. mdc(bitbang, 0);
  138. mdio(bitbang, (addr & 0x10) != 0);
  139. mii_delay(bitbang);
  140. mdc(bitbang, 1);
  141. mii_delay(bitbang);
  142. addr <<= 1;
  143. }
  144. /* send the register address */
  145. for (j = 0; j < 5; j++) {
  146. mdc(bitbang, 0);
  147. mdio(bitbang, (reg & 0x10) != 0);
  148. mii_delay(bitbang);
  149. mdc(bitbang, 1);
  150. mii_delay(bitbang);
  151. reg <<= 1;
  152. }
  153. }
  154. static int fs_enet_mii_bb_read(struct mii_bus *bus , int phy_id, int location)
  155. {
  156. u16 rdreg;
  157. int ret, j;
  158. u8 addr = phy_id & 0xff;
  159. u8 reg = location & 0xff;
  160. struct bb_info* bitbang = bus->priv;
  161. bitbang_pre(bitbang, 1, addr, reg);
  162. /* tri-state our MDIO I/O pin so we can read */
  163. mdc(bitbang, 0);
  164. mdio_tristate(bitbang);
  165. mii_delay(bitbang);
  166. mdc(bitbang, 1);
  167. mii_delay(bitbang);
  168. /* check the turnaround bit: the PHY should be driving it to zero */
  169. if (mdio_read(bitbang) != 0) {
  170. /* PHY didn't drive TA low */
  171. for (j = 0; j < 32; j++) {
  172. mdc(bitbang, 0);
  173. mii_delay(bitbang);
  174. mdc(bitbang, 1);
  175. mii_delay(bitbang);
  176. }
  177. ret = -1;
  178. goto out;
  179. }
  180. mdc(bitbang, 0);
  181. mii_delay(bitbang);
  182. /* read 16 bits of register data, MSB first */
  183. rdreg = 0;
  184. for (j = 0; j < 16; j++) {
  185. mdc(bitbang, 1);
  186. mii_delay(bitbang);
  187. rdreg <<= 1;
  188. rdreg |= mdio_read(bitbang);
  189. mdc(bitbang, 0);
  190. mii_delay(bitbang);
  191. }
  192. mdc(bitbang, 1);
  193. mii_delay(bitbang);
  194. mdc(bitbang, 0);
  195. mii_delay(bitbang);
  196. mdc(bitbang, 1);
  197. mii_delay(bitbang);
  198. ret = rdreg;
  199. out:
  200. return ret;
  201. }
  202. static int fs_enet_mii_bb_write(struct mii_bus *bus, int phy_id, int location, u16 val)
  203. {
  204. int j;
  205. struct bb_info* bitbang = bus->priv;
  206. u8 addr = phy_id & 0xff;
  207. u8 reg = location & 0xff;
  208. u16 value = val & 0xffff;
  209. bitbang_pre(bitbang, 0, addr, reg);
  210. /* send the turnaround (10) */
  211. mdc(bitbang, 0);
  212. mdio(bitbang, 1);
  213. mii_delay(bitbang);
  214. mdc(bitbang, 1);
  215. mii_delay(bitbang);
  216. mdc(bitbang, 0);
  217. mdio(bitbang, 0);
  218. mii_delay(bitbang);
  219. mdc(bitbang, 1);
  220. mii_delay(bitbang);
  221. /* write 16 bits of register data, MSB first */
  222. for (j = 0; j < 16; j++) {
  223. mdc(bitbang, 0);
  224. mdio(bitbang, (value & 0x8000) != 0);
  225. mii_delay(bitbang);
  226. mdc(bitbang, 1);
  227. mii_delay(bitbang);
  228. value <<= 1;
  229. }
  230. /*
  231. * Tri-state the MDIO line.
  232. */
  233. mdio_tristate(bitbang);
  234. mdc(bitbang, 0);
  235. mii_delay(bitbang);
  236. mdc(bitbang, 1);
  237. mii_delay(bitbang);
  238. return 0;
  239. }
  240. static int fs_enet_mii_bb_reset(struct mii_bus *bus)
  241. {
  242. /*nothing here - dunno how to reset it*/
  243. return 0;
  244. }
  245. static int fs_mii_bitbang_init(struct bb_info *bitbang, struct fs_mii_bb_platform_info* fmpi)
  246. {
  247. int r;
  248. bitbang->delay = fmpi->delay;
  249. r = bitbang_prep_bit(&bitbang->mdio_dir,
  250. &bitbang->mdio_dir_msk,
  251. &fmpi->mdio_dir);
  252. if (r != 0)
  253. return r;
  254. r = bitbang_prep_bit(&bitbang->mdio_dat,
  255. &bitbang->mdio_dat_msk,
  256. &fmpi->mdio_dat);
  257. if (r != 0)
  258. return r;
  259. r = bitbang_prep_bit(&bitbang->mdc_dat,
  260. &bitbang->mdc_msk,
  261. &fmpi->mdc_dat);
  262. if (r != 0)
  263. return r;
  264. return 0;
  265. }
  266. static int __devinit fs_enet_mdio_probe(struct device *dev)
  267. {
  268. struct platform_device *pdev = to_platform_device(dev);
  269. struct fs_mii_bb_platform_info *pdata;
  270. struct mii_bus *new_bus;
  271. struct bb_info *bitbang;
  272. int err = 0;
  273. if (NULL == dev)
  274. return -EINVAL;
  275. new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
  276. if (NULL == new_bus)
  277. return -ENOMEM;
  278. bitbang = kzalloc(sizeof(struct bb_info), GFP_KERNEL);
  279. if (NULL == bitbang)
  280. return -ENOMEM;
  281. new_bus->name = "BB MII Bus",
  282. new_bus->read = &fs_enet_mii_bb_read,
  283. new_bus->write = &fs_enet_mii_bb_write,
  284. new_bus->reset = &fs_enet_mii_bb_reset,
  285. new_bus->id = pdev->id;
  286. new_bus->phy_mask = ~0x9;
  287. pdata = (struct fs_mii_bb_platform_info *)pdev->dev.platform_data;
  288. if (NULL == pdata) {
  289. printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
  290. return -ENODEV;
  291. }
  292. /*set up workspace*/
  293. fs_mii_bitbang_init(bitbang, pdata);
  294. new_bus->priv = bitbang;
  295. new_bus->irq = pdata->irq;
  296. new_bus->dev = dev;
  297. dev_set_drvdata(dev, new_bus);
  298. err = mdiobus_register(new_bus);
  299. if (0 != err) {
  300. printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
  301. new_bus->name);
  302. goto bus_register_fail;
  303. }
  304. return 0;
  305. bus_register_fail:
  306. kfree(bitbang);
  307. kfree(new_bus);
  308. return err;
  309. }
  310. static int fs_enet_mdio_remove(struct device *dev)
  311. {
  312. struct mii_bus *bus = dev_get_drvdata(dev);
  313. mdiobus_unregister(bus);
  314. dev_set_drvdata(dev, NULL);
  315. iounmap((void *) (&bus->priv));
  316. bus->priv = NULL;
  317. kfree(bus);
  318. return 0;
  319. }
  320. static struct device_driver fs_enet_bb_mdio_driver = {
  321. .name = "fsl-bb-mdio",
  322. .bus = &platform_bus_type,
  323. .probe = fs_enet_mdio_probe,
  324. .remove = fs_enet_mdio_remove,
  325. };
  326. int fs_enet_mdio_bb_init(void)
  327. {
  328. return driver_register(&fs_enet_bb_mdio_driver);
  329. }
  330. void fs_enet_mdio_bb_exit(void)
  331. {
  332. driver_unregister(&fs_enet_bb_mdio_driver);
  333. }