fec_mii.c 10 KB

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  1. /*
  2. * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx.
  3. *
  4. * Copyright (c) 2003 Intracom S.A.
  5. * by Pantelis Antoniou <panto@intracom.gr>
  6. *
  7. * Heavily based on original FEC driver by Dan Malek <dan@embeddededge.com>
  8. * and modifications by Joakim Tjernlund <joakim.tjernlund@lumentis.se>
  9. *
  10. * Released under the GPL
  11. */
  12. #include <linux/module.h>
  13. #include <linux/types.h>
  14. #include <linux/kernel.h>
  15. #include <linux/sched.h>
  16. #include <linux/string.h>
  17. #include <linux/ptrace.h>
  18. #include <linux/errno.h>
  19. #include <linux/ioport.h>
  20. #include <linux/slab.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/pci.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/netdevice.h>
  26. #include <linux/etherdevice.h>
  27. #include <linux/skbuff.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/mii.h>
  30. #include <linux/ethtool.h>
  31. #include <linux/bitops.h>
  32. #include <asm/8xx_immap.h>
  33. #include <asm/pgtable.h>
  34. #include <asm/mpc8xx.h>
  35. #include <asm/irq.h>
  36. #include <asm/uaccess.h>
  37. #include <asm/commproc.h>
  38. /*************************************************/
  39. #include "fec_8xx.h"
  40. /*************************************************/
  41. /* Make MII read/write commands for the FEC.
  42. */
  43. #define mk_mii_read(REG) (0x60020000 | ((REG & 0x1f) << 18))
  44. #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff))
  45. #define mk_mii_end 0
  46. /*************************************************/
  47. /* XXX both FECs use the MII interface of FEC1 */
  48. static DEFINE_SPINLOCK(fec_mii_lock);
  49. #define FEC_MII_LOOPS 10000
  50. int fec_mii_read(struct net_device *dev, int phy_id, int location)
  51. {
  52. struct fec_enet_private *fep = netdev_priv(dev);
  53. fec_t *fecp;
  54. int i, ret = -1;
  55. unsigned long flags;
  56. /* XXX MII interface is only connected to FEC1 */
  57. fecp = &((immap_t *) IMAP_ADDR)->im_cpm.cp_fec;
  58. spin_lock_irqsave(&fec_mii_lock, flags);
  59. if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0) {
  60. FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  61. FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  62. FW(fecp, ievent, FEC_ENET_MII);
  63. }
  64. /* Add PHY address to register command. */
  65. FW(fecp, mii_speed, fep->fec_phy_speed);
  66. FW(fecp, mii_data, (phy_id << 23) | mk_mii_read(location));
  67. for (i = 0; i < FEC_MII_LOOPS; i++)
  68. if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
  69. break;
  70. if (i < FEC_MII_LOOPS) {
  71. FW(fecp, ievent, FEC_ENET_MII);
  72. ret = FR(fecp, mii_data) & 0xffff;
  73. }
  74. spin_unlock_irqrestore(&fec_mii_lock, flags);
  75. return ret;
  76. }
  77. void fec_mii_write(struct net_device *dev, int phy_id, int location, int value)
  78. {
  79. struct fec_enet_private *fep = netdev_priv(dev);
  80. fec_t *fecp;
  81. unsigned long flags;
  82. int i;
  83. /* XXX MII interface is only connected to FEC1 */
  84. fecp = &((immap_t *) IMAP_ADDR)->im_cpm.cp_fec;
  85. spin_lock_irqsave(&fec_mii_lock, flags);
  86. if ((FR(fecp, r_cntrl) & FEC_RCNTRL_MII_MODE) == 0) {
  87. FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE); /* MII enable */
  88. FS(fecp, ecntrl, FEC_ECNTRL_PINMUX | FEC_ECNTRL_ETHER_EN);
  89. FW(fecp, ievent, FEC_ENET_MII);
  90. }
  91. /* Add PHY address to register command. */
  92. FW(fecp, mii_speed, fep->fec_phy_speed); /* always adapt mii speed */
  93. FW(fecp, mii_data, (phy_id << 23) | mk_mii_write(location, value));
  94. for (i = 0; i < FEC_MII_LOOPS; i++)
  95. if ((FR(fecp, ievent) & FEC_ENET_MII) != 0)
  96. break;
  97. if (i < FEC_MII_LOOPS)
  98. FW(fecp, ievent, FEC_ENET_MII);
  99. spin_unlock_irqrestore(&fec_mii_lock, flags);
  100. }
  101. /*************************************************/
  102. #ifdef CONFIG_FEC_8XX_GENERIC_PHY
  103. /*
  104. * Generic PHY support.
  105. * Should work for all PHYs, but link change is detected by polling
  106. */
  107. static void generic_timer_callback(unsigned long data)
  108. {
  109. struct net_device *dev = (struct net_device *)data;
  110. struct fec_enet_private *fep = netdev_priv(dev);
  111. fep->phy_timer_list.expires = jiffies + HZ / 2;
  112. add_timer(&fep->phy_timer_list);
  113. fec_mii_link_status_change_check(dev, 0);
  114. }
  115. static void generic_startup(struct net_device *dev)
  116. {
  117. struct fec_enet_private *fep = netdev_priv(dev);
  118. fep->phy_timer_list.expires = jiffies + HZ / 2; /* every 500ms */
  119. fep->phy_timer_list.data = (unsigned long)dev;
  120. fep->phy_timer_list.function = generic_timer_callback;
  121. add_timer(&fep->phy_timer_list);
  122. }
  123. static void generic_shutdown(struct net_device *dev)
  124. {
  125. struct fec_enet_private *fep = netdev_priv(dev);
  126. del_timer_sync(&fep->phy_timer_list);
  127. }
  128. #endif
  129. #ifdef CONFIG_FEC_8XX_DM9161_PHY
  130. /* ------------------------------------------------------------------------- */
  131. /* The Davicom DM9161 is used on the NETTA board */
  132. /* register definitions */
  133. #define MII_DM9161_ACR 16 /* Aux. Config Register */
  134. #define MII_DM9161_ACSR 17 /* Aux. Config/Status Register */
  135. #define MII_DM9161_10TCSR 18 /* 10BaseT Config/Status Reg. */
  136. #define MII_DM9161_INTR 21 /* Interrupt Register */
  137. #define MII_DM9161_RECR 22 /* Receive Error Counter Reg. */
  138. #define MII_DM9161_DISCR 23 /* Disconnect Counter Register */
  139. static void dm9161_startup(struct net_device *dev)
  140. {
  141. struct fec_enet_private *fep = netdev_priv(dev);
  142. fec_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0000);
  143. }
  144. static void dm9161_ack_int(struct net_device *dev)
  145. {
  146. struct fec_enet_private *fep = netdev_priv(dev);
  147. fec_mii_read(dev, fep->mii_if.phy_id, MII_DM9161_INTR);
  148. }
  149. static void dm9161_shutdown(struct net_device *dev)
  150. {
  151. struct fec_enet_private *fep = netdev_priv(dev);
  152. fec_mii_write(dev, fep->mii_if.phy_id, MII_DM9161_INTR, 0x0f00);
  153. }
  154. #endif
  155. #ifdef CONFIG_FEC_8XX_LXT971_PHY
  156. /* Support for LXT971/972 PHY */
  157. #define MII_LXT971_PCR 16 /* Port Control Register */
  158. #define MII_LXT971_SR2 17 /* Status Register 2 */
  159. #define MII_LXT971_IER 18 /* Interrupt Enable Register */
  160. #define MII_LXT971_ISR 19 /* Interrupt Status Register */
  161. #define MII_LXT971_LCR 20 /* LED Control Register */
  162. #define MII_LXT971_TCR 30 /* Transmit Control Register */
  163. static void lxt971_startup(struct net_device *dev)
  164. {
  165. struct fec_enet_private *fep = netdev_priv(dev);
  166. fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x00F2);
  167. }
  168. static void lxt971_ack_int(struct net_device *dev)
  169. {
  170. struct fec_enet_private *fep = netdev_priv(dev);
  171. fec_mii_read(dev, fep->mii_if.phy_id, MII_LXT971_ISR);
  172. }
  173. static void lxt971_shutdown(struct net_device *dev)
  174. {
  175. struct fec_enet_private *fep = netdev_priv(dev);
  176. fec_mii_write(dev, fep->mii_if.phy_id, MII_LXT971_IER, 0x0000);
  177. }
  178. #endif
  179. /**********************************************************************************/
  180. static const struct phy_info phy_info[] = {
  181. #ifdef CONFIG_FEC_8XX_DM9161_PHY
  182. {
  183. .id = 0x00181b88,
  184. .name = "DM9161",
  185. .startup = dm9161_startup,
  186. .ack_int = dm9161_ack_int,
  187. .shutdown = dm9161_shutdown,
  188. },
  189. #endif
  190. #ifdef CONFIG_FEC_8XX_LXT971_PHY
  191. {
  192. .id = 0x0001378e,
  193. .name = "LXT971/972",
  194. .startup = lxt971_startup,
  195. .ack_int = lxt971_ack_int,
  196. .shutdown = lxt971_shutdown,
  197. },
  198. #endif
  199. #ifdef CONFIG_FEC_8XX_GENERIC_PHY
  200. {
  201. .id = 0,
  202. .name = "GENERIC",
  203. .startup = generic_startup,
  204. .shutdown = generic_shutdown,
  205. },
  206. #endif
  207. };
  208. /**********************************************************************************/
  209. int fec_mii_phy_id_detect(struct net_device *dev)
  210. {
  211. struct fec_enet_private *fep = netdev_priv(dev);
  212. const struct fec_platform_info *fpi = fep->fpi;
  213. int i, r, start, end, phytype, physubtype;
  214. const struct phy_info *phy;
  215. int phy_hwid, phy_id;
  216. /* if no MDIO */
  217. if (fpi->use_mdio == 0)
  218. return -1;
  219. phy_hwid = -1;
  220. fep->phy = NULL;
  221. /* auto-detect? */
  222. if (fpi->phy_addr == -1) {
  223. start = 0;
  224. end = 32;
  225. } else { /* direct */
  226. start = fpi->phy_addr;
  227. end = start + 1;
  228. }
  229. for (phy_id = start; phy_id < end; phy_id++) {
  230. r = fec_mii_read(dev, phy_id, MII_PHYSID1);
  231. if (r == -1 || (phytype = (r & 0xffff)) == 0xffff)
  232. continue;
  233. r = fec_mii_read(dev, phy_id, MII_PHYSID2);
  234. if (r == -1 || (physubtype = (r & 0xffff)) == 0xffff)
  235. continue;
  236. phy_hwid = (phytype << 16) | physubtype;
  237. if (phy_hwid != -1)
  238. break;
  239. }
  240. if (phy_hwid == -1) {
  241. printk(KERN_ERR DRV_MODULE_NAME
  242. ": %s No PHY detected!\n", dev->name);
  243. return -1;
  244. }
  245. for (i = 0, phy = phy_info; i < sizeof(phy_info) / sizeof(phy_info[0]);
  246. i++, phy++)
  247. if (phy->id == (phy_hwid >> 4) || phy->id == 0)
  248. break;
  249. if (i >= sizeof(phy_info) / sizeof(phy_info[0])) {
  250. printk(KERN_ERR DRV_MODULE_NAME
  251. ": %s PHY id 0x%08x is not supported!\n",
  252. dev->name, phy_hwid);
  253. return -1;
  254. }
  255. fep->phy = phy;
  256. printk(KERN_INFO DRV_MODULE_NAME
  257. ": %s Phy @ 0x%x, type %s (0x%08x)\n",
  258. dev->name, phy_id, fep->phy->name, phy_hwid);
  259. return phy_id;
  260. }
  261. void fec_mii_startup(struct net_device *dev)
  262. {
  263. struct fec_enet_private *fep = netdev_priv(dev);
  264. const struct fec_platform_info *fpi = fep->fpi;
  265. if (!fpi->use_mdio || fep->phy == NULL)
  266. return;
  267. if (fep->phy->startup == NULL)
  268. return;
  269. (*fep->phy->startup) (dev);
  270. }
  271. void fec_mii_shutdown(struct net_device *dev)
  272. {
  273. struct fec_enet_private *fep = netdev_priv(dev);
  274. const struct fec_platform_info *fpi = fep->fpi;
  275. if (!fpi->use_mdio || fep->phy == NULL)
  276. return;
  277. if (fep->phy->shutdown == NULL)
  278. return;
  279. (*fep->phy->shutdown) (dev);
  280. }
  281. void fec_mii_ack_int(struct net_device *dev)
  282. {
  283. struct fec_enet_private *fep = netdev_priv(dev);
  284. const struct fec_platform_info *fpi = fep->fpi;
  285. if (!fpi->use_mdio || fep->phy == NULL)
  286. return;
  287. if (fep->phy->ack_int == NULL)
  288. return;
  289. (*fep->phy->ack_int) (dev);
  290. }
  291. /* helper function */
  292. static int mii_negotiated(struct mii_if_info *mii)
  293. {
  294. int advert, lpa, val;
  295. if (!mii_link_ok(mii))
  296. return 0;
  297. val = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_BMSR);
  298. if ((val & BMSR_ANEGCOMPLETE) == 0)
  299. return 0;
  300. advert = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_ADVERTISE);
  301. lpa = (*mii->mdio_read) (mii->dev, mii->phy_id, MII_LPA);
  302. return mii_nway_result(advert & lpa);
  303. }
  304. void fec_mii_link_status_change_check(struct net_device *dev, int init_media)
  305. {
  306. struct fec_enet_private *fep = netdev_priv(dev);
  307. unsigned int media;
  308. unsigned long flags;
  309. if (mii_check_media(&fep->mii_if, netif_msg_link(fep), init_media) == 0)
  310. return;
  311. media = mii_negotiated(&fep->mii_if);
  312. if (netif_carrier_ok(dev)) {
  313. spin_lock_irqsave(&fep->lock, flags);
  314. fec_restart(dev, !!(media & ADVERTISE_FULL),
  315. (media & (ADVERTISE_100FULL | ADVERTISE_100HALF)) ?
  316. 100 : 10);
  317. spin_unlock_irqrestore(&fep->lock, flags);
  318. netif_start_queue(dev);
  319. } else {
  320. netif_stop_queue(dev);
  321. spin_lock_irqsave(&fep->lock, flags);
  322. fec_stop(dev);
  323. spin_unlock_irqrestore(&fep->lock, flags);
  324. }
  325. }