tifm_sd.c 25 KB

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  1. /*
  2. * tifm_sd.c - TI FlashMedia driver
  3. *
  4. * Copyright (C) 2006 Alex Dubov <oakad@yahoo.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. */
  11. #include <linux/tifm.h>
  12. #include <linux/mmc/protocol.h>
  13. #include <linux/mmc/host.h>
  14. #include <linux/highmem.h>
  15. #include <asm/io.h>
  16. #define DRIVER_NAME "tifm_sd"
  17. #define DRIVER_VERSION "0.6"
  18. static int no_dma = 0;
  19. static int fixed_timeout = 0;
  20. module_param(no_dma, bool, 0644);
  21. module_param(fixed_timeout, bool, 0644);
  22. /* Constants here are mostly from OMAP5912 datasheet */
  23. #define TIFM_MMCSD_RESET 0x0002
  24. #define TIFM_MMCSD_CLKMASK 0x03ff
  25. #define TIFM_MMCSD_POWER 0x0800
  26. #define TIFM_MMCSD_4BBUS 0x8000
  27. #define TIFM_MMCSD_RXDE 0x8000 /* rx dma enable */
  28. #define TIFM_MMCSD_TXDE 0x0080 /* tx dma enable */
  29. #define TIFM_MMCSD_BUFINT 0x0c00 /* set bits: AE, AF */
  30. #define TIFM_MMCSD_DPE 0x0020 /* data timeout counted in kilocycles */
  31. #define TIFM_MMCSD_INAB 0x0080 /* abort / initialize command */
  32. #define TIFM_MMCSD_READ 0x8000
  33. #define TIFM_MMCSD_DATAMASK 0x001d /* set bits: EOFB, BRS, CB, EOC */
  34. #define TIFM_MMCSD_ERRMASK 0x41e0 /* set bits: CERR, CCRC, CTO, DCRC, DTO */
  35. #define TIFM_MMCSD_EOC 0x0001 /* end of command phase */
  36. #define TIFM_MMCSD_CB 0x0004 /* card enter busy state */
  37. #define TIFM_MMCSD_BRS 0x0008 /* block received/sent */
  38. #define TIFM_MMCSD_EOFB 0x0010 /* card exit busy state */
  39. #define TIFM_MMCSD_DTO 0x0020 /* data time-out */
  40. #define TIFM_MMCSD_DCRC 0x0040 /* data crc error */
  41. #define TIFM_MMCSD_CTO 0x0080 /* command time-out */
  42. #define TIFM_MMCSD_CCRC 0x0100 /* command crc error */
  43. #define TIFM_MMCSD_AF 0x0400 /* fifo almost full */
  44. #define TIFM_MMCSD_AE 0x0800 /* fifo almost empty */
  45. #define TIFM_MMCSD_CERR 0x4000 /* card status error */
  46. #define TIFM_MMCSD_FIFO_SIZE 0x0020
  47. #define TIFM_MMCSD_RSP_R0 0x0000
  48. #define TIFM_MMCSD_RSP_R1 0x0100
  49. #define TIFM_MMCSD_RSP_R2 0x0200
  50. #define TIFM_MMCSD_RSP_R3 0x0300
  51. #define TIFM_MMCSD_RSP_R4 0x0400
  52. #define TIFM_MMCSD_RSP_R5 0x0500
  53. #define TIFM_MMCSD_RSP_R6 0x0600
  54. #define TIFM_MMCSD_RSP_BUSY 0x0800
  55. #define TIFM_MMCSD_CMD_BC 0x0000
  56. #define TIFM_MMCSD_CMD_BCR 0x1000
  57. #define TIFM_MMCSD_CMD_AC 0x2000
  58. #define TIFM_MMCSD_CMD_ADTC 0x3000
  59. typedef enum {
  60. IDLE = 0,
  61. CMD, /* main command ended */
  62. BRS, /* block transfer finished */
  63. SCMD, /* stop command ended */
  64. CARD, /* card left busy state */
  65. FIFO, /* FIFO operation completed (uncertain) */
  66. READY
  67. } card_state_t;
  68. enum {
  69. FIFO_RDY = 0x0001, /* hardware dependent value */
  70. HOST_REG = 0x0002,
  71. EJECT = 0x0004,
  72. EJECT_DONE = 0x0008,
  73. CARD_BUSY = 0x0010,
  74. OPENDRAIN = 0x0040, /* hardware dependent value */
  75. CARD_EVENT = 0x0100, /* hardware dependent value */
  76. CARD_RO = 0x0200, /* hardware dependent value */
  77. FIFO_EVENT = 0x10000 }; /* hardware dependent value */
  78. struct tifm_sd {
  79. struct tifm_dev *dev;
  80. unsigned int flags;
  81. card_state_t state;
  82. unsigned int clk_freq;
  83. unsigned int clk_div;
  84. unsigned long timeout_jiffies; // software timeout - 2 sec
  85. struct mmc_request *req;
  86. struct work_struct cmd_handler;
  87. struct work_struct abort_handler;
  88. wait_queue_head_t can_eject;
  89. size_t written_blocks;
  90. char *buffer;
  91. size_t buffer_size;
  92. size_t buffer_pos;
  93. };
  94. static int tifm_sd_transfer_data(struct tifm_dev *sock, struct tifm_sd *host,
  95. unsigned int host_status)
  96. {
  97. struct mmc_command *cmd = host->req->cmd;
  98. unsigned int t_val = 0, cnt = 0;
  99. if (host_status & TIFM_MMCSD_BRS) {
  100. /* in non-dma rx mode BRS fires when fifo is still not empty */
  101. if (host->buffer && (cmd->data->flags & MMC_DATA_READ)) {
  102. while (host->buffer_size > host->buffer_pos) {
  103. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  104. host->buffer[host->buffer_pos++] = t_val & 0xff;
  105. host->buffer[host->buffer_pos++] =
  106. (t_val >> 8) & 0xff;
  107. }
  108. }
  109. return 1;
  110. } else if (host->buffer) {
  111. if ((cmd->data->flags & MMC_DATA_READ) &&
  112. (host_status & TIFM_MMCSD_AF)) {
  113. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  114. t_val = readl(sock->addr + SOCK_MMCSD_DATA);
  115. if (host->buffer_size > host->buffer_pos) {
  116. host->buffer[host->buffer_pos++] =
  117. t_val & 0xff;
  118. host->buffer[host->buffer_pos++] =
  119. (t_val >> 8) & 0xff;
  120. }
  121. }
  122. } else if ((cmd->data->flags & MMC_DATA_WRITE)
  123. && (host_status & TIFM_MMCSD_AE)) {
  124. for (cnt = 0; cnt < TIFM_MMCSD_FIFO_SIZE; cnt++) {
  125. if (host->buffer_size > host->buffer_pos) {
  126. t_val = host->buffer[host->buffer_pos++] & 0x00ff;
  127. t_val |= ((host->buffer[host->buffer_pos++]) << 8)
  128. & 0xff00;
  129. writel(t_val,
  130. sock->addr + SOCK_MMCSD_DATA);
  131. }
  132. }
  133. }
  134. }
  135. return 0;
  136. }
  137. static unsigned int tifm_sd_op_flags(struct mmc_command *cmd)
  138. {
  139. unsigned int rc = 0;
  140. switch (mmc_resp_type(cmd)) {
  141. case MMC_RSP_NONE:
  142. rc |= TIFM_MMCSD_RSP_R0;
  143. break;
  144. case MMC_RSP_R1B:
  145. rc |= TIFM_MMCSD_RSP_BUSY; // deliberate fall-through
  146. case MMC_RSP_R1:
  147. rc |= TIFM_MMCSD_RSP_R1;
  148. break;
  149. case MMC_RSP_R2:
  150. rc |= TIFM_MMCSD_RSP_R2;
  151. break;
  152. case MMC_RSP_R3:
  153. rc |= TIFM_MMCSD_RSP_R3;
  154. break;
  155. case MMC_RSP_R6:
  156. rc |= TIFM_MMCSD_RSP_R6;
  157. break;
  158. default:
  159. BUG();
  160. }
  161. switch (mmc_cmd_type(cmd)) {
  162. case MMC_CMD_BC:
  163. rc |= TIFM_MMCSD_CMD_BC;
  164. break;
  165. case MMC_CMD_BCR:
  166. rc |= TIFM_MMCSD_CMD_BCR;
  167. break;
  168. case MMC_CMD_AC:
  169. rc |= TIFM_MMCSD_CMD_AC;
  170. break;
  171. case MMC_CMD_ADTC:
  172. rc |= TIFM_MMCSD_CMD_ADTC;
  173. break;
  174. default:
  175. BUG();
  176. }
  177. return rc;
  178. }
  179. static void tifm_sd_exec(struct tifm_sd *host, struct mmc_command *cmd)
  180. {
  181. struct tifm_dev *sock = host->dev;
  182. unsigned int cmd_mask = tifm_sd_op_flags(cmd) |
  183. (host->flags & OPENDRAIN);
  184. if (cmd->data && (cmd->data->flags & MMC_DATA_READ))
  185. cmd_mask |= TIFM_MMCSD_READ;
  186. dev_dbg(&sock->dev, "executing opcode 0x%x, arg: 0x%x, mask: 0x%x\n",
  187. cmd->opcode, cmd->arg, cmd_mask);
  188. writel((cmd->arg >> 16) & 0xffff, sock->addr + SOCK_MMCSD_ARG_HIGH);
  189. writel(cmd->arg & 0xffff, sock->addr + SOCK_MMCSD_ARG_LOW);
  190. writel(cmd->opcode | cmd_mask, sock->addr + SOCK_MMCSD_COMMAND);
  191. }
  192. static void tifm_sd_fetch_resp(struct mmc_command *cmd, struct tifm_dev *sock)
  193. {
  194. cmd->resp[0] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x1c) << 16)
  195. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x18);
  196. cmd->resp[1] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x14) << 16)
  197. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x10);
  198. cmd->resp[2] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x0c) << 16)
  199. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x08);
  200. cmd->resp[3] = (readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x04) << 16)
  201. | readl(sock->addr + SOCK_MMCSD_RESPONSE + 0x00);
  202. }
  203. static void tifm_sd_process_cmd(struct tifm_dev *sock, struct tifm_sd *host,
  204. unsigned int host_status)
  205. {
  206. struct mmc_command *cmd = host->req->cmd;
  207. change_state:
  208. switch (host->state) {
  209. case IDLE:
  210. return;
  211. case CMD:
  212. if (host_status & TIFM_MMCSD_EOC) {
  213. tifm_sd_fetch_resp(cmd, sock);
  214. if (cmd->data) {
  215. host->state = BRS;
  216. } else
  217. host->state = READY;
  218. goto change_state;
  219. }
  220. break;
  221. case BRS:
  222. if (tifm_sd_transfer_data(sock, host, host_status)) {
  223. if (!host->req->stop) {
  224. if (cmd->data->flags & MMC_DATA_WRITE) {
  225. host->state = CARD;
  226. } else {
  227. host->state =
  228. host->buffer ? READY : FIFO;
  229. }
  230. goto change_state;
  231. }
  232. tifm_sd_exec(host, host->req->stop);
  233. host->state = SCMD;
  234. }
  235. break;
  236. case SCMD:
  237. if (host_status & TIFM_MMCSD_EOC) {
  238. tifm_sd_fetch_resp(host->req->stop, sock);
  239. if (cmd->error) {
  240. host->state = READY;
  241. } else if (cmd->data->flags & MMC_DATA_WRITE) {
  242. host->state = CARD;
  243. } else {
  244. host->state = host->buffer ? READY : FIFO;
  245. }
  246. goto change_state;
  247. }
  248. break;
  249. case CARD:
  250. if (!(host->flags & CARD_BUSY)
  251. && (host->written_blocks == cmd->data->blocks)) {
  252. host->state = host->buffer ? READY : FIFO;
  253. goto change_state;
  254. }
  255. break;
  256. case FIFO:
  257. if (host->flags & FIFO_RDY) {
  258. host->state = READY;
  259. host->flags &= ~FIFO_RDY;
  260. goto change_state;
  261. }
  262. break;
  263. case READY:
  264. queue_work(sock->wq, &host->cmd_handler);
  265. return;
  266. }
  267. queue_delayed_work(sock->wq, &host->abort_handler,
  268. host->timeout_jiffies);
  269. }
  270. /* Called from interrupt handler */
  271. static unsigned int tifm_sd_signal_irq(struct tifm_dev *sock,
  272. unsigned int sock_irq_status)
  273. {
  274. struct tifm_sd *host;
  275. unsigned int host_status = 0, fifo_status = 0;
  276. int error_code = 0;
  277. spin_lock(&sock->lock);
  278. host = mmc_priv((struct mmc_host*)tifm_get_drvdata(sock));
  279. cancel_delayed_work(&host->abort_handler);
  280. if (sock_irq_status & FIFO_EVENT) {
  281. fifo_status = readl(sock->addr + SOCK_DMA_FIFO_STATUS);
  282. writel(fifo_status, sock->addr + SOCK_DMA_FIFO_STATUS);
  283. host->flags |= fifo_status & FIFO_RDY;
  284. }
  285. if (sock_irq_status & CARD_EVENT) {
  286. host_status = readl(sock->addr + SOCK_MMCSD_STATUS);
  287. writel(host_status, sock->addr + SOCK_MMCSD_STATUS);
  288. if (!(host->flags & HOST_REG))
  289. queue_work(sock->wq, &host->cmd_handler);
  290. if (!host->req)
  291. goto done;
  292. if (host_status & TIFM_MMCSD_ERRMASK) {
  293. if (host_status & TIFM_MMCSD_CERR)
  294. error_code = MMC_ERR_FAILED;
  295. else if (host_status &
  296. (TIFM_MMCSD_CTO | TIFM_MMCSD_DTO))
  297. error_code = MMC_ERR_TIMEOUT;
  298. else if (host_status &
  299. (TIFM_MMCSD_CCRC | TIFM_MMCSD_DCRC))
  300. error_code = MMC_ERR_BADCRC;
  301. writel(TIFM_FIFO_INT_SETALL,
  302. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  303. writel(TIFM_DMA_RESET, sock->addr + SOCK_DMA_CONTROL);
  304. if (host->req->stop) {
  305. if (host->state == SCMD) {
  306. host->req->stop->error = error_code;
  307. } else if(host->state == BRS) {
  308. host->req->cmd->error = error_code;
  309. tifm_sd_exec(host, host->req->stop);
  310. queue_delayed_work(sock->wq,
  311. &host->abort_handler,
  312. host->timeout_jiffies);
  313. host->state = SCMD;
  314. goto done;
  315. } else {
  316. host->req->cmd->error = error_code;
  317. }
  318. } else {
  319. host->req->cmd->error = error_code;
  320. }
  321. host->state = READY;
  322. }
  323. if (host_status & TIFM_MMCSD_CB)
  324. host->flags |= CARD_BUSY;
  325. if ((host_status & TIFM_MMCSD_EOFB) &&
  326. (host->flags & CARD_BUSY)) {
  327. host->written_blocks++;
  328. host->flags &= ~CARD_BUSY;
  329. }
  330. }
  331. if (host->req)
  332. tifm_sd_process_cmd(sock, host, host_status);
  333. done:
  334. dev_dbg(&sock->dev, "host_status %x, fifo_status %x\n",
  335. host_status, fifo_status);
  336. spin_unlock(&sock->lock);
  337. return sock_irq_status;
  338. }
  339. static void tifm_sd_prepare_data(struct tifm_sd *card, struct mmc_command *cmd)
  340. {
  341. struct tifm_dev *sock = card->dev;
  342. unsigned int dest_cnt;
  343. /* DMA style IO */
  344. writel(TIFM_FIFO_INT_SETALL,
  345. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  346. writel(long_log2(cmd->data->blksz) - 2,
  347. sock->addr + SOCK_FIFO_PAGE_SIZE);
  348. writel(TIFM_FIFO_ENABLE, sock->addr + SOCK_FIFO_CONTROL);
  349. writel(TIFM_FIFO_INTMASK, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  350. dest_cnt = (cmd->data->blocks) << 8;
  351. writel(sg_dma_address(cmd->data->sg), sock->addr + SOCK_DMA_ADDRESS);
  352. writel(cmd->data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  353. writel(cmd->data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  354. if (cmd->data->flags & MMC_DATA_WRITE) {
  355. writel(TIFM_MMCSD_TXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  356. writel(dest_cnt | TIFM_DMA_TX | TIFM_DMA_EN,
  357. sock->addr + SOCK_DMA_CONTROL);
  358. } else {
  359. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  360. writel(dest_cnt | TIFM_DMA_EN, sock->addr + SOCK_DMA_CONTROL);
  361. }
  362. }
  363. static void tifm_sd_set_data_timeout(struct tifm_sd *host,
  364. struct mmc_data *data)
  365. {
  366. struct tifm_dev *sock = host->dev;
  367. unsigned int data_timeout = data->timeout_clks;
  368. if (fixed_timeout)
  369. return;
  370. data_timeout += data->timeout_ns /
  371. ((1000000000 / host->clk_freq) * host->clk_div);
  372. data_timeout *= 10; // call it fudge factor for now
  373. if (data_timeout < 0xffff) {
  374. writel((~TIFM_MMCSD_DPE) &
  375. readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  376. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  377. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  378. } else {
  379. writel(TIFM_MMCSD_DPE |
  380. readl(sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG),
  381. sock->addr + SOCK_MMCSD_SDIO_MODE_CONFIG);
  382. data_timeout = (data_timeout >> 10) + 1;
  383. if(data_timeout > 0xffff)
  384. data_timeout = 0; /* set to unlimited */
  385. writel(data_timeout, sock->addr + SOCK_MMCSD_DATA_TO);
  386. }
  387. }
  388. static void tifm_sd_request(struct mmc_host *mmc, struct mmc_request *mrq)
  389. {
  390. struct tifm_sd *host = mmc_priv(mmc);
  391. struct tifm_dev *sock = host->dev;
  392. unsigned long flags;
  393. int sg_count = 0;
  394. struct mmc_data *r_data = mrq->cmd->data;
  395. spin_lock_irqsave(&sock->lock, flags);
  396. if (host->flags & EJECT) {
  397. spin_unlock_irqrestore(&sock->lock, flags);
  398. goto err_out;
  399. }
  400. if (host->req) {
  401. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  402. spin_unlock_irqrestore(&sock->lock, flags);
  403. goto err_out;
  404. }
  405. if (r_data) {
  406. tifm_sd_set_data_timeout(host, r_data);
  407. sg_count = tifm_map_sg(sock, r_data->sg, r_data->sg_len,
  408. mrq->cmd->flags & MMC_DATA_WRITE
  409. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  410. if (sg_count != 1) {
  411. printk(KERN_ERR DRIVER_NAME
  412. ": scatterlist map failed\n");
  413. spin_unlock_irqrestore(&sock->lock, flags);
  414. goto err_out;
  415. }
  416. host->written_blocks = 0;
  417. host->flags &= ~CARD_BUSY;
  418. tifm_sd_prepare_data(host, mrq->cmd);
  419. }
  420. host->req = mrq;
  421. host->state = CMD;
  422. queue_delayed_work(sock->wq, &host->abort_handler,
  423. host->timeout_jiffies);
  424. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  425. sock->addr + SOCK_CONTROL);
  426. tifm_sd_exec(host, mrq->cmd);
  427. spin_unlock_irqrestore(&sock->lock, flags);
  428. return;
  429. err_out:
  430. if (sg_count > 0)
  431. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  432. (r_data->flags & MMC_DATA_WRITE)
  433. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  434. mrq->cmd->error = MMC_ERR_TIMEOUT;
  435. mmc_request_done(mmc, mrq);
  436. }
  437. static void tifm_sd_end_cmd(void *data)
  438. {
  439. struct tifm_sd *host = data;
  440. struct tifm_dev *sock = host->dev;
  441. struct mmc_host *mmc = tifm_get_drvdata(sock);
  442. struct mmc_request *mrq;
  443. struct mmc_data *r_data = NULL;
  444. unsigned long flags;
  445. spin_lock_irqsave(&sock->lock, flags);
  446. mrq = host->req;
  447. host->req = NULL;
  448. host->state = IDLE;
  449. if (!mrq) {
  450. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  451. spin_unlock_irqrestore(&sock->lock, flags);
  452. return;
  453. }
  454. r_data = mrq->cmd->data;
  455. if (r_data) {
  456. if (r_data->flags & MMC_DATA_WRITE) {
  457. r_data->bytes_xfered = host->written_blocks *
  458. r_data->blksz;
  459. } else {
  460. r_data->bytes_xfered = r_data->blocks -
  461. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  462. r_data->bytes_xfered *= r_data->blksz;
  463. r_data->bytes_xfered += r_data->blksz -
  464. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  465. }
  466. tifm_unmap_sg(sock, r_data->sg, r_data->sg_len,
  467. (r_data->flags & MMC_DATA_WRITE)
  468. ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  469. }
  470. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  471. sock->addr + SOCK_CONTROL);
  472. spin_unlock_irqrestore(&sock->lock, flags);
  473. mmc_request_done(mmc, mrq);
  474. }
  475. static void tifm_sd_request_nodma(struct mmc_host *mmc, struct mmc_request *mrq)
  476. {
  477. struct tifm_sd *host = mmc_priv(mmc);
  478. struct tifm_dev *sock = host->dev;
  479. unsigned long flags;
  480. struct mmc_data *r_data = mrq->cmd->data;
  481. char *t_buffer = NULL;
  482. if (r_data) {
  483. t_buffer = kmap(r_data->sg->page);
  484. if (!t_buffer) {
  485. printk(KERN_ERR DRIVER_NAME ": kmap failed\n");
  486. goto err_out;
  487. }
  488. }
  489. spin_lock_irqsave(&sock->lock, flags);
  490. if (host->flags & EJECT) {
  491. spin_unlock_irqrestore(&sock->lock, flags);
  492. goto err_out;
  493. }
  494. if (host->req) {
  495. printk(KERN_ERR DRIVER_NAME ": unfinished request detected\n");
  496. spin_unlock_irqrestore(&sock->lock, flags);
  497. goto err_out;
  498. }
  499. if (r_data) {
  500. tifm_sd_set_data_timeout(host, r_data);
  501. host->buffer = t_buffer + r_data->sg->offset;
  502. host->buffer_size = mrq->cmd->data->blocks *
  503. mrq->cmd->data->blksz;
  504. writel(TIFM_MMCSD_BUFINT |
  505. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  506. sock->addr + SOCK_MMCSD_INT_ENABLE);
  507. writel(((TIFM_MMCSD_FIFO_SIZE - 1) << 8) |
  508. (TIFM_MMCSD_FIFO_SIZE - 1),
  509. sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  510. host->written_blocks = 0;
  511. host->flags &= ~CARD_BUSY;
  512. host->buffer_pos = 0;
  513. writel(r_data->blocks - 1, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  514. writel(r_data->blksz - 1, sock->addr + SOCK_MMCSD_BLOCK_LEN);
  515. }
  516. host->req = mrq;
  517. host->state = CMD;
  518. queue_delayed_work(sock->wq, &host->abort_handler,
  519. host->timeout_jiffies);
  520. writel(TIFM_CTRL_LED | readl(sock->addr + SOCK_CONTROL),
  521. sock->addr + SOCK_CONTROL);
  522. tifm_sd_exec(host, mrq->cmd);
  523. spin_unlock_irqrestore(&sock->lock, flags);
  524. return;
  525. err_out:
  526. if (t_buffer)
  527. kunmap(r_data->sg->page);
  528. mrq->cmd->error = MMC_ERR_TIMEOUT;
  529. mmc_request_done(mmc, mrq);
  530. }
  531. static void tifm_sd_end_cmd_nodma(void *data)
  532. {
  533. struct tifm_sd *host = (struct tifm_sd*)data;
  534. struct tifm_dev *sock = host->dev;
  535. struct mmc_host *mmc = tifm_get_drvdata(sock);
  536. struct mmc_request *mrq;
  537. struct mmc_data *r_data = NULL;
  538. unsigned long flags;
  539. spin_lock_irqsave(&sock->lock, flags);
  540. mrq = host->req;
  541. host->req = NULL;
  542. host->state = IDLE;
  543. if (!mrq) {
  544. printk(KERN_ERR DRIVER_NAME ": no request to complete?\n");
  545. spin_unlock_irqrestore(&sock->lock, flags);
  546. return;
  547. }
  548. r_data = mrq->cmd->data;
  549. if (r_data) {
  550. writel((~TIFM_MMCSD_BUFINT) &
  551. readl(sock->addr + SOCK_MMCSD_INT_ENABLE),
  552. sock->addr + SOCK_MMCSD_INT_ENABLE);
  553. if (r_data->flags & MMC_DATA_WRITE) {
  554. r_data->bytes_xfered = host->written_blocks *
  555. r_data->blksz;
  556. } else {
  557. r_data->bytes_xfered = r_data->blocks -
  558. readl(sock->addr + SOCK_MMCSD_NUM_BLOCKS) - 1;
  559. r_data->bytes_xfered *= r_data->blksz;
  560. r_data->bytes_xfered += r_data->blksz -
  561. readl(sock->addr + SOCK_MMCSD_BLOCK_LEN) + 1;
  562. }
  563. host->buffer = NULL;
  564. host->buffer_pos = 0;
  565. host->buffer_size = 0;
  566. }
  567. writel((~TIFM_CTRL_LED) & readl(sock->addr + SOCK_CONTROL),
  568. sock->addr + SOCK_CONTROL);
  569. spin_unlock_irqrestore(&sock->lock, flags);
  570. if (r_data)
  571. kunmap(r_data->sg->page);
  572. mmc_request_done(mmc, mrq);
  573. }
  574. static void tifm_sd_abort(void *data)
  575. {
  576. printk(KERN_ERR DRIVER_NAME
  577. ": card failed to respond for a long period of time");
  578. tifm_eject(((struct tifm_sd*)data)->dev);
  579. }
  580. static void tifm_sd_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  581. {
  582. struct tifm_sd *host = mmc_priv(mmc);
  583. struct tifm_dev *sock = host->dev;
  584. unsigned int clk_div1, clk_div2;
  585. unsigned long flags;
  586. spin_lock_irqsave(&sock->lock, flags);
  587. dev_dbg(&sock->dev, "Setting bus width %d, power %d\n", ios->bus_width,
  588. ios->power_mode);
  589. if (ios->bus_width == MMC_BUS_WIDTH_4) {
  590. writel(TIFM_MMCSD_4BBUS | readl(sock->addr + SOCK_MMCSD_CONFIG),
  591. sock->addr + SOCK_MMCSD_CONFIG);
  592. } else {
  593. writel((~TIFM_MMCSD_4BBUS) &
  594. readl(sock->addr + SOCK_MMCSD_CONFIG),
  595. sock->addr + SOCK_MMCSD_CONFIG);
  596. }
  597. if (ios->clock) {
  598. clk_div1 = 20000000 / ios->clock;
  599. if (!clk_div1)
  600. clk_div1 = 1;
  601. clk_div2 = 24000000 / ios->clock;
  602. if (!clk_div2)
  603. clk_div2 = 1;
  604. if ((20000000 / clk_div1) > ios->clock)
  605. clk_div1++;
  606. if ((24000000 / clk_div2) > ios->clock)
  607. clk_div2++;
  608. if ((20000000 / clk_div1) > (24000000 / clk_div2)) {
  609. host->clk_freq = 20000000;
  610. host->clk_div = clk_div1;
  611. writel((~TIFM_CTRL_FAST_CLK) &
  612. readl(sock->addr + SOCK_CONTROL),
  613. sock->addr + SOCK_CONTROL);
  614. } else {
  615. host->clk_freq = 24000000;
  616. host->clk_div = clk_div2;
  617. writel(TIFM_CTRL_FAST_CLK |
  618. readl(sock->addr + SOCK_CONTROL),
  619. sock->addr + SOCK_CONTROL);
  620. }
  621. } else {
  622. host->clk_div = 0;
  623. }
  624. host->clk_div &= TIFM_MMCSD_CLKMASK;
  625. writel(host->clk_div | ((~TIFM_MMCSD_CLKMASK) &
  626. readl(sock->addr + SOCK_MMCSD_CONFIG)),
  627. sock->addr + SOCK_MMCSD_CONFIG);
  628. if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
  629. host->flags |= OPENDRAIN;
  630. else
  631. host->flags &= ~OPENDRAIN;
  632. /* chip_select : maybe later */
  633. //vdd
  634. //power is set before probe / after remove
  635. //I believe, power_off when already marked for eject is sufficient to
  636. // allow removal.
  637. if ((host->flags & EJECT) && ios->power_mode == MMC_POWER_OFF) {
  638. host->flags |= EJECT_DONE;
  639. wake_up_all(&host->can_eject);
  640. }
  641. spin_unlock_irqrestore(&sock->lock, flags);
  642. }
  643. static int tifm_sd_ro(struct mmc_host *mmc)
  644. {
  645. int rc;
  646. struct tifm_sd *host = mmc_priv(mmc);
  647. struct tifm_dev *sock = host->dev;
  648. unsigned long flags;
  649. spin_lock_irqsave(&sock->lock, flags);
  650. host->flags |= (CARD_RO & readl(sock->addr + SOCK_PRESENT_STATE));
  651. rc = (host->flags & CARD_RO) ? 1 : 0;
  652. spin_unlock_irqrestore(&sock->lock, flags);
  653. return rc;
  654. }
  655. static struct mmc_host_ops tifm_sd_ops = {
  656. .request = tifm_sd_request,
  657. .set_ios = tifm_sd_ios,
  658. .get_ro = tifm_sd_ro
  659. };
  660. static void tifm_sd_register_host(void *data)
  661. {
  662. struct tifm_sd *host = (struct tifm_sd*)data;
  663. struct tifm_dev *sock = host->dev;
  664. struct mmc_host *mmc = tifm_get_drvdata(sock);
  665. unsigned long flags;
  666. spin_lock_irqsave(&sock->lock, flags);
  667. host->flags |= HOST_REG;
  668. PREPARE_WORK(&host->cmd_handler,
  669. no_dma ? tifm_sd_end_cmd_nodma : tifm_sd_end_cmd,
  670. data);
  671. spin_unlock_irqrestore(&sock->lock, flags);
  672. dev_dbg(&sock->dev, "adding host\n");
  673. mmc_add_host(mmc);
  674. }
  675. static int tifm_sd_probe(struct tifm_dev *sock)
  676. {
  677. struct mmc_host *mmc;
  678. struct tifm_sd *host;
  679. int rc = -EIO;
  680. if (!(TIFM_SOCK_STATE_OCCUPIED &
  681. readl(sock->addr + SOCK_PRESENT_STATE))) {
  682. printk(KERN_WARNING DRIVER_NAME ": card gone, unexpectedly\n");
  683. return rc;
  684. }
  685. mmc = mmc_alloc_host(sizeof(struct tifm_sd), &sock->dev);
  686. if (!mmc)
  687. return -ENOMEM;
  688. host = mmc_priv(mmc);
  689. host->dev = sock;
  690. host->clk_div = 61;
  691. init_waitqueue_head(&host->can_eject);
  692. INIT_WORK(&host->cmd_handler, tifm_sd_register_host, host);
  693. INIT_WORK(&host->abort_handler, tifm_sd_abort, host);
  694. tifm_set_drvdata(sock, mmc);
  695. sock->signal_irq = tifm_sd_signal_irq;
  696. host->clk_freq = 20000000;
  697. host->timeout_jiffies = msecs_to_jiffies(1000);
  698. tifm_sd_ops.request = no_dma ? tifm_sd_request_nodma : tifm_sd_request;
  699. mmc->ops = &tifm_sd_ops;
  700. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  701. mmc->caps = MMC_CAP_4_BIT_DATA;
  702. mmc->f_min = 20000000 / 60;
  703. mmc->f_max = 24000000;
  704. mmc->max_hw_segs = 1;
  705. mmc->max_phys_segs = 1;
  706. mmc->max_sectors = 127;
  707. mmc->max_seg_size = mmc->max_sectors << 11; //2k maximum hw block length
  708. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  709. writel(TIFM_MMCSD_RESET, sock->addr + SOCK_MMCSD_SYSTEM_CONTROL);
  710. writel(host->clk_div | TIFM_MMCSD_POWER,
  711. sock->addr + SOCK_MMCSD_CONFIG);
  712. for (rc = 0; rc < 50; rc++) {
  713. /* Wait for reset ack */
  714. if (1 & readl(sock->addr + SOCK_MMCSD_SYSTEM_STATUS)) {
  715. rc = 0;
  716. break;
  717. }
  718. msleep(10);
  719. }
  720. if (rc) {
  721. printk(KERN_ERR DRIVER_NAME
  722. ": card not ready - probe failed\n");
  723. mmc_free_host(mmc);
  724. return -ENODEV;
  725. }
  726. writel(0, sock->addr + SOCK_MMCSD_NUM_BLOCKS);
  727. writel(host->clk_div | TIFM_MMCSD_POWER,
  728. sock->addr + SOCK_MMCSD_CONFIG);
  729. writel(TIFM_MMCSD_RXDE, sock->addr + SOCK_MMCSD_BUFFER_CONFIG);
  730. writel(TIFM_MMCSD_DATAMASK | TIFM_MMCSD_ERRMASK,
  731. sock->addr + SOCK_MMCSD_INT_ENABLE);
  732. writel(64, sock->addr + SOCK_MMCSD_COMMAND_TO); // command timeout 64 clocks for now
  733. writel(TIFM_MMCSD_INAB, sock->addr + SOCK_MMCSD_COMMAND);
  734. writel(host->clk_div | TIFM_MMCSD_POWER,
  735. sock->addr + SOCK_MMCSD_CONFIG);
  736. queue_delayed_work(sock->wq, &host->abort_handler,
  737. host->timeout_jiffies);
  738. return 0;
  739. }
  740. static int tifm_sd_host_is_down(struct tifm_dev *sock)
  741. {
  742. struct mmc_host *mmc = tifm_get_drvdata(sock);
  743. struct tifm_sd *host = mmc_priv(mmc);
  744. unsigned long flags;
  745. int rc = 0;
  746. spin_lock_irqsave(&sock->lock, flags);
  747. rc = (host->flags & EJECT_DONE);
  748. spin_unlock_irqrestore(&sock->lock, flags);
  749. return rc;
  750. }
  751. static void tifm_sd_remove(struct tifm_dev *sock)
  752. {
  753. struct mmc_host *mmc = tifm_get_drvdata(sock);
  754. struct tifm_sd *host = mmc_priv(mmc);
  755. unsigned long flags;
  756. spin_lock_irqsave(&sock->lock, flags);
  757. host->flags |= EJECT;
  758. if (host->req)
  759. queue_work(sock->wq, &host->cmd_handler);
  760. spin_unlock_irqrestore(&sock->lock, flags);
  761. wait_event_timeout(host->can_eject, tifm_sd_host_is_down(sock),
  762. host->timeout_jiffies);
  763. if (host->flags & HOST_REG)
  764. mmc_remove_host(mmc);
  765. /* The meaning of the bit majority in this constant is unknown. */
  766. writel(0xfff8 & readl(sock->addr + SOCK_CONTROL),
  767. sock->addr + SOCK_CONTROL);
  768. writel(0, sock->addr + SOCK_MMCSD_INT_ENABLE);
  769. writel(TIFM_FIFO_INT_SETALL,
  770. sock->addr + SOCK_DMA_FIFO_INT_ENABLE_CLEAR);
  771. writel(0, sock->addr + SOCK_DMA_FIFO_INT_ENABLE_SET);
  772. tifm_set_drvdata(sock, NULL);
  773. mmc_free_host(mmc);
  774. }
  775. static tifm_media_id tifm_sd_id_tbl[] = {
  776. FM_SD, 0
  777. };
  778. static struct tifm_driver tifm_sd_driver = {
  779. .driver = {
  780. .name = DRIVER_NAME,
  781. .owner = THIS_MODULE
  782. },
  783. .id_table = tifm_sd_id_tbl,
  784. .probe = tifm_sd_probe,
  785. .remove = tifm_sd_remove
  786. };
  787. static int __init tifm_sd_init(void)
  788. {
  789. return tifm_register_driver(&tifm_sd_driver);
  790. }
  791. static void __exit tifm_sd_exit(void)
  792. {
  793. tifm_unregister_driver(&tifm_sd_driver);
  794. }
  795. MODULE_AUTHOR("Alex Dubov");
  796. MODULE_DESCRIPTION("TI FlashMedia SD driver");
  797. MODULE_LICENSE("GPL");
  798. MODULE_DEVICE_TABLE(tifm, tifm_sd_id_tbl);
  799. MODULE_VERSION(DRIVER_VERSION);
  800. module_init(tifm_sd_init);
  801. module_exit(tifm_sd_exit);