sdhci.c 37 KB

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  1. /*
  2. * linux/drivers/mmc/sdhci.c - Secure Digital Host Controller Interface driver
  3. *
  4. * Copyright (C) 2005-2006 Pierre Ossman, All Rights Reserved.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or (at
  9. * your option) any later version.
  10. */
  11. #include <linux/delay.h>
  12. #include <linux/highmem.h>
  13. #include <linux/pci.h>
  14. #include <linux/dma-mapping.h>
  15. #include <linux/mmc/host.h>
  16. #include <linux/mmc/protocol.h>
  17. #include <asm/scatterlist.h>
  18. #include "sdhci.h"
  19. #define DRIVER_NAME "sdhci"
  20. #define DRIVER_VERSION "0.12"
  21. #define BUGMAIL "<sdhci-devel@list.drzeus.cx>"
  22. #define DBG(f, x...) \
  23. pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  24. static unsigned int debug_nodma = 0;
  25. static unsigned int debug_forcedma = 0;
  26. static unsigned int debug_quirks = 0;
  27. #define SDHCI_QUIRK_CLOCK_BEFORE_RESET (1<<0)
  28. #define SDHCI_QUIRK_FORCE_DMA (1<<1)
  29. /* Controller doesn't like some resets when there is no card inserted. */
  30. #define SDHCI_QUIRK_NO_CARD_NO_RESET (1<<2)
  31. static const struct pci_device_id pci_ids[] __devinitdata = {
  32. {
  33. .vendor = PCI_VENDOR_ID_RICOH,
  34. .device = PCI_DEVICE_ID_RICOH_R5C822,
  35. .subvendor = PCI_VENDOR_ID_IBM,
  36. .subdevice = PCI_ANY_ID,
  37. .driver_data = SDHCI_QUIRK_CLOCK_BEFORE_RESET |
  38. SDHCI_QUIRK_FORCE_DMA,
  39. },
  40. {
  41. .vendor = PCI_VENDOR_ID_RICOH,
  42. .device = PCI_DEVICE_ID_RICOH_R5C822,
  43. .subvendor = PCI_ANY_ID,
  44. .subdevice = PCI_ANY_ID,
  45. .driver_data = SDHCI_QUIRK_FORCE_DMA |
  46. SDHCI_QUIRK_NO_CARD_NO_RESET,
  47. },
  48. {
  49. .vendor = PCI_VENDOR_ID_TI,
  50. .device = PCI_DEVICE_ID_TI_XX21_XX11_SD,
  51. .subvendor = PCI_ANY_ID,
  52. .subdevice = PCI_ANY_ID,
  53. .driver_data = SDHCI_QUIRK_FORCE_DMA,
  54. },
  55. { /* Generic SD host controller */
  56. PCI_DEVICE_CLASS((PCI_CLASS_SYSTEM_SDHCI << 8), 0xFFFF00)
  57. },
  58. { /* end: all zeroes */ },
  59. };
  60. MODULE_DEVICE_TABLE(pci, pci_ids);
  61. static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
  62. static void sdhci_finish_data(struct sdhci_host *);
  63. static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
  64. static void sdhci_finish_command(struct sdhci_host *);
  65. static void sdhci_dumpregs(struct sdhci_host *host)
  66. {
  67. printk(KERN_DEBUG DRIVER_NAME ": ============== REGISTER DUMP ==============\n");
  68. printk(KERN_DEBUG DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
  69. readl(host->ioaddr + SDHCI_DMA_ADDRESS),
  70. readw(host->ioaddr + SDHCI_HOST_VERSION));
  71. printk(KERN_DEBUG DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
  72. readw(host->ioaddr + SDHCI_BLOCK_SIZE),
  73. readw(host->ioaddr + SDHCI_BLOCK_COUNT));
  74. printk(KERN_DEBUG DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  75. readl(host->ioaddr + SDHCI_ARGUMENT),
  76. readw(host->ioaddr + SDHCI_TRANSFER_MODE));
  77. printk(KERN_DEBUG DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
  78. readl(host->ioaddr + SDHCI_PRESENT_STATE),
  79. readb(host->ioaddr + SDHCI_HOST_CONTROL));
  80. printk(KERN_DEBUG DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
  81. readb(host->ioaddr + SDHCI_POWER_CONTROL),
  82. readb(host->ioaddr + SDHCI_BLOCK_GAP_CONTROL));
  83. printk(KERN_DEBUG DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
  84. readb(host->ioaddr + SDHCI_WALK_UP_CONTROL),
  85. readw(host->ioaddr + SDHCI_CLOCK_CONTROL));
  86. printk(KERN_DEBUG DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
  87. readb(host->ioaddr + SDHCI_TIMEOUT_CONTROL),
  88. readl(host->ioaddr + SDHCI_INT_STATUS));
  89. printk(KERN_DEBUG DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
  90. readl(host->ioaddr + SDHCI_INT_ENABLE),
  91. readl(host->ioaddr + SDHCI_SIGNAL_ENABLE));
  92. printk(KERN_DEBUG DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
  93. readw(host->ioaddr + SDHCI_ACMD12_ERR),
  94. readw(host->ioaddr + SDHCI_SLOT_INT_STATUS));
  95. printk(KERN_DEBUG DRIVER_NAME ": Caps: 0x%08x | Max curr: 0x%08x\n",
  96. readl(host->ioaddr + SDHCI_CAPABILITIES),
  97. readl(host->ioaddr + SDHCI_MAX_CURRENT));
  98. printk(KERN_DEBUG DRIVER_NAME ": ===========================================\n");
  99. }
  100. /*****************************************************************************\
  101. * *
  102. * Low level functions *
  103. * *
  104. \*****************************************************************************/
  105. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  106. {
  107. unsigned long timeout;
  108. if (host->chip->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
  109. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
  110. SDHCI_CARD_PRESENT))
  111. return;
  112. }
  113. writeb(mask, host->ioaddr + SDHCI_SOFTWARE_RESET);
  114. if (mask & SDHCI_RESET_ALL)
  115. host->clock = 0;
  116. /* Wait max 100 ms */
  117. timeout = 100;
  118. /* hw clears the bit when it's done */
  119. while (readb(host->ioaddr + SDHCI_SOFTWARE_RESET) & mask) {
  120. if (timeout == 0) {
  121. printk(KERN_ERR "%s: Reset 0x%x never completed. "
  122. "Please report this to " BUGMAIL ".\n",
  123. mmc_hostname(host->mmc), (int)mask);
  124. sdhci_dumpregs(host);
  125. return;
  126. }
  127. timeout--;
  128. mdelay(1);
  129. }
  130. }
  131. static void sdhci_init(struct sdhci_host *host)
  132. {
  133. u32 intmask;
  134. sdhci_reset(host, SDHCI_RESET_ALL);
  135. intmask = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
  136. SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_INDEX |
  137. SDHCI_INT_END_BIT | SDHCI_INT_CRC | SDHCI_INT_TIMEOUT |
  138. SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT |
  139. SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL |
  140. SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE;
  141. writel(intmask, host->ioaddr + SDHCI_INT_ENABLE);
  142. writel(intmask, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  143. }
  144. static void sdhci_activate_led(struct sdhci_host *host)
  145. {
  146. u8 ctrl;
  147. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  148. ctrl |= SDHCI_CTRL_LED;
  149. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  150. }
  151. static void sdhci_deactivate_led(struct sdhci_host *host)
  152. {
  153. u8 ctrl;
  154. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  155. ctrl &= ~SDHCI_CTRL_LED;
  156. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  157. }
  158. /*****************************************************************************\
  159. * *
  160. * Core functions *
  161. * *
  162. \*****************************************************************************/
  163. static inline char* sdhci_kmap_sg(struct sdhci_host* host)
  164. {
  165. host->mapped_sg = kmap_atomic(host->cur_sg->page, KM_BIO_SRC_IRQ);
  166. return host->mapped_sg + host->cur_sg->offset;
  167. }
  168. static inline void sdhci_kunmap_sg(struct sdhci_host* host)
  169. {
  170. kunmap_atomic(host->mapped_sg, KM_BIO_SRC_IRQ);
  171. }
  172. static inline int sdhci_next_sg(struct sdhci_host* host)
  173. {
  174. /*
  175. * Skip to next SG entry.
  176. */
  177. host->cur_sg++;
  178. host->num_sg--;
  179. /*
  180. * Any entries left?
  181. */
  182. if (host->num_sg > 0) {
  183. host->offset = 0;
  184. host->remain = host->cur_sg->length;
  185. }
  186. return host->num_sg;
  187. }
  188. static void sdhci_read_block_pio(struct sdhci_host *host)
  189. {
  190. int blksize, chunk_remain;
  191. u32 data;
  192. char *buffer;
  193. int size;
  194. DBG("PIO reading\n");
  195. blksize = host->data->blksz;
  196. chunk_remain = 0;
  197. data = 0;
  198. buffer = sdhci_kmap_sg(host) + host->offset;
  199. while (blksize) {
  200. if (chunk_remain == 0) {
  201. data = readl(host->ioaddr + SDHCI_BUFFER);
  202. chunk_remain = min(blksize, 4);
  203. }
  204. size = min(host->size, host->remain);
  205. size = min(size, chunk_remain);
  206. chunk_remain -= size;
  207. blksize -= size;
  208. host->offset += size;
  209. host->remain -= size;
  210. host->size -= size;
  211. while (size) {
  212. *buffer = data & 0xFF;
  213. buffer++;
  214. data >>= 8;
  215. size--;
  216. }
  217. if (host->remain == 0) {
  218. sdhci_kunmap_sg(host);
  219. if (sdhci_next_sg(host) == 0) {
  220. BUG_ON(blksize != 0);
  221. return;
  222. }
  223. buffer = sdhci_kmap_sg(host);
  224. }
  225. }
  226. sdhci_kunmap_sg(host);
  227. }
  228. static void sdhci_write_block_pio(struct sdhci_host *host)
  229. {
  230. int blksize, chunk_remain;
  231. u32 data;
  232. char *buffer;
  233. int bytes, size;
  234. DBG("PIO writing\n");
  235. blksize = host->data->blksz;
  236. chunk_remain = 4;
  237. data = 0;
  238. bytes = 0;
  239. buffer = sdhci_kmap_sg(host) + host->offset;
  240. while (blksize) {
  241. size = min(host->size, host->remain);
  242. size = min(size, chunk_remain);
  243. chunk_remain -= size;
  244. blksize -= size;
  245. host->offset += size;
  246. host->remain -= size;
  247. host->size -= size;
  248. while (size) {
  249. data >>= 8;
  250. data |= (u32)*buffer << 24;
  251. buffer++;
  252. size--;
  253. }
  254. if (chunk_remain == 0) {
  255. writel(data, host->ioaddr + SDHCI_BUFFER);
  256. chunk_remain = min(blksize, 4);
  257. }
  258. if (host->remain == 0) {
  259. sdhci_kunmap_sg(host);
  260. if (sdhci_next_sg(host) == 0) {
  261. BUG_ON(blksize != 0);
  262. return;
  263. }
  264. buffer = sdhci_kmap_sg(host);
  265. }
  266. }
  267. sdhci_kunmap_sg(host);
  268. }
  269. static void sdhci_transfer_pio(struct sdhci_host *host)
  270. {
  271. u32 mask;
  272. BUG_ON(!host->data);
  273. if (host->size == 0)
  274. return;
  275. if (host->data->flags & MMC_DATA_READ)
  276. mask = SDHCI_DATA_AVAILABLE;
  277. else
  278. mask = SDHCI_SPACE_AVAILABLE;
  279. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  280. if (host->data->flags & MMC_DATA_READ)
  281. sdhci_read_block_pio(host);
  282. else
  283. sdhci_write_block_pio(host);
  284. if (host->size == 0)
  285. break;
  286. BUG_ON(host->num_sg == 0);
  287. }
  288. DBG("PIO transfer complete.\n");
  289. }
  290. static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
  291. {
  292. u8 count;
  293. unsigned target_timeout, current_timeout;
  294. WARN_ON(host->data);
  295. if (data == NULL)
  296. return;
  297. DBG("blksz %04x blks %04x flags %08x\n",
  298. data->blksz, data->blocks, data->flags);
  299. DBG("tsac %d ms nsac %d clk\n",
  300. data->timeout_ns / 1000000, data->timeout_clks);
  301. /* Sanity checks */
  302. BUG_ON(data->blksz * data->blocks > 524288);
  303. BUG_ON(data->blksz > host->max_block);
  304. BUG_ON(data->blocks > 65535);
  305. /* timeout in us */
  306. target_timeout = data->timeout_ns / 1000 +
  307. data->timeout_clks / host->clock;
  308. /*
  309. * Figure out needed cycles.
  310. * We do this in steps in order to fit inside a 32 bit int.
  311. * The first step is the minimum timeout, which will have a
  312. * minimum resolution of 6 bits:
  313. * (1) 2^13*1000 > 2^22,
  314. * (2) host->timeout_clk < 2^16
  315. * =>
  316. * (1) / (2) > 2^6
  317. */
  318. count = 0;
  319. current_timeout = (1 << 13) * 1000 / host->timeout_clk;
  320. while (current_timeout < target_timeout) {
  321. count++;
  322. current_timeout <<= 1;
  323. if (count >= 0xF)
  324. break;
  325. }
  326. if (count >= 0xF) {
  327. printk(KERN_WARNING "%s: Too large timeout requested!\n",
  328. mmc_hostname(host->mmc));
  329. count = 0xE;
  330. }
  331. writeb(count, host->ioaddr + SDHCI_TIMEOUT_CONTROL);
  332. if (host->flags & SDHCI_USE_DMA) {
  333. int count;
  334. count = pci_map_sg(host->chip->pdev, data->sg, data->sg_len,
  335. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  336. BUG_ON(count != 1);
  337. writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
  338. } else {
  339. host->size = data->blksz * data->blocks;
  340. host->cur_sg = data->sg;
  341. host->num_sg = data->sg_len;
  342. host->offset = 0;
  343. host->remain = host->cur_sg->length;
  344. }
  345. /* We do not handle DMA boundaries, so set it to max (512 KiB) */
  346. writew(SDHCI_MAKE_BLKSZ(7, data->blksz),
  347. host->ioaddr + SDHCI_BLOCK_SIZE);
  348. writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
  349. }
  350. static void sdhci_set_transfer_mode(struct sdhci_host *host,
  351. struct mmc_data *data)
  352. {
  353. u16 mode;
  354. WARN_ON(host->data);
  355. if (data == NULL)
  356. return;
  357. mode = SDHCI_TRNS_BLK_CNT_EN;
  358. if (data->blocks > 1)
  359. mode |= SDHCI_TRNS_MULTI;
  360. if (data->flags & MMC_DATA_READ)
  361. mode |= SDHCI_TRNS_READ;
  362. if (host->flags & SDHCI_USE_DMA)
  363. mode |= SDHCI_TRNS_DMA;
  364. writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
  365. }
  366. static void sdhci_finish_data(struct sdhci_host *host)
  367. {
  368. struct mmc_data *data;
  369. u16 blocks;
  370. BUG_ON(!host->data);
  371. data = host->data;
  372. host->data = NULL;
  373. if (host->flags & SDHCI_USE_DMA) {
  374. pci_unmap_sg(host->chip->pdev, data->sg, data->sg_len,
  375. (data->flags & MMC_DATA_READ)?PCI_DMA_FROMDEVICE:PCI_DMA_TODEVICE);
  376. }
  377. /*
  378. * Controller doesn't count down when in single block mode.
  379. */
  380. if ((data->blocks == 1) && (data->error == MMC_ERR_NONE))
  381. blocks = 0;
  382. else
  383. blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
  384. data->bytes_xfered = data->blksz * (data->blocks - blocks);
  385. if ((data->error == MMC_ERR_NONE) && blocks) {
  386. printk(KERN_ERR "%s: Controller signalled completion even "
  387. "though there were blocks left. Please report this "
  388. "to " BUGMAIL ".\n", mmc_hostname(host->mmc));
  389. data->error = MMC_ERR_FAILED;
  390. } else if (host->size != 0) {
  391. printk(KERN_ERR "%s: %d bytes were left untransferred. "
  392. "Please report this to " BUGMAIL ".\n",
  393. mmc_hostname(host->mmc), host->size);
  394. data->error = MMC_ERR_FAILED;
  395. }
  396. DBG("Ending data transfer (%d bytes)\n", data->bytes_xfered);
  397. if (data->stop) {
  398. /*
  399. * The controller needs a reset of internal state machines
  400. * upon error conditions.
  401. */
  402. if (data->error != MMC_ERR_NONE) {
  403. sdhci_reset(host, SDHCI_RESET_CMD);
  404. sdhci_reset(host, SDHCI_RESET_DATA);
  405. }
  406. sdhci_send_command(host, data->stop);
  407. } else
  408. tasklet_schedule(&host->finish_tasklet);
  409. }
  410. static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
  411. {
  412. int flags;
  413. u32 mask;
  414. unsigned long timeout;
  415. WARN_ON(host->cmd);
  416. DBG("Sending cmd (%x)\n", cmd->opcode);
  417. /* Wait max 10 ms */
  418. timeout = 10;
  419. mask = SDHCI_CMD_INHIBIT;
  420. if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
  421. mask |= SDHCI_DATA_INHIBIT;
  422. /* We shouldn't wait for data inihibit for stop commands, even
  423. though they might use busy signaling */
  424. if (host->mrq->data && (cmd == host->mrq->data->stop))
  425. mask &= ~SDHCI_DATA_INHIBIT;
  426. while (readl(host->ioaddr + SDHCI_PRESENT_STATE) & mask) {
  427. if (timeout == 0) {
  428. printk(KERN_ERR "%s: Controller never released "
  429. "inhibit bit(s). Please report this to "
  430. BUGMAIL ".\n", mmc_hostname(host->mmc));
  431. sdhci_dumpregs(host);
  432. cmd->error = MMC_ERR_FAILED;
  433. tasklet_schedule(&host->finish_tasklet);
  434. return;
  435. }
  436. timeout--;
  437. mdelay(1);
  438. }
  439. mod_timer(&host->timer, jiffies + 10 * HZ);
  440. host->cmd = cmd;
  441. sdhci_prepare_data(host, cmd->data);
  442. writel(cmd->arg, host->ioaddr + SDHCI_ARGUMENT);
  443. sdhci_set_transfer_mode(host, cmd->data);
  444. if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
  445. printk(KERN_ERR "%s: Unsupported response type! "
  446. "Please report this to " BUGMAIL ".\n",
  447. mmc_hostname(host->mmc));
  448. cmd->error = MMC_ERR_INVALID;
  449. tasklet_schedule(&host->finish_tasklet);
  450. return;
  451. }
  452. if (!(cmd->flags & MMC_RSP_PRESENT))
  453. flags = SDHCI_CMD_RESP_NONE;
  454. else if (cmd->flags & MMC_RSP_136)
  455. flags = SDHCI_CMD_RESP_LONG;
  456. else if (cmd->flags & MMC_RSP_BUSY)
  457. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  458. else
  459. flags = SDHCI_CMD_RESP_SHORT;
  460. if (cmd->flags & MMC_RSP_CRC)
  461. flags |= SDHCI_CMD_CRC;
  462. if (cmd->flags & MMC_RSP_OPCODE)
  463. flags |= SDHCI_CMD_INDEX;
  464. if (cmd->data)
  465. flags |= SDHCI_CMD_DATA;
  466. writew(SDHCI_MAKE_CMD(cmd->opcode, flags),
  467. host->ioaddr + SDHCI_COMMAND);
  468. }
  469. static void sdhci_finish_command(struct sdhci_host *host)
  470. {
  471. int i;
  472. BUG_ON(host->cmd == NULL);
  473. if (host->cmd->flags & MMC_RSP_PRESENT) {
  474. if (host->cmd->flags & MMC_RSP_136) {
  475. /* CRC is stripped so we need to do some shifting. */
  476. for (i = 0;i < 4;i++) {
  477. host->cmd->resp[i] = readl(host->ioaddr +
  478. SDHCI_RESPONSE + (3-i)*4) << 8;
  479. if (i != 3)
  480. host->cmd->resp[i] |=
  481. readb(host->ioaddr +
  482. SDHCI_RESPONSE + (3-i)*4-1);
  483. }
  484. } else {
  485. host->cmd->resp[0] = readl(host->ioaddr + SDHCI_RESPONSE);
  486. }
  487. }
  488. host->cmd->error = MMC_ERR_NONE;
  489. DBG("Ending cmd (%x)\n", host->cmd->opcode);
  490. if (host->cmd->data)
  491. host->data = host->cmd->data;
  492. else
  493. tasklet_schedule(&host->finish_tasklet);
  494. host->cmd = NULL;
  495. }
  496. static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
  497. {
  498. int div;
  499. u16 clk;
  500. unsigned long timeout;
  501. if (clock == host->clock)
  502. return;
  503. writew(0, host->ioaddr + SDHCI_CLOCK_CONTROL);
  504. if (clock == 0)
  505. goto out;
  506. for (div = 1;div < 256;div *= 2) {
  507. if ((host->max_clk / div) <= clock)
  508. break;
  509. }
  510. div >>= 1;
  511. clk = div << SDHCI_DIVIDER_SHIFT;
  512. clk |= SDHCI_CLOCK_INT_EN;
  513. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  514. /* Wait max 10 ms */
  515. timeout = 10;
  516. while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
  517. & SDHCI_CLOCK_INT_STABLE)) {
  518. if (timeout == 0) {
  519. printk(KERN_ERR "%s: Internal clock never stabilised. "
  520. "Please report this to " BUGMAIL ".\n",
  521. mmc_hostname(host->mmc));
  522. sdhci_dumpregs(host);
  523. return;
  524. }
  525. timeout--;
  526. mdelay(1);
  527. }
  528. clk |= SDHCI_CLOCK_CARD_EN;
  529. writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
  530. out:
  531. host->clock = clock;
  532. }
  533. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  534. {
  535. u8 pwr;
  536. if (host->power == power)
  537. return;
  538. writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
  539. if (power == (unsigned short)-1)
  540. goto out;
  541. pwr = SDHCI_POWER_ON;
  542. switch (power) {
  543. case MMC_VDD_170:
  544. case MMC_VDD_180:
  545. case MMC_VDD_190:
  546. pwr |= SDHCI_POWER_180;
  547. break;
  548. case MMC_VDD_290:
  549. case MMC_VDD_300:
  550. case MMC_VDD_310:
  551. pwr |= SDHCI_POWER_300;
  552. break;
  553. case MMC_VDD_320:
  554. case MMC_VDD_330:
  555. case MMC_VDD_340:
  556. pwr |= SDHCI_POWER_330;
  557. break;
  558. default:
  559. BUG();
  560. }
  561. writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
  562. out:
  563. host->power = power;
  564. }
  565. /*****************************************************************************\
  566. * *
  567. * MMC callbacks *
  568. * *
  569. \*****************************************************************************/
  570. static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  571. {
  572. struct sdhci_host *host;
  573. unsigned long flags;
  574. host = mmc_priv(mmc);
  575. spin_lock_irqsave(&host->lock, flags);
  576. WARN_ON(host->mrq != NULL);
  577. sdhci_activate_led(host);
  578. host->mrq = mrq;
  579. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  580. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  581. tasklet_schedule(&host->finish_tasklet);
  582. } else
  583. sdhci_send_command(host, mrq->cmd);
  584. mmiowb();
  585. spin_unlock_irqrestore(&host->lock, flags);
  586. }
  587. static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  588. {
  589. struct sdhci_host *host;
  590. unsigned long flags;
  591. u8 ctrl;
  592. host = mmc_priv(mmc);
  593. spin_lock_irqsave(&host->lock, flags);
  594. /*
  595. * Reset the chip on each power off.
  596. * Should clear out any weird states.
  597. */
  598. if (ios->power_mode == MMC_POWER_OFF) {
  599. writel(0, host->ioaddr + SDHCI_SIGNAL_ENABLE);
  600. sdhci_init(host);
  601. }
  602. sdhci_set_clock(host, ios->clock);
  603. if (ios->power_mode == MMC_POWER_OFF)
  604. sdhci_set_power(host, -1);
  605. else
  606. sdhci_set_power(host, ios->vdd);
  607. ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
  608. if (ios->bus_width == MMC_BUS_WIDTH_4)
  609. ctrl |= SDHCI_CTRL_4BITBUS;
  610. else
  611. ctrl &= ~SDHCI_CTRL_4BITBUS;
  612. writeb(ctrl, host->ioaddr + SDHCI_HOST_CONTROL);
  613. mmiowb();
  614. spin_unlock_irqrestore(&host->lock, flags);
  615. }
  616. static int sdhci_get_ro(struct mmc_host *mmc)
  617. {
  618. struct sdhci_host *host;
  619. unsigned long flags;
  620. int present;
  621. host = mmc_priv(mmc);
  622. spin_lock_irqsave(&host->lock, flags);
  623. present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
  624. spin_unlock_irqrestore(&host->lock, flags);
  625. return !(present & SDHCI_WRITE_PROTECT);
  626. }
  627. static struct mmc_host_ops sdhci_ops = {
  628. .request = sdhci_request,
  629. .set_ios = sdhci_set_ios,
  630. .get_ro = sdhci_get_ro,
  631. };
  632. /*****************************************************************************\
  633. * *
  634. * Tasklets *
  635. * *
  636. \*****************************************************************************/
  637. static void sdhci_tasklet_card(unsigned long param)
  638. {
  639. struct sdhci_host *host;
  640. unsigned long flags;
  641. host = (struct sdhci_host*)param;
  642. spin_lock_irqsave(&host->lock, flags);
  643. if (!(readl(host->ioaddr + SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT)) {
  644. if (host->mrq) {
  645. printk(KERN_ERR "%s: Card removed during transfer!\n",
  646. mmc_hostname(host->mmc));
  647. printk(KERN_ERR "%s: Resetting controller.\n",
  648. mmc_hostname(host->mmc));
  649. sdhci_reset(host, SDHCI_RESET_CMD);
  650. sdhci_reset(host, SDHCI_RESET_DATA);
  651. host->mrq->cmd->error = MMC_ERR_FAILED;
  652. tasklet_schedule(&host->finish_tasklet);
  653. }
  654. }
  655. spin_unlock_irqrestore(&host->lock, flags);
  656. mmc_detect_change(host->mmc, msecs_to_jiffies(500));
  657. }
  658. static void sdhci_tasklet_finish(unsigned long param)
  659. {
  660. struct sdhci_host *host;
  661. unsigned long flags;
  662. struct mmc_request *mrq;
  663. host = (struct sdhci_host*)param;
  664. spin_lock_irqsave(&host->lock, flags);
  665. del_timer(&host->timer);
  666. mrq = host->mrq;
  667. DBG("Ending request, cmd (%x)\n", mrq->cmd->opcode);
  668. /*
  669. * The controller needs a reset of internal state machines
  670. * upon error conditions.
  671. */
  672. if ((mrq->cmd->error != MMC_ERR_NONE) ||
  673. (mrq->data && ((mrq->data->error != MMC_ERR_NONE) ||
  674. (mrq->data->stop && (mrq->data->stop->error != MMC_ERR_NONE))))) {
  675. /* Some controllers need this kick or reset won't work here */
  676. if (host->chip->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) {
  677. unsigned int clock;
  678. /* This is to force an update */
  679. clock = host->clock;
  680. host->clock = 0;
  681. sdhci_set_clock(host, clock);
  682. }
  683. /* Spec says we should do both at the same time, but Ricoh
  684. controllers do not like that. */
  685. sdhci_reset(host, SDHCI_RESET_CMD);
  686. sdhci_reset(host, SDHCI_RESET_DATA);
  687. }
  688. host->mrq = NULL;
  689. host->cmd = NULL;
  690. host->data = NULL;
  691. sdhci_deactivate_led(host);
  692. mmiowb();
  693. spin_unlock_irqrestore(&host->lock, flags);
  694. mmc_request_done(host->mmc, mrq);
  695. }
  696. static void sdhci_timeout_timer(unsigned long data)
  697. {
  698. struct sdhci_host *host;
  699. unsigned long flags;
  700. host = (struct sdhci_host*)data;
  701. spin_lock_irqsave(&host->lock, flags);
  702. if (host->mrq) {
  703. printk(KERN_ERR "%s: Timeout waiting for hardware interrupt. "
  704. "Please report this to " BUGMAIL ".\n",
  705. mmc_hostname(host->mmc));
  706. sdhci_dumpregs(host);
  707. if (host->data) {
  708. host->data->error = MMC_ERR_TIMEOUT;
  709. sdhci_finish_data(host);
  710. } else {
  711. if (host->cmd)
  712. host->cmd->error = MMC_ERR_TIMEOUT;
  713. else
  714. host->mrq->cmd->error = MMC_ERR_TIMEOUT;
  715. tasklet_schedule(&host->finish_tasklet);
  716. }
  717. }
  718. mmiowb();
  719. spin_unlock_irqrestore(&host->lock, flags);
  720. }
  721. /*****************************************************************************\
  722. * *
  723. * Interrupt handling *
  724. * *
  725. \*****************************************************************************/
  726. static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
  727. {
  728. BUG_ON(intmask == 0);
  729. if (!host->cmd) {
  730. printk(KERN_ERR "%s: Got command interrupt even though no "
  731. "command operation was in progress.\n",
  732. mmc_hostname(host->mmc));
  733. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  734. mmc_hostname(host->mmc));
  735. sdhci_dumpregs(host);
  736. return;
  737. }
  738. if (intmask & SDHCI_INT_RESPONSE)
  739. sdhci_finish_command(host);
  740. else {
  741. if (intmask & SDHCI_INT_TIMEOUT)
  742. host->cmd->error = MMC_ERR_TIMEOUT;
  743. else if (intmask & SDHCI_INT_CRC)
  744. host->cmd->error = MMC_ERR_BADCRC;
  745. else if (intmask & (SDHCI_INT_END_BIT | SDHCI_INT_INDEX))
  746. host->cmd->error = MMC_ERR_FAILED;
  747. else
  748. host->cmd->error = MMC_ERR_INVALID;
  749. tasklet_schedule(&host->finish_tasklet);
  750. }
  751. }
  752. static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
  753. {
  754. BUG_ON(intmask == 0);
  755. if (!host->data) {
  756. /*
  757. * A data end interrupt is sent together with the response
  758. * for the stop command.
  759. */
  760. if (intmask & SDHCI_INT_DATA_END)
  761. return;
  762. printk(KERN_ERR "%s: Got data interrupt even though no "
  763. "data operation was in progress.\n",
  764. mmc_hostname(host->mmc));
  765. printk(KERN_ERR "%s: Please report this to " BUGMAIL ".\n",
  766. mmc_hostname(host->mmc));
  767. sdhci_dumpregs(host);
  768. return;
  769. }
  770. if (intmask & SDHCI_INT_DATA_TIMEOUT)
  771. host->data->error = MMC_ERR_TIMEOUT;
  772. else if (intmask & SDHCI_INT_DATA_CRC)
  773. host->data->error = MMC_ERR_BADCRC;
  774. else if (intmask & SDHCI_INT_DATA_END_BIT)
  775. host->data->error = MMC_ERR_FAILED;
  776. if (host->data->error != MMC_ERR_NONE)
  777. sdhci_finish_data(host);
  778. else {
  779. if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
  780. sdhci_transfer_pio(host);
  781. if (intmask & SDHCI_INT_DATA_END)
  782. sdhci_finish_data(host);
  783. }
  784. }
  785. static irqreturn_t sdhci_irq(int irq, void *dev_id)
  786. {
  787. irqreturn_t result;
  788. struct sdhci_host* host = dev_id;
  789. u32 intmask;
  790. spin_lock(&host->lock);
  791. intmask = readl(host->ioaddr + SDHCI_INT_STATUS);
  792. if (!intmask) {
  793. result = IRQ_NONE;
  794. goto out;
  795. }
  796. DBG("*** %s got interrupt: 0x%08x\n", host->slot_descr, intmask);
  797. if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
  798. writel(intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE),
  799. host->ioaddr + SDHCI_INT_STATUS);
  800. tasklet_schedule(&host->card_tasklet);
  801. }
  802. intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE);
  803. if (intmask & SDHCI_INT_CMD_MASK) {
  804. writel(intmask & SDHCI_INT_CMD_MASK,
  805. host->ioaddr + SDHCI_INT_STATUS);
  806. sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
  807. }
  808. if (intmask & SDHCI_INT_DATA_MASK) {
  809. writel(intmask & SDHCI_INT_DATA_MASK,
  810. host->ioaddr + SDHCI_INT_STATUS);
  811. sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
  812. }
  813. intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
  814. if (intmask & SDHCI_INT_BUS_POWER) {
  815. printk(KERN_ERR "%s: Card is consuming too much power!\n",
  816. mmc_hostname(host->mmc));
  817. writel(SDHCI_INT_BUS_POWER, host->ioaddr + SDHCI_INT_STATUS);
  818. }
  819. intmask &= SDHCI_INT_BUS_POWER;
  820. if (intmask) {
  821. printk(KERN_ERR "%s: Unexpected interrupt 0x%08x. Please "
  822. "report this to " BUGMAIL ".\n",
  823. mmc_hostname(host->mmc), intmask);
  824. sdhci_dumpregs(host);
  825. writel(intmask, host->ioaddr + SDHCI_INT_STATUS);
  826. }
  827. result = IRQ_HANDLED;
  828. mmiowb();
  829. out:
  830. spin_unlock(&host->lock);
  831. return result;
  832. }
  833. /*****************************************************************************\
  834. * *
  835. * Suspend/resume *
  836. * *
  837. \*****************************************************************************/
  838. #ifdef CONFIG_PM
  839. static int sdhci_suspend (struct pci_dev *pdev, pm_message_t state)
  840. {
  841. struct sdhci_chip *chip;
  842. int i, ret;
  843. chip = pci_get_drvdata(pdev);
  844. if (!chip)
  845. return 0;
  846. DBG("Suspending...\n");
  847. for (i = 0;i < chip->num_slots;i++) {
  848. if (!chip->hosts[i])
  849. continue;
  850. ret = mmc_suspend_host(chip->hosts[i]->mmc, state);
  851. if (ret) {
  852. for (i--;i >= 0;i--)
  853. mmc_resume_host(chip->hosts[i]->mmc);
  854. return ret;
  855. }
  856. }
  857. pci_save_state(pdev);
  858. pci_enable_wake(pdev, pci_choose_state(pdev, state), 0);
  859. pci_disable_device(pdev);
  860. pci_set_power_state(pdev, pci_choose_state(pdev, state));
  861. return 0;
  862. }
  863. static int sdhci_resume (struct pci_dev *pdev)
  864. {
  865. struct sdhci_chip *chip;
  866. int i, ret;
  867. chip = pci_get_drvdata(pdev);
  868. if (!chip)
  869. return 0;
  870. DBG("Resuming...\n");
  871. pci_set_power_state(pdev, PCI_D0);
  872. pci_restore_state(pdev);
  873. pci_enable_device(pdev);
  874. for (i = 0;i < chip->num_slots;i++) {
  875. if (!chip->hosts[i])
  876. continue;
  877. if (chip->hosts[i]->flags & SDHCI_USE_DMA)
  878. pci_set_master(pdev);
  879. sdhci_init(chip->hosts[i]);
  880. mmiowb();
  881. ret = mmc_resume_host(chip->hosts[i]->mmc);
  882. if (ret)
  883. return ret;
  884. }
  885. return 0;
  886. }
  887. #else /* CONFIG_PM */
  888. #define sdhci_suspend NULL
  889. #define sdhci_resume NULL
  890. #endif /* CONFIG_PM */
  891. /*****************************************************************************\
  892. * *
  893. * Device probing/removal *
  894. * *
  895. \*****************************************************************************/
  896. static int __devinit sdhci_probe_slot(struct pci_dev *pdev, int slot)
  897. {
  898. int ret;
  899. unsigned int version;
  900. struct sdhci_chip *chip;
  901. struct mmc_host *mmc;
  902. struct sdhci_host *host;
  903. u8 first_bar;
  904. unsigned int caps;
  905. chip = pci_get_drvdata(pdev);
  906. BUG_ON(!chip);
  907. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
  908. if (ret)
  909. return ret;
  910. first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
  911. if (first_bar > 5) {
  912. printk(KERN_ERR DRIVER_NAME ": Invalid first BAR. Aborting.\n");
  913. return -ENODEV;
  914. }
  915. if (!(pci_resource_flags(pdev, first_bar + slot) & IORESOURCE_MEM)) {
  916. printk(KERN_ERR DRIVER_NAME ": BAR is not iomem. Aborting.\n");
  917. return -ENODEV;
  918. }
  919. if (pci_resource_len(pdev, first_bar + slot) != 0x100) {
  920. printk(KERN_ERR DRIVER_NAME ": Invalid iomem size. Aborting.\n");
  921. return -ENODEV;
  922. }
  923. if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
  924. printk(KERN_ERR DRIVER_NAME ": Vendor specific interface. Aborting.\n");
  925. return -ENODEV;
  926. }
  927. if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
  928. printk(KERN_ERR DRIVER_NAME ": Unknown interface. Aborting.\n");
  929. return -ENODEV;
  930. }
  931. mmc = mmc_alloc_host(sizeof(struct sdhci_host), &pdev->dev);
  932. if (!mmc)
  933. return -ENOMEM;
  934. host = mmc_priv(mmc);
  935. host->mmc = mmc;
  936. host->chip = chip;
  937. chip->hosts[slot] = host;
  938. host->bar = first_bar + slot;
  939. host->addr = pci_resource_start(pdev, host->bar);
  940. host->irq = pdev->irq;
  941. DBG("slot %d at 0x%08lx, irq %d\n", slot, host->addr, host->irq);
  942. snprintf(host->slot_descr, 20, "sdhci:slot%d", slot);
  943. ret = pci_request_region(pdev, host->bar, host->slot_descr);
  944. if (ret)
  945. goto free;
  946. host->ioaddr = ioremap_nocache(host->addr,
  947. pci_resource_len(pdev, host->bar));
  948. if (!host->ioaddr) {
  949. ret = -ENOMEM;
  950. goto release;
  951. }
  952. sdhci_reset(host, SDHCI_RESET_ALL);
  953. version = readw(host->ioaddr + SDHCI_HOST_VERSION);
  954. version = (version & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
  955. if (version != 0) {
  956. printk(KERN_ERR "%s: Unknown controller version (%d). "
  957. "You may experience problems.\n", host->slot_descr,
  958. version);
  959. }
  960. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  961. if (debug_nodma)
  962. DBG("DMA forced off\n");
  963. else if (debug_forcedma) {
  964. DBG("DMA forced on\n");
  965. host->flags |= SDHCI_USE_DMA;
  966. } else if (chip->quirks & SDHCI_QUIRK_FORCE_DMA)
  967. host->flags |= SDHCI_USE_DMA;
  968. else if ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA)
  969. DBG("Controller doesn't have DMA interface\n");
  970. else if (!(caps & SDHCI_CAN_DO_DMA))
  971. DBG("Controller doesn't have DMA capability\n");
  972. else
  973. host->flags |= SDHCI_USE_DMA;
  974. if (host->flags & SDHCI_USE_DMA) {
  975. if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
  976. printk(KERN_WARNING "%s: No suitable DMA available. "
  977. "Falling back to PIO.\n", host->slot_descr);
  978. host->flags &= ~SDHCI_USE_DMA;
  979. }
  980. }
  981. if (host->flags & SDHCI_USE_DMA)
  982. pci_set_master(pdev);
  983. else /* XXX: Hack to get MMC layer to avoid highmem */
  984. pdev->dma_mask = 0;
  985. host->max_clk =
  986. (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
  987. if (host->max_clk == 0) {
  988. printk(KERN_ERR "%s: Hardware doesn't specify base clock "
  989. "frequency.\n", host->slot_descr);
  990. ret = -ENODEV;
  991. goto unmap;
  992. }
  993. host->max_clk *= 1000000;
  994. host->timeout_clk =
  995. (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
  996. if (host->timeout_clk == 0) {
  997. printk(KERN_ERR "%s: Hardware doesn't specify timeout clock "
  998. "frequency.\n", host->slot_descr);
  999. ret = -ENODEV;
  1000. goto unmap;
  1001. }
  1002. if (caps & SDHCI_TIMEOUT_CLK_UNIT)
  1003. host->timeout_clk *= 1000;
  1004. host->max_block = (caps & SDHCI_MAX_BLOCK_MASK) >> SDHCI_MAX_BLOCK_SHIFT;
  1005. if (host->max_block >= 3) {
  1006. printk(KERN_ERR "%s: Invalid maximum block size.\n",
  1007. host->slot_descr);
  1008. ret = -ENODEV;
  1009. goto unmap;
  1010. }
  1011. host->max_block = 512 << host->max_block;
  1012. /*
  1013. * Set host parameters.
  1014. */
  1015. mmc->ops = &sdhci_ops;
  1016. mmc->f_min = host->max_clk / 256;
  1017. mmc->f_max = host->max_clk;
  1018. mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_MULTIWRITE | MMC_CAP_BYTEBLOCK;
  1019. mmc->ocr_avail = 0;
  1020. if (caps & SDHCI_CAN_VDD_330)
  1021. mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
  1022. else if (caps & SDHCI_CAN_VDD_300)
  1023. mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
  1024. else if (caps & SDHCI_CAN_VDD_180)
  1025. mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
  1026. if (mmc->ocr_avail == 0) {
  1027. printk(KERN_ERR "%s: Hardware doesn't report any "
  1028. "support voltages.\n", host->slot_descr);
  1029. ret = -ENODEV;
  1030. goto unmap;
  1031. }
  1032. spin_lock_init(&host->lock);
  1033. /*
  1034. * Maximum number of segments. Hardware cannot do scatter lists.
  1035. */
  1036. if (host->flags & SDHCI_USE_DMA)
  1037. mmc->max_hw_segs = 1;
  1038. else
  1039. mmc->max_hw_segs = 16;
  1040. mmc->max_phys_segs = 16;
  1041. /*
  1042. * Maximum number of sectors in one transfer. Limited by DMA boundary
  1043. * size (512KiB), which means (512 KiB/512=) 1024 entries.
  1044. */
  1045. mmc->max_sectors = 1024;
  1046. /*
  1047. * Maximum segment size. Could be one segment with the maximum number
  1048. * of sectors.
  1049. */
  1050. mmc->max_seg_size = mmc->max_sectors * 512;
  1051. /*
  1052. * Init tasklets.
  1053. */
  1054. tasklet_init(&host->card_tasklet,
  1055. sdhci_tasklet_card, (unsigned long)host);
  1056. tasklet_init(&host->finish_tasklet,
  1057. sdhci_tasklet_finish, (unsigned long)host);
  1058. setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
  1059. ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
  1060. host->slot_descr, host);
  1061. if (ret)
  1062. goto untasklet;
  1063. sdhci_init(host);
  1064. #ifdef CONFIG_MMC_DEBUG
  1065. sdhci_dumpregs(host);
  1066. #endif
  1067. mmiowb();
  1068. mmc_add_host(mmc);
  1069. printk(KERN_INFO "%s: SDHCI at 0x%08lx irq %d %s\n", mmc_hostname(mmc),
  1070. host->addr, host->irq,
  1071. (host->flags & SDHCI_USE_DMA)?"DMA":"PIO");
  1072. return 0;
  1073. untasklet:
  1074. tasklet_kill(&host->card_tasklet);
  1075. tasklet_kill(&host->finish_tasklet);
  1076. unmap:
  1077. iounmap(host->ioaddr);
  1078. release:
  1079. pci_release_region(pdev, host->bar);
  1080. free:
  1081. mmc_free_host(mmc);
  1082. return ret;
  1083. }
  1084. static void sdhci_remove_slot(struct pci_dev *pdev, int slot)
  1085. {
  1086. struct sdhci_chip *chip;
  1087. struct mmc_host *mmc;
  1088. struct sdhci_host *host;
  1089. chip = pci_get_drvdata(pdev);
  1090. host = chip->hosts[slot];
  1091. mmc = host->mmc;
  1092. chip->hosts[slot] = NULL;
  1093. mmc_remove_host(mmc);
  1094. sdhci_reset(host, SDHCI_RESET_ALL);
  1095. free_irq(host->irq, host);
  1096. del_timer_sync(&host->timer);
  1097. tasklet_kill(&host->card_tasklet);
  1098. tasklet_kill(&host->finish_tasklet);
  1099. iounmap(host->ioaddr);
  1100. pci_release_region(pdev, host->bar);
  1101. mmc_free_host(mmc);
  1102. }
  1103. static int __devinit sdhci_probe(struct pci_dev *pdev,
  1104. const struct pci_device_id *ent)
  1105. {
  1106. int ret, i;
  1107. u8 slots, rev;
  1108. struct sdhci_chip *chip;
  1109. BUG_ON(pdev == NULL);
  1110. BUG_ON(ent == NULL);
  1111. pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
  1112. printk(KERN_INFO DRIVER_NAME
  1113. ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
  1114. pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
  1115. (int)rev);
  1116. ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
  1117. if (ret)
  1118. return ret;
  1119. slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
  1120. DBG("found %d slot(s)\n", slots);
  1121. if (slots == 0)
  1122. return -ENODEV;
  1123. ret = pci_enable_device(pdev);
  1124. if (ret)
  1125. return ret;
  1126. chip = kzalloc(sizeof(struct sdhci_chip) +
  1127. sizeof(struct sdhci_host*) * slots, GFP_KERNEL);
  1128. if (!chip) {
  1129. ret = -ENOMEM;
  1130. goto err;
  1131. }
  1132. chip->pdev = pdev;
  1133. chip->quirks = ent->driver_data;
  1134. if (debug_quirks)
  1135. chip->quirks = debug_quirks;
  1136. chip->num_slots = slots;
  1137. pci_set_drvdata(pdev, chip);
  1138. for (i = 0;i < slots;i++) {
  1139. ret = sdhci_probe_slot(pdev, i);
  1140. if (ret) {
  1141. for (i--;i >= 0;i--)
  1142. sdhci_remove_slot(pdev, i);
  1143. goto free;
  1144. }
  1145. }
  1146. return 0;
  1147. free:
  1148. pci_set_drvdata(pdev, NULL);
  1149. kfree(chip);
  1150. err:
  1151. pci_disable_device(pdev);
  1152. return ret;
  1153. }
  1154. static void __devexit sdhci_remove(struct pci_dev *pdev)
  1155. {
  1156. int i;
  1157. struct sdhci_chip *chip;
  1158. chip = pci_get_drvdata(pdev);
  1159. if (chip) {
  1160. for (i = 0;i < chip->num_slots;i++)
  1161. sdhci_remove_slot(pdev, i);
  1162. pci_set_drvdata(pdev, NULL);
  1163. kfree(chip);
  1164. }
  1165. pci_disable_device(pdev);
  1166. }
  1167. static struct pci_driver sdhci_driver = {
  1168. .name = DRIVER_NAME,
  1169. .id_table = pci_ids,
  1170. .probe = sdhci_probe,
  1171. .remove = __devexit_p(sdhci_remove),
  1172. .suspend = sdhci_suspend,
  1173. .resume = sdhci_resume,
  1174. };
  1175. /*****************************************************************************\
  1176. * *
  1177. * Driver init/exit *
  1178. * *
  1179. \*****************************************************************************/
  1180. static int __init sdhci_drv_init(void)
  1181. {
  1182. printk(KERN_INFO DRIVER_NAME
  1183. ": Secure Digital Host Controller Interface driver, "
  1184. DRIVER_VERSION "\n");
  1185. printk(KERN_INFO DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
  1186. return pci_register_driver(&sdhci_driver);
  1187. }
  1188. static void __exit sdhci_drv_exit(void)
  1189. {
  1190. DBG("Exiting\n");
  1191. pci_unregister_driver(&sdhci_driver);
  1192. }
  1193. module_init(sdhci_drv_init);
  1194. module_exit(sdhci_drv_exit);
  1195. module_param(debug_nodma, uint, 0444);
  1196. module_param(debug_forcedma, uint, 0444);
  1197. module_param(debug_quirks, uint, 0444);
  1198. MODULE_AUTHOR("Pierre Ossman <drzeus@drzeus.cx>");
  1199. MODULE_DESCRIPTION("Secure Digital Host Controller Interface driver");
  1200. MODULE_VERSION(DRIVER_VERSION);
  1201. MODULE_LICENSE("GPL");
  1202. MODULE_PARM_DESC(debug_nodma, "Forcefully disable DMA transfers. (default 0)");
  1203. MODULE_PARM_DESC(debug_forcedma, "Forcefully enable DMA transfers. (default 0)");
  1204. MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");