dibx000_common.h 3.8 KB

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  1. #ifndef DIBX000_COMMON_H
  2. #define DIBX000_COMMON_H
  3. enum dibx000_i2c_interface {
  4. DIBX000_I2C_INTERFACE_TUNER = 0,
  5. DIBX000_I2C_INTERFACE_GPIO_1_2 = 1,
  6. DIBX000_I2C_INTERFACE_GPIO_3_4 = 2
  7. };
  8. struct dibx000_i2c_master {
  9. #define DIB3000MC 1
  10. #define DIB7000 2
  11. #define DIB7000P 11
  12. #define DIB7000MC 12
  13. u16 device_rev;
  14. enum dibx000_i2c_interface selected_interface;
  15. // struct i2c_adapter tuner_i2c_adap;
  16. struct i2c_adapter gated_tuner_i2c_adap;
  17. struct i2c_adapter *i2c_adap;
  18. u8 i2c_addr;
  19. u16 base_reg;
  20. };
  21. extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst, u16 device_rev, struct i2c_adapter *i2c_adap, u8 i2c_addr);
  22. extern struct i2c_adapter * dibx000_get_i2c_adapter(struct dibx000_i2c_master *mst, enum dibx000_i2c_interface intf, int gating);
  23. extern void dibx000_exit_i2c_master(struct dibx000_i2c_master *mst);
  24. #define BAND_LBAND 0x01
  25. #define BAND_UHF 0x02
  26. #define BAND_VHF 0x04
  27. struct dibx000_agc_config {
  28. /* defines the capabilities of this AGC-setting - using the BAND_-defines*/
  29. u8 band_caps;
  30. u16 setup;
  31. u16 inv_gain;
  32. u16 time_stabiliz;
  33. u8 alpha_level;
  34. u16 thlock;
  35. u8 wbd_inv;
  36. u16 wbd_ref;
  37. u8 wbd_sel;
  38. u8 wbd_alpha;
  39. u16 agc1_max;
  40. u16 agc1_min;
  41. u16 agc2_max;
  42. u16 agc2_min;
  43. u8 agc1_pt1;
  44. u8 agc1_pt2;
  45. u8 agc1_pt3;
  46. u8 agc1_slope1;
  47. u8 agc1_slope2;
  48. u8 agc2_pt1;
  49. u8 agc2_pt2;
  50. u8 agc2_slope1;
  51. u8 agc2_slope2;
  52. u8 alpha_mant;
  53. u8 alpha_exp;
  54. u8 beta_mant;
  55. u8 beta_exp;
  56. u8 perform_agc_softsplit;
  57. struct {
  58. u16 min;
  59. u16 max;
  60. u16 min_thres;
  61. u16 max_thres;
  62. } split;
  63. };
  64. struct dibx000_bandwidth_config {
  65. u32 internal;
  66. u32 sampling;
  67. u8 pll_prediv;
  68. u8 pll_ratio;
  69. u8 pll_range;
  70. u8 pll_reset;
  71. u8 pll_bypass;
  72. u8 enable_refdiv;
  73. u8 bypclk_div;
  74. u8 IO_CLK_en_core;
  75. u8 ADClkSrc;
  76. u8 modulo;
  77. u16 sad_cfg;
  78. u32 ifreq;
  79. u32 timf;
  80. };
  81. enum dibx000_adc_states {
  82. DIBX000_SLOW_ADC_ON = 0,
  83. DIBX000_SLOW_ADC_OFF,
  84. DIBX000_ADC_ON,
  85. DIBX000_ADC_OFF,
  86. DIBX000_VBG_ENABLE,
  87. DIBX000_VBG_DISABLE,
  88. };
  89. #define BW_INDEX_TO_KHZ(v) ( (v) == BANDWIDTH_8_MHZ ? 8000 : \
  90. (v) == BANDWIDTH_7_MHZ ? 7000 : \
  91. (v) == BANDWIDTH_6_MHZ ? 6000 : 8000 )
  92. /* Chip output mode. */
  93. #define OUTMODE_HIGH_Z 0
  94. #define OUTMODE_MPEG2_PAR_GATED_CLK 1
  95. #define OUTMODE_MPEG2_PAR_CONT_CLK 2
  96. #define OUTMODE_MPEG2_SERIAL 7
  97. #define OUTMODE_DIVERSITY 4
  98. #define OUTMODE_MPEG2_FIFO 5
  99. /* I hope I can get rid of the following kludge in the near future */
  100. struct dibx000_ofdm_channel {
  101. u8 Bw;
  102. s16 nfft;
  103. s16 guard;
  104. s16 nqam;
  105. s16 vit_hrch;
  106. s16 vit_select_hp;
  107. s16 vit_alpha;
  108. s16 vit_code_rate_hp;
  109. s16 vit_code_rate_lp;
  110. };
  111. #define FEP2DIB(fep,ch) \
  112. (ch)->Bw = (fep)->u.ofdm.bandwidth; \
  113. (ch)->nfft = (fep)->u.ofdm.transmission_mode == TRANSMISSION_MODE_AUTO ? -1 : (fep)->u.ofdm.transmission_mode; \
  114. (ch)->guard = (fep)->u.ofdm.guard_interval == GUARD_INTERVAL_AUTO ? -1 : (fep)->u.ofdm.guard_interval; \
  115. (ch)->nqam = (fep)->u.ofdm.constellation == QAM_AUTO ? -1 : (fep)->u.ofdm.constellation == QAM_64 ? 2 : (fep)->u.ofdm.constellation; \
  116. (ch)->vit_hrch = 0; /* linux-dvb is not prepared for HIERARCHICAL TRANSMISSION */ \
  117. (ch)->vit_select_hp = 1; \
  118. (ch)->vit_alpha = 1; \
  119. (ch)->vit_code_rate_hp = (fep)->u.ofdm.code_rate_HP == FEC_AUTO ? -1 : (fep)->u.ofdm.code_rate_HP; \
  120. (ch)->vit_code_rate_lp = (fep)->u.ofdm.code_rate_LP == FEC_AUTO ? -1 : (fep)->u.ofdm.code_rate_LP;
  121. #define INIT_OFDM_CHANNEL(ch) do {\
  122. (ch)->Bw = 0; \
  123. (ch)->nfft = -1; \
  124. (ch)->guard = -1; \
  125. (ch)->nqam = -1; \
  126. (ch)->vit_hrch = -1; \
  127. (ch)->vit_select_hp = -1; \
  128. (ch)->vit_alpha = -1; \
  129. (ch)->vit_code_rate_hp = -1; \
  130. (ch)->vit_code_rate_lp = -1; \
  131. } while (0)
  132. #endif