ipath_verbs.c 46 KB

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  1. /*
  2. * Copyright (c) 2006 QLogic, Inc. All rights reserved.
  3. * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <rdma/ib_mad.h>
  34. #include <rdma/ib_user_verbs.h>
  35. #include <linux/io.h>
  36. #include <linux/utsname.h>
  37. #include "ipath_kernel.h"
  38. #include "ipath_verbs.h"
  39. #include "ipath_common.h"
  40. static unsigned int ib_ipath_qp_table_size = 251;
  41. module_param_named(qp_table_size, ib_ipath_qp_table_size, uint, S_IRUGO);
  42. MODULE_PARM_DESC(qp_table_size, "QP table size");
  43. unsigned int ib_ipath_lkey_table_size = 12;
  44. module_param_named(lkey_table_size, ib_ipath_lkey_table_size, uint,
  45. S_IRUGO);
  46. MODULE_PARM_DESC(lkey_table_size,
  47. "LKEY table size in bits (2^n, 1 <= n <= 23)");
  48. static unsigned int ib_ipath_max_pds = 0xFFFF;
  49. module_param_named(max_pds, ib_ipath_max_pds, uint, S_IWUSR | S_IRUGO);
  50. MODULE_PARM_DESC(max_pds,
  51. "Maximum number of protection domains to support");
  52. static unsigned int ib_ipath_max_ahs = 0xFFFF;
  53. module_param_named(max_ahs, ib_ipath_max_ahs, uint, S_IWUSR | S_IRUGO);
  54. MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
  55. unsigned int ib_ipath_max_cqes = 0x2FFFF;
  56. module_param_named(max_cqes, ib_ipath_max_cqes, uint, S_IWUSR | S_IRUGO);
  57. MODULE_PARM_DESC(max_cqes,
  58. "Maximum number of completion queue entries to support");
  59. unsigned int ib_ipath_max_cqs = 0x1FFFF;
  60. module_param_named(max_cqs, ib_ipath_max_cqs, uint, S_IWUSR | S_IRUGO);
  61. MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
  62. unsigned int ib_ipath_max_qp_wrs = 0x3FFF;
  63. module_param_named(max_qp_wrs, ib_ipath_max_qp_wrs, uint,
  64. S_IWUSR | S_IRUGO);
  65. MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
  66. unsigned int ib_ipath_max_qps = 16384;
  67. module_param_named(max_qps, ib_ipath_max_qps, uint, S_IWUSR | S_IRUGO);
  68. MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
  69. unsigned int ib_ipath_max_sges = 0x60;
  70. module_param_named(max_sges, ib_ipath_max_sges, uint, S_IWUSR | S_IRUGO);
  71. MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
  72. unsigned int ib_ipath_max_mcast_grps = 16384;
  73. module_param_named(max_mcast_grps, ib_ipath_max_mcast_grps, uint,
  74. S_IWUSR | S_IRUGO);
  75. MODULE_PARM_DESC(max_mcast_grps,
  76. "Maximum number of multicast groups to support");
  77. unsigned int ib_ipath_max_mcast_qp_attached = 16;
  78. module_param_named(max_mcast_qp_attached, ib_ipath_max_mcast_qp_attached,
  79. uint, S_IWUSR | S_IRUGO);
  80. MODULE_PARM_DESC(max_mcast_qp_attached,
  81. "Maximum number of attached QPs to support");
  82. unsigned int ib_ipath_max_srqs = 1024;
  83. module_param_named(max_srqs, ib_ipath_max_srqs, uint, S_IWUSR | S_IRUGO);
  84. MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
  85. unsigned int ib_ipath_max_srq_sges = 128;
  86. module_param_named(max_srq_sges, ib_ipath_max_srq_sges,
  87. uint, S_IWUSR | S_IRUGO);
  88. MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
  89. unsigned int ib_ipath_max_srq_wrs = 0x1FFFF;
  90. module_param_named(max_srq_wrs, ib_ipath_max_srq_wrs,
  91. uint, S_IWUSR | S_IRUGO);
  92. MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
  93. static unsigned int ib_ipath_disable_sma;
  94. module_param_named(disable_sma, ib_ipath_disable_sma, uint, S_IWUSR | S_IRUGO);
  95. MODULE_PARM_DESC(ib_ipath_disable_sma, "Disable the SMA");
  96. const int ib_ipath_state_ops[IB_QPS_ERR + 1] = {
  97. [IB_QPS_RESET] = 0,
  98. [IB_QPS_INIT] = IPATH_POST_RECV_OK,
  99. [IB_QPS_RTR] = IPATH_POST_RECV_OK | IPATH_PROCESS_RECV_OK,
  100. [IB_QPS_RTS] = IPATH_POST_RECV_OK | IPATH_PROCESS_RECV_OK |
  101. IPATH_POST_SEND_OK | IPATH_PROCESS_SEND_OK,
  102. [IB_QPS_SQD] = IPATH_POST_RECV_OK | IPATH_PROCESS_RECV_OK |
  103. IPATH_POST_SEND_OK,
  104. [IB_QPS_SQE] = IPATH_POST_RECV_OK | IPATH_PROCESS_RECV_OK,
  105. [IB_QPS_ERR] = 0,
  106. };
  107. struct ipath_ucontext {
  108. struct ib_ucontext ibucontext;
  109. };
  110. static inline struct ipath_ucontext *to_iucontext(struct ib_ucontext
  111. *ibucontext)
  112. {
  113. return container_of(ibucontext, struct ipath_ucontext, ibucontext);
  114. }
  115. /*
  116. * Translate ib_wr_opcode into ib_wc_opcode.
  117. */
  118. const enum ib_wc_opcode ib_ipath_wc_opcode[] = {
  119. [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
  120. [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
  121. [IB_WR_SEND] = IB_WC_SEND,
  122. [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
  123. [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
  124. [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
  125. [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
  126. };
  127. /*
  128. * System image GUID.
  129. */
  130. static __be64 sys_image_guid;
  131. /**
  132. * ipath_copy_sge - copy data to SGE memory
  133. * @ss: the SGE state
  134. * @data: the data to copy
  135. * @length: the length of the data
  136. */
  137. void ipath_copy_sge(struct ipath_sge_state *ss, void *data, u32 length)
  138. {
  139. struct ipath_sge *sge = &ss->sge;
  140. while (length) {
  141. u32 len = sge->length;
  142. BUG_ON(len == 0);
  143. if (len > length)
  144. len = length;
  145. memcpy(sge->vaddr, data, len);
  146. sge->vaddr += len;
  147. sge->length -= len;
  148. sge->sge_length -= len;
  149. if (sge->sge_length == 0) {
  150. if (--ss->num_sge)
  151. *sge = *ss->sg_list++;
  152. } else if (sge->length == 0 && sge->mr != NULL) {
  153. if (++sge->n >= IPATH_SEGSZ) {
  154. if (++sge->m >= sge->mr->mapsz)
  155. break;
  156. sge->n = 0;
  157. }
  158. sge->vaddr =
  159. sge->mr->map[sge->m]->segs[sge->n].vaddr;
  160. sge->length =
  161. sge->mr->map[sge->m]->segs[sge->n].length;
  162. }
  163. data += len;
  164. length -= len;
  165. }
  166. }
  167. /**
  168. * ipath_skip_sge - skip over SGE memory - XXX almost dup of prev func
  169. * @ss: the SGE state
  170. * @length: the number of bytes to skip
  171. */
  172. void ipath_skip_sge(struct ipath_sge_state *ss, u32 length)
  173. {
  174. struct ipath_sge *sge = &ss->sge;
  175. while (length) {
  176. u32 len = sge->length;
  177. BUG_ON(len == 0);
  178. if (len > length)
  179. len = length;
  180. sge->vaddr += len;
  181. sge->length -= len;
  182. sge->sge_length -= len;
  183. if (sge->sge_length == 0) {
  184. if (--ss->num_sge)
  185. *sge = *ss->sg_list++;
  186. } else if (sge->length == 0 && sge->mr != NULL) {
  187. if (++sge->n >= IPATH_SEGSZ) {
  188. if (++sge->m >= sge->mr->mapsz)
  189. break;
  190. sge->n = 0;
  191. }
  192. sge->vaddr =
  193. sge->mr->map[sge->m]->segs[sge->n].vaddr;
  194. sge->length =
  195. sge->mr->map[sge->m]->segs[sge->n].length;
  196. }
  197. length -= len;
  198. }
  199. }
  200. /**
  201. * ipath_post_send - post a send on a QP
  202. * @ibqp: the QP to post the send on
  203. * @wr: the list of work requests to post
  204. * @bad_wr: the first bad WR is put here
  205. *
  206. * This may be called from interrupt context.
  207. */
  208. static int ipath_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  209. struct ib_send_wr **bad_wr)
  210. {
  211. struct ipath_qp *qp = to_iqp(ibqp);
  212. int err = 0;
  213. /* Check that state is OK to post send. */
  214. if (!(ib_ipath_state_ops[qp->state] & IPATH_POST_SEND_OK)) {
  215. *bad_wr = wr;
  216. err = -EINVAL;
  217. goto bail;
  218. }
  219. for (; wr; wr = wr->next) {
  220. switch (qp->ibqp.qp_type) {
  221. case IB_QPT_UC:
  222. case IB_QPT_RC:
  223. err = ipath_post_ruc_send(qp, wr);
  224. break;
  225. case IB_QPT_SMI:
  226. case IB_QPT_GSI:
  227. case IB_QPT_UD:
  228. err = ipath_post_ud_send(qp, wr);
  229. break;
  230. default:
  231. err = -EINVAL;
  232. }
  233. if (err) {
  234. *bad_wr = wr;
  235. break;
  236. }
  237. }
  238. bail:
  239. return err;
  240. }
  241. /**
  242. * ipath_post_receive - post a receive on a QP
  243. * @ibqp: the QP to post the receive on
  244. * @wr: the WR to post
  245. * @bad_wr: the first bad WR is put here
  246. *
  247. * This may be called from interrupt context.
  248. */
  249. static int ipath_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  250. struct ib_recv_wr **bad_wr)
  251. {
  252. struct ipath_qp *qp = to_iqp(ibqp);
  253. struct ipath_rwq *wq = qp->r_rq.wq;
  254. unsigned long flags;
  255. int ret;
  256. /* Check that state is OK to post receive. */
  257. if (!(ib_ipath_state_ops[qp->state] & IPATH_POST_RECV_OK) || !wq) {
  258. *bad_wr = wr;
  259. ret = -EINVAL;
  260. goto bail;
  261. }
  262. for (; wr; wr = wr->next) {
  263. struct ipath_rwqe *wqe;
  264. u32 next;
  265. int i;
  266. if ((unsigned) wr->num_sge > qp->r_rq.max_sge) {
  267. *bad_wr = wr;
  268. ret = -ENOMEM;
  269. goto bail;
  270. }
  271. spin_lock_irqsave(&qp->r_rq.lock, flags);
  272. next = wq->head + 1;
  273. if (next >= qp->r_rq.size)
  274. next = 0;
  275. if (next == wq->tail) {
  276. spin_unlock_irqrestore(&qp->r_rq.lock, flags);
  277. *bad_wr = wr;
  278. ret = -ENOMEM;
  279. goto bail;
  280. }
  281. wqe = get_rwqe_ptr(&qp->r_rq, wq->head);
  282. wqe->wr_id = wr->wr_id;
  283. wqe->num_sge = wr->num_sge;
  284. for (i = 0; i < wr->num_sge; i++)
  285. wqe->sg_list[i] = wr->sg_list[i];
  286. wq->head = next;
  287. spin_unlock_irqrestore(&qp->r_rq.lock, flags);
  288. }
  289. ret = 0;
  290. bail:
  291. return ret;
  292. }
  293. /**
  294. * ipath_qp_rcv - processing an incoming packet on a QP
  295. * @dev: the device the packet came on
  296. * @hdr: the packet header
  297. * @has_grh: true if the packet has a GRH
  298. * @data: the packet data
  299. * @tlen: the packet length
  300. * @qp: the QP the packet came on
  301. *
  302. * This is called from ipath_ib_rcv() to process an incoming packet
  303. * for the given QP.
  304. * Called at interrupt level.
  305. */
  306. static void ipath_qp_rcv(struct ipath_ibdev *dev,
  307. struct ipath_ib_header *hdr, int has_grh,
  308. void *data, u32 tlen, struct ipath_qp *qp)
  309. {
  310. /* Check for valid receive state. */
  311. if (!(ib_ipath_state_ops[qp->state] & IPATH_PROCESS_RECV_OK)) {
  312. dev->n_pkt_drops++;
  313. return;
  314. }
  315. switch (qp->ibqp.qp_type) {
  316. case IB_QPT_SMI:
  317. case IB_QPT_GSI:
  318. if (ib_ipath_disable_sma)
  319. break;
  320. /* FALLTHROUGH */
  321. case IB_QPT_UD:
  322. ipath_ud_rcv(dev, hdr, has_grh, data, tlen, qp);
  323. break;
  324. case IB_QPT_RC:
  325. ipath_rc_rcv(dev, hdr, has_grh, data, tlen, qp);
  326. break;
  327. case IB_QPT_UC:
  328. ipath_uc_rcv(dev, hdr, has_grh, data, tlen, qp);
  329. break;
  330. default:
  331. break;
  332. }
  333. }
  334. /**
  335. * ipath_ib_rcv - process an incoming packet
  336. * @arg: the device pointer
  337. * @rhdr: the header of the packet
  338. * @data: the packet data
  339. * @tlen: the packet length
  340. *
  341. * This is called from ipath_kreceive() to process an incoming packet at
  342. * interrupt level. Tlen is the length of the header + data + CRC in bytes.
  343. */
  344. void ipath_ib_rcv(struct ipath_ibdev *dev, void *rhdr, void *data,
  345. u32 tlen)
  346. {
  347. struct ipath_ib_header *hdr = rhdr;
  348. struct ipath_other_headers *ohdr;
  349. struct ipath_qp *qp;
  350. u32 qp_num;
  351. int lnh;
  352. u8 opcode;
  353. u16 lid;
  354. if (unlikely(dev == NULL))
  355. goto bail;
  356. if (unlikely(tlen < 24)) { /* LRH+BTH+CRC */
  357. dev->rcv_errors++;
  358. goto bail;
  359. }
  360. /* Check for a valid destination LID (see ch. 7.11.1). */
  361. lid = be16_to_cpu(hdr->lrh[1]);
  362. if (lid < IPATH_MULTICAST_LID_BASE) {
  363. lid &= ~((1 << (dev->mkeyprot_resv_lmc & 7)) - 1);
  364. if (unlikely(lid != dev->dd->ipath_lid)) {
  365. dev->rcv_errors++;
  366. goto bail;
  367. }
  368. }
  369. /* Check for GRH */
  370. lnh = be16_to_cpu(hdr->lrh[0]) & 3;
  371. if (lnh == IPATH_LRH_BTH)
  372. ohdr = &hdr->u.oth;
  373. else if (lnh == IPATH_LRH_GRH)
  374. ohdr = &hdr->u.l.oth;
  375. else {
  376. dev->rcv_errors++;
  377. goto bail;
  378. }
  379. opcode = be32_to_cpu(ohdr->bth[0]) >> 24;
  380. dev->opstats[opcode].n_bytes += tlen;
  381. dev->opstats[opcode].n_packets++;
  382. /* Get the destination QP number. */
  383. qp_num = be32_to_cpu(ohdr->bth[1]) & IPATH_QPN_MASK;
  384. if (qp_num == IPATH_MULTICAST_QPN) {
  385. struct ipath_mcast *mcast;
  386. struct ipath_mcast_qp *p;
  387. mcast = ipath_mcast_find(&hdr->u.l.grh.dgid);
  388. if (mcast == NULL) {
  389. dev->n_pkt_drops++;
  390. goto bail;
  391. }
  392. dev->n_multicast_rcv++;
  393. list_for_each_entry_rcu(p, &mcast->qp_list, list)
  394. ipath_qp_rcv(dev, hdr, lnh == IPATH_LRH_GRH, data,
  395. tlen, p->qp);
  396. /*
  397. * Notify ipath_multicast_detach() if it is waiting for us
  398. * to finish.
  399. */
  400. if (atomic_dec_return(&mcast->refcount) <= 1)
  401. wake_up(&mcast->wait);
  402. } else {
  403. qp = ipath_lookup_qpn(&dev->qp_table, qp_num);
  404. if (qp) {
  405. dev->n_unicast_rcv++;
  406. ipath_qp_rcv(dev, hdr, lnh == IPATH_LRH_GRH, data,
  407. tlen, qp);
  408. /*
  409. * Notify ipath_destroy_qp() if it is waiting
  410. * for us to finish.
  411. */
  412. if (atomic_dec_and_test(&qp->refcount))
  413. wake_up(&qp->wait);
  414. } else
  415. dev->n_pkt_drops++;
  416. }
  417. bail:;
  418. }
  419. /**
  420. * ipath_ib_timer - verbs timer
  421. * @arg: the device pointer
  422. *
  423. * This is called from ipath_do_rcv_timer() at interrupt level to check for
  424. * QPs which need retransmits and to collect performance numbers.
  425. */
  426. void ipath_ib_timer(struct ipath_ibdev *dev)
  427. {
  428. struct ipath_qp *resend = NULL;
  429. struct list_head *last;
  430. struct ipath_qp *qp;
  431. unsigned long flags;
  432. if (dev == NULL)
  433. return;
  434. spin_lock_irqsave(&dev->pending_lock, flags);
  435. /* Start filling the next pending queue. */
  436. if (++dev->pending_index >= ARRAY_SIZE(dev->pending))
  437. dev->pending_index = 0;
  438. /* Save any requests still in the new queue, they have timed out. */
  439. last = &dev->pending[dev->pending_index];
  440. while (!list_empty(last)) {
  441. qp = list_entry(last->next, struct ipath_qp, timerwait);
  442. list_del_init(&qp->timerwait);
  443. qp->timer_next = resend;
  444. resend = qp;
  445. atomic_inc(&qp->refcount);
  446. }
  447. last = &dev->rnrwait;
  448. if (!list_empty(last)) {
  449. qp = list_entry(last->next, struct ipath_qp, timerwait);
  450. if (--qp->s_rnr_timeout == 0) {
  451. do {
  452. list_del_init(&qp->timerwait);
  453. tasklet_hi_schedule(&qp->s_task);
  454. if (list_empty(last))
  455. break;
  456. qp = list_entry(last->next, struct ipath_qp,
  457. timerwait);
  458. } while (qp->s_rnr_timeout == 0);
  459. }
  460. }
  461. /*
  462. * We should only be in the started state if pma_sample_start != 0
  463. */
  464. if (dev->pma_sample_status == IB_PMA_SAMPLE_STATUS_STARTED &&
  465. --dev->pma_sample_start == 0) {
  466. dev->pma_sample_status = IB_PMA_SAMPLE_STATUS_RUNNING;
  467. ipath_snapshot_counters(dev->dd, &dev->ipath_sword,
  468. &dev->ipath_rword,
  469. &dev->ipath_spkts,
  470. &dev->ipath_rpkts,
  471. &dev->ipath_xmit_wait);
  472. }
  473. if (dev->pma_sample_status == IB_PMA_SAMPLE_STATUS_RUNNING) {
  474. if (dev->pma_sample_interval == 0) {
  475. u64 ta, tb, tc, td, te;
  476. dev->pma_sample_status = IB_PMA_SAMPLE_STATUS_DONE;
  477. ipath_snapshot_counters(dev->dd, &ta, &tb,
  478. &tc, &td, &te);
  479. dev->ipath_sword = ta - dev->ipath_sword;
  480. dev->ipath_rword = tb - dev->ipath_rword;
  481. dev->ipath_spkts = tc - dev->ipath_spkts;
  482. dev->ipath_rpkts = td - dev->ipath_rpkts;
  483. dev->ipath_xmit_wait = te - dev->ipath_xmit_wait;
  484. }
  485. else
  486. dev->pma_sample_interval--;
  487. }
  488. spin_unlock_irqrestore(&dev->pending_lock, flags);
  489. /* XXX What if timer fires again while this is running? */
  490. for (qp = resend; qp != NULL; qp = qp->timer_next) {
  491. struct ib_wc wc;
  492. spin_lock_irqsave(&qp->s_lock, flags);
  493. if (qp->s_last != qp->s_tail && qp->state == IB_QPS_RTS) {
  494. dev->n_timeouts++;
  495. ipath_restart_rc(qp, qp->s_last_psn + 1, &wc);
  496. }
  497. spin_unlock_irqrestore(&qp->s_lock, flags);
  498. /* Notify ipath_destroy_qp() if it is waiting. */
  499. if (atomic_dec_and_test(&qp->refcount))
  500. wake_up(&qp->wait);
  501. }
  502. }
  503. static void update_sge(struct ipath_sge_state *ss, u32 length)
  504. {
  505. struct ipath_sge *sge = &ss->sge;
  506. sge->vaddr += length;
  507. sge->length -= length;
  508. sge->sge_length -= length;
  509. if (sge->sge_length == 0) {
  510. if (--ss->num_sge)
  511. *sge = *ss->sg_list++;
  512. } else if (sge->length == 0 && sge->mr != NULL) {
  513. if (++sge->n >= IPATH_SEGSZ) {
  514. if (++sge->m >= sge->mr->mapsz)
  515. return;
  516. sge->n = 0;
  517. }
  518. sge->vaddr = sge->mr->map[sge->m]->segs[sge->n].vaddr;
  519. sge->length = sge->mr->map[sge->m]->segs[sge->n].length;
  520. }
  521. }
  522. #ifdef __LITTLE_ENDIAN
  523. static inline u32 get_upper_bits(u32 data, u32 shift)
  524. {
  525. return data >> shift;
  526. }
  527. static inline u32 set_upper_bits(u32 data, u32 shift)
  528. {
  529. return data << shift;
  530. }
  531. static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
  532. {
  533. data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
  534. data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
  535. return data;
  536. }
  537. #else
  538. static inline u32 get_upper_bits(u32 data, u32 shift)
  539. {
  540. return data << shift;
  541. }
  542. static inline u32 set_upper_bits(u32 data, u32 shift)
  543. {
  544. return data >> shift;
  545. }
  546. static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
  547. {
  548. data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
  549. data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
  550. return data;
  551. }
  552. #endif
  553. static void copy_io(u32 __iomem *piobuf, struct ipath_sge_state *ss,
  554. u32 length)
  555. {
  556. u32 extra = 0;
  557. u32 data = 0;
  558. u32 last;
  559. while (1) {
  560. u32 len = ss->sge.length;
  561. u32 off;
  562. BUG_ON(len == 0);
  563. if (len > length)
  564. len = length;
  565. if (len > ss->sge.sge_length)
  566. len = ss->sge.sge_length;
  567. /* If the source address is not aligned, try to align it. */
  568. off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
  569. if (off) {
  570. u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
  571. ~(sizeof(u32) - 1));
  572. u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
  573. u32 y;
  574. y = sizeof(u32) - off;
  575. if (len > y)
  576. len = y;
  577. if (len + extra >= sizeof(u32)) {
  578. data |= set_upper_bits(v, extra *
  579. BITS_PER_BYTE);
  580. len = sizeof(u32) - extra;
  581. if (len == length) {
  582. last = data;
  583. break;
  584. }
  585. __raw_writel(data, piobuf);
  586. piobuf++;
  587. extra = 0;
  588. data = 0;
  589. } else {
  590. /* Clear unused upper bytes */
  591. data |= clear_upper_bytes(v, len, extra);
  592. if (len == length) {
  593. last = data;
  594. break;
  595. }
  596. extra += len;
  597. }
  598. } else if (extra) {
  599. /* Source address is aligned. */
  600. u32 *addr = (u32 *) ss->sge.vaddr;
  601. int shift = extra * BITS_PER_BYTE;
  602. int ushift = 32 - shift;
  603. u32 l = len;
  604. while (l >= sizeof(u32)) {
  605. u32 v = *addr;
  606. data |= set_upper_bits(v, shift);
  607. __raw_writel(data, piobuf);
  608. data = get_upper_bits(v, ushift);
  609. piobuf++;
  610. addr++;
  611. l -= sizeof(u32);
  612. }
  613. /*
  614. * We still have 'extra' number of bytes leftover.
  615. */
  616. if (l) {
  617. u32 v = *addr;
  618. if (l + extra >= sizeof(u32)) {
  619. data |= set_upper_bits(v, shift);
  620. len -= l + extra - sizeof(u32);
  621. if (len == length) {
  622. last = data;
  623. break;
  624. }
  625. __raw_writel(data, piobuf);
  626. piobuf++;
  627. extra = 0;
  628. data = 0;
  629. } else {
  630. /* Clear unused upper bytes */
  631. data |= clear_upper_bytes(v, l,
  632. extra);
  633. if (len == length) {
  634. last = data;
  635. break;
  636. }
  637. extra += l;
  638. }
  639. } else if (len == length) {
  640. last = data;
  641. break;
  642. }
  643. } else if (len == length) {
  644. u32 w;
  645. /*
  646. * Need to round up for the last dword in the
  647. * packet.
  648. */
  649. w = (len + 3) >> 2;
  650. __iowrite32_copy(piobuf, ss->sge.vaddr, w - 1);
  651. piobuf += w - 1;
  652. last = ((u32 *) ss->sge.vaddr)[w - 1];
  653. break;
  654. } else {
  655. u32 w = len >> 2;
  656. __iowrite32_copy(piobuf, ss->sge.vaddr, w);
  657. piobuf += w;
  658. extra = len & (sizeof(u32) - 1);
  659. if (extra) {
  660. u32 v = ((u32 *) ss->sge.vaddr)[w];
  661. /* Clear unused upper bytes */
  662. data = clear_upper_bytes(v, extra, 0);
  663. }
  664. }
  665. update_sge(ss, len);
  666. length -= len;
  667. }
  668. /* Update address before sending packet. */
  669. update_sge(ss, length);
  670. /* must flush early everything before trigger word */
  671. ipath_flush_wc();
  672. __raw_writel(last, piobuf);
  673. /* be sure trigger word is written */
  674. ipath_flush_wc();
  675. }
  676. /**
  677. * ipath_verbs_send - send a packet
  678. * @dd: the infinipath device
  679. * @hdrwords: the number of words in the header
  680. * @hdr: the packet header
  681. * @len: the length of the packet in bytes
  682. * @ss: the SGE to send
  683. */
  684. int ipath_verbs_send(struct ipath_devdata *dd, u32 hdrwords,
  685. u32 *hdr, u32 len, struct ipath_sge_state *ss)
  686. {
  687. u32 __iomem *piobuf;
  688. u32 plen;
  689. int ret;
  690. /* +1 is for the qword padding of pbc */
  691. plen = hdrwords + ((len + 3) >> 2) + 1;
  692. if (unlikely((plen << 2) > dd->ipath_ibmaxlen)) {
  693. ipath_dbg("packet len 0x%x too long, failing\n", plen);
  694. ret = -EINVAL;
  695. goto bail;
  696. }
  697. /* Get a PIO buffer to use. */
  698. piobuf = ipath_getpiobuf(dd, NULL);
  699. if (unlikely(piobuf == NULL)) {
  700. ret = -EBUSY;
  701. goto bail;
  702. }
  703. /*
  704. * Write len to control qword, no flags.
  705. * We have to flush after the PBC for correctness on some cpus
  706. * or WC buffer can be written out of order.
  707. */
  708. writeq(plen, piobuf);
  709. ipath_flush_wc();
  710. piobuf += 2;
  711. if (len == 0) {
  712. /*
  713. * If there is just the header portion, must flush before
  714. * writing last word of header for correctness, and after
  715. * the last header word (trigger word).
  716. */
  717. __iowrite32_copy(piobuf, hdr, hdrwords - 1);
  718. ipath_flush_wc();
  719. __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
  720. ipath_flush_wc();
  721. ret = 0;
  722. goto bail;
  723. }
  724. __iowrite32_copy(piobuf, hdr, hdrwords);
  725. piobuf += hdrwords;
  726. /* The common case is aligned and contained in one segment. */
  727. if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
  728. !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
  729. u32 w;
  730. u32 *addr = (u32 *) ss->sge.vaddr;
  731. /* Update address before sending packet. */
  732. update_sge(ss, len);
  733. /* Need to round up for the last dword in the packet. */
  734. w = (len + 3) >> 2;
  735. __iowrite32_copy(piobuf, addr, w - 1);
  736. /* must flush early everything before trigger word */
  737. ipath_flush_wc();
  738. __raw_writel(addr[w - 1], piobuf + w - 1);
  739. /* be sure trigger word is written */
  740. ipath_flush_wc();
  741. ret = 0;
  742. goto bail;
  743. }
  744. copy_io(piobuf, ss, len);
  745. ret = 0;
  746. bail:
  747. return ret;
  748. }
  749. int ipath_snapshot_counters(struct ipath_devdata *dd, u64 *swords,
  750. u64 *rwords, u64 *spkts, u64 *rpkts,
  751. u64 *xmit_wait)
  752. {
  753. int ret;
  754. if (!(dd->ipath_flags & IPATH_INITTED)) {
  755. /* no hardware, freeze, etc. */
  756. ipath_dbg("unit %u not usable\n", dd->ipath_unit);
  757. ret = -EINVAL;
  758. goto bail;
  759. }
  760. *swords = ipath_snap_cntr(dd, dd->ipath_cregs->cr_wordsendcnt);
  761. *rwords = ipath_snap_cntr(dd, dd->ipath_cregs->cr_wordrcvcnt);
  762. *spkts = ipath_snap_cntr(dd, dd->ipath_cregs->cr_pktsendcnt);
  763. *rpkts = ipath_snap_cntr(dd, dd->ipath_cregs->cr_pktrcvcnt);
  764. *xmit_wait = ipath_snap_cntr(dd, dd->ipath_cregs->cr_sendstallcnt);
  765. ret = 0;
  766. bail:
  767. return ret;
  768. }
  769. /**
  770. * ipath_get_counters - get various chip counters
  771. * @dd: the infinipath device
  772. * @cntrs: counters are placed here
  773. *
  774. * Return the counters needed by recv_pma_get_portcounters().
  775. */
  776. int ipath_get_counters(struct ipath_devdata *dd,
  777. struct ipath_verbs_counters *cntrs)
  778. {
  779. int ret;
  780. if (!(dd->ipath_flags & IPATH_INITTED)) {
  781. /* no hardware, freeze, etc. */
  782. ipath_dbg("unit %u not usable\n", dd->ipath_unit);
  783. ret = -EINVAL;
  784. goto bail;
  785. }
  786. cntrs->symbol_error_counter =
  787. ipath_snap_cntr(dd, dd->ipath_cregs->cr_ibsymbolerrcnt);
  788. cntrs->link_error_recovery_counter =
  789. ipath_snap_cntr(dd, dd->ipath_cregs->cr_iblinkerrrecovcnt);
  790. /*
  791. * The link downed counter counts when the other side downs the
  792. * connection. We add in the number of times we downed the link
  793. * due to local link integrity errors to compensate.
  794. */
  795. cntrs->link_downed_counter =
  796. ipath_snap_cntr(dd, dd->ipath_cregs->cr_iblinkdowncnt);
  797. cntrs->port_rcv_errors =
  798. ipath_snap_cntr(dd, dd->ipath_cregs->cr_rxdroppktcnt) +
  799. ipath_snap_cntr(dd, dd->ipath_cregs->cr_rcvovflcnt) +
  800. ipath_snap_cntr(dd, dd->ipath_cregs->cr_portovflcnt) +
  801. ipath_snap_cntr(dd, dd->ipath_cregs->cr_err_rlencnt) +
  802. ipath_snap_cntr(dd, dd->ipath_cregs->cr_invalidrlencnt) +
  803. ipath_snap_cntr(dd, dd->ipath_cregs->cr_erricrccnt) +
  804. ipath_snap_cntr(dd, dd->ipath_cregs->cr_errvcrccnt) +
  805. ipath_snap_cntr(dd, dd->ipath_cregs->cr_errlpcrccnt) +
  806. ipath_snap_cntr(dd, dd->ipath_cregs->cr_badformatcnt) +
  807. dd->ipath_rxfc_unsupvl_errs;
  808. cntrs->port_rcv_remphys_errors =
  809. ipath_snap_cntr(dd, dd->ipath_cregs->cr_rcvebpcnt);
  810. cntrs->port_xmit_discards =
  811. ipath_snap_cntr(dd, dd->ipath_cregs->cr_unsupvlcnt);
  812. cntrs->port_xmit_data =
  813. ipath_snap_cntr(dd, dd->ipath_cregs->cr_wordsendcnt);
  814. cntrs->port_rcv_data =
  815. ipath_snap_cntr(dd, dd->ipath_cregs->cr_wordrcvcnt);
  816. cntrs->port_xmit_packets =
  817. ipath_snap_cntr(dd, dd->ipath_cregs->cr_pktsendcnt);
  818. cntrs->port_rcv_packets =
  819. ipath_snap_cntr(dd, dd->ipath_cregs->cr_pktrcvcnt);
  820. cntrs->local_link_integrity_errors =
  821. (dd->ipath_flags & IPATH_GPIO_ERRINTRS) ?
  822. dd->ipath_lli_errs : dd->ipath_lli_errors;
  823. cntrs->excessive_buffer_overrun_errors = dd->ipath_overrun_thresh_errs;
  824. ret = 0;
  825. bail:
  826. return ret;
  827. }
  828. /**
  829. * ipath_ib_piobufavail - callback when a PIO buffer is available
  830. * @arg: the device pointer
  831. *
  832. * This is called from ipath_intr() at interrupt level when a PIO buffer is
  833. * available after ipath_verbs_send() returned an error that no buffers were
  834. * available. Return 1 if we consumed all the PIO buffers and we still have
  835. * QPs waiting for buffers (for now, just do a tasklet_hi_schedule and
  836. * return zero).
  837. */
  838. int ipath_ib_piobufavail(struct ipath_ibdev *dev)
  839. {
  840. struct ipath_qp *qp;
  841. unsigned long flags;
  842. if (dev == NULL)
  843. goto bail;
  844. spin_lock_irqsave(&dev->pending_lock, flags);
  845. while (!list_empty(&dev->piowait)) {
  846. qp = list_entry(dev->piowait.next, struct ipath_qp,
  847. piowait);
  848. list_del_init(&qp->piowait);
  849. tasklet_hi_schedule(&qp->s_task);
  850. }
  851. spin_unlock_irqrestore(&dev->pending_lock, flags);
  852. bail:
  853. return 0;
  854. }
  855. static int ipath_query_device(struct ib_device *ibdev,
  856. struct ib_device_attr *props)
  857. {
  858. struct ipath_ibdev *dev = to_idev(ibdev);
  859. memset(props, 0, sizeof(*props));
  860. props->device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
  861. IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
  862. IB_DEVICE_SYS_IMAGE_GUID;
  863. props->page_size_cap = PAGE_SIZE;
  864. props->vendor_id = dev->dd->ipath_vendorid;
  865. props->vendor_part_id = dev->dd->ipath_deviceid;
  866. props->hw_ver = dev->dd->ipath_pcirev;
  867. props->sys_image_guid = dev->sys_image_guid;
  868. props->max_mr_size = ~0ull;
  869. props->max_qp = ib_ipath_max_qps;
  870. props->max_qp_wr = ib_ipath_max_qp_wrs;
  871. props->max_sge = ib_ipath_max_sges;
  872. props->max_cq = ib_ipath_max_cqs;
  873. props->max_ah = ib_ipath_max_ahs;
  874. props->max_cqe = ib_ipath_max_cqes;
  875. props->max_mr = dev->lk_table.max;
  876. props->max_pd = ib_ipath_max_pds;
  877. props->max_qp_rd_atom = 1;
  878. props->max_qp_init_rd_atom = 1;
  879. /* props->max_res_rd_atom */
  880. props->max_srq = ib_ipath_max_srqs;
  881. props->max_srq_wr = ib_ipath_max_srq_wrs;
  882. props->max_srq_sge = ib_ipath_max_srq_sges;
  883. /* props->local_ca_ack_delay */
  884. props->atomic_cap = IB_ATOMIC_HCA;
  885. props->max_pkeys = ipath_get_npkeys(dev->dd);
  886. props->max_mcast_grp = ib_ipath_max_mcast_grps;
  887. props->max_mcast_qp_attach = ib_ipath_max_mcast_qp_attached;
  888. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  889. props->max_mcast_grp;
  890. return 0;
  891. }
  892. const u8 ipath_cvt_physportstate[16] = {
  893. [INFINIPATH_IBCS_LT_STATE_DISABLED] = 3,
  894. [INFINIPATH_IBCS_LT_STATE_LINKUP] = 5,
  895. [INFINIPATH_IBCS_LT_STATE_POLLACTIVE] = 2,
  896. [INFINIPATH_IBCS_LT_STATE_POLLQUIET] = 2,
  897. [INFINIPATH_IBCS_LT_STATE_SLEEPDELAY] = 1,
  898. [INFINIPATH_IBCS_LT_STATE_SLEEPQUIET] = 1,
  899. [INFINIPATH_IBCS_LT_STATE_CFGDEBOUNCE] = 4,
  900. [INFINIPATH_IBCS_LT_STATE_CFGRCVFCFG] = 4,
  901. [INFINIPATH_IBCS_LT_STATE_CFGWAITRMT] = 4,
  902. [INFINIPATH_IBCS_LT_STATE_CFGIDLE] = 4,
  903. [INFINIPATH_IBCS_LT_STATE_RECOVERRETRAIN] = 6,
  904. [INFINIPATH_IBCS_LT_STATE_RECOVERWAITRMT] = 6,
  905. [INFINIPATH_IBCS_LT_STATE_RECOVERIDLE] = 6,
  906. };
  907. u32 ipath_get_cr_errpkey(struct ipath_devdata *dd)
  908. {
  909. return ipath_read_creg32(dd, dd->ipath_cregs->cr_errpkey);
  910. }
  911. static int ipath_query_port(struct ib_device *ibdev,
  912. u8 port, struct ib_port_attr *props)
  913. {
  914. struct ipath_ibdev *dev = to_idev(ibdev);
  915. enum ib_mtu mtu;
  916. u16 lid = dev->dd->ipath_lid;
  917. u64 ibcstat;
  918. memset(props, 0, sizeof(*props));
  919. props->lid = lid ? lid : __constant_be16_to_cpu(IB_LID_PERMISSIVE);
  920. props->lmc = dev->mkeyprot_resv_lmc & 7;
  921. props->sm_lid = dev->sm_lid;
  922. props->sm_sl = dev->sm_sl;
  923. ibcstat = dev->dd->ipath_lastibcstat;
  924. props->state = ((ibcstat >> 4) & 0x3) + 1;
  925. /* See phys_state_show() */
  926. props->phys_state = ipath_cvt_physportstate[
  927. dev->dd->ipath_lastibcstat & 0xf];
  928. props->port_cap_flags = dev->port_cap_flags;
  929. props->gid_tbl_len = 1;
  930. props->max_msg_sz = 0x80000000;
  931. props->pkey_tbl_len = ipath_get_npkeys(dev->dd);
  932. props->bad_pkey_cntr = ipath_get_cr_errpkey(dev->dd) -
  933. dev->z_pkey_violations;
  934. props->qkey_viol_cntr = dev->qkey_violations;
  935. props->active_width = IB_WIDTH_4X;
  936. /* See rate_show() */
  937. props->active_speed = 1; /* Regular 10Mbs speed. */
  938. props->max_vl_num = 1; /* VLCap = VL0 */
  939. props->init_type_reply = 0;
  940. props->max_mtu = IB_MTU_4096;
  941. switch (dev->dd->ipath_ibmtu) {
  942. case 4096:
  943. mtu = IB_MTU_4096;
  944. break;
  945. case 2048:
  946. mtu = IB_MTU_2048;
  947. break;
  948. case 1024:
  949. mtu = IB_MTU_1024;
  950. break;
  951. case 512:
  952. mtu = IB_MTU_512;
  953. break;
  954. case 256:
  955. mtu = IB_MTU_256;
  956. break;
  957. default:
  958. mtu = IB_MTU_2048;
  959. }
  960. props->active_mtu = mtu;
  961. props->subnet_timeout = dev->subnet_timeout;
  962. return 0;
  963. }
  964. static int ipath_modify_device(struct ib_device *device,
  965. int device_modify_mask,
  966. struct ib_device_modify *device_modify)
  967. {
  968. int ret;
  969. if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
  970. IB_DEVICE_MODIFY_NODE_DESC)) {
  971. ret = -EOPNOTSUPP;
  972. goto bail;
  973. }
  974. if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC)
  975. memcpy(device->node_desc, device_modify->node_desc, 64);
  976. if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID)
  977. to_idev(device)->sys_image_guid =
  978. cpu_to_be64(device_modify->sys_image_guid);
  979. ret = 0;
  980. bail:
  981. return ret;
  982. }
  983. static int ipath_modify_port(struct ib_device *ibdev,
  984. u8 port, int port_modify_mask,
  985. struct ib_port_modify *props)
  986. {
  987. struct ipath_ibdev *dev = to_idev(ibdev);
  988. dev->port_cap_flags |= props->set_port_cap_mask;
  989. dev->port_cap_flags &= ~props->clr_port_cap_mask;
  990. if (port_modify_mask & IB_PORT_SHUTDOWN)
  991. ipath_set_linkstate(dev->dd, IPATH_IB_LINKDOWN);
  992. if (port_modify_mask & IB_PORT_RESET_QKEY_CNTR)
  993. dev->qkey_violations = 0;
  994. return 0;
  995. }
  996. static int ipath_query_gid(struct ib_device *ibdev, u8 port,
  997. int index, union ib_gid *gid)
  998. {
  999. struct ipath_ibdev *dev = to_idev(ibdev);
  1000. int ret;
  1001. if (index >= 1) {
  1002. ret = -EINVAL;
  1003. goto bail;
  1004. }
  1005. gid->global.subnet_prefix = dev->gid_prefix;
  1006. gid->global.interface_id = dev->dd->ipath_guid;
  1007. ret = 0;
  1008. bail:
  1009. return ret;
  1010. }
  1011. static struct ib_pd *ipath_alloc_pd(struct ib_device *ibdev,
  1012. struct ib_ucontext *context,
  1013. struct ib_udata *udata)
  1014. {
  1015. struct ipath_ibdev *dev = to_idev(ibdev);
  1016. struct ipath_pd *pd;
  1017. struct ib_pd *ret;
  1018. /*
  1019. * This is actually totally arbitrary. Some correctness tests
  1020. * assume there's a maximum number of PDs that can be allocated.
  1021. * We don't actually have this limit, but we fail the test if
  1022. * we allow allocations of more than we report for this value.
  1023. */
  1024. pd = kmalloc(sizeof *pd, GFP_KERNEL);
  1025. if (!pd) {
  1026. ret = ERR_PTR(-ENOMEM);
  1027. goto bail;
  1028. }
  1029. spin_lock(&dev->n_pds_lock);
  1030. if (dev->n_pds_allocated == ib_ipath_max_pds) {
  1031. spin_unlock(&dev->n_pds_lock);
  1032. kfree(pd);
  1033. ret = ERR_PTR(-ENOMEM);
  1034. goto bail;
  1035. }
  1036. dev->n_pds_allocated++;
  1037. spin_unlock(&dev->n_pds_lock);
  1038. /* ib_alloc_pd() will initialize pd->ibpd. */
  1039. pd->user = udata != NULL;
  1040. ret = &pd->ibpd;
  1041. bail:
  1042. return ret;
  1043. }
  1044. static int ipath_dealloc_pd(struct ib_pd *ibpd)
  1045. {
  1046. struct ipath_pd *pd = to_ipd(ibpd);
  1047. struct ipath_ibdev *dev = to_idev(ibpd->device);
  1048. spin_lock(&dev->n_pds_lock);
  1049. dev->n_pds_allocated--;
  1050. spin_unlock(&dev->n_pds_lock);
  1051. kfree(pd);
  1052. return 0;
  1053. }
  1054. /**
  1055. * ipath_create_ah - create an address handle
  1056. * @pd: the protection domain
  1057. * @ah_attr: the attributes of the AH
  1058. *
  1059. * This may be called from interrupt context.
  1060. */
  1061. static struct ib_ah *ipath_create_ah(struct ib_pd *pd,
  1062. struct ib_ah_attr *ah_attr)
  1063. {
  1064. struct ipath_ah *ah;
  1065. struct ib_ah *ret;
  1066. struct ipath_ibdev *dev = to_idev(pd->device);
  1067. unsigned long flags;
  1068. /* A multicast address requires a GRH (see ch. 8.4.1). */
  1069. if (ah_attr->dlid >= IPATH_MULTICAST_LID_BASE &&
  1070. ah_attr->dlid != IPATH_PERMISSIVE_LID &&
  1071. !(ah_attr->ah_flags & IB_AH_GRH)) {
  1072. ret = ERR_PTR(-EINVAL);
  1073. goto bail;
  1074. }
  1075. if (ah_attr->dlid == 0) {
  1076. ret = ERR_PTR(-EINVAL);
  1077. goto bail;
  1078. }
  1079. if (ah_attr->port_num < 1 ||
  1080. ah_attr->port_num > pd->device->phys_port_cnt) {
  1081. ret = ERR_PTR(-EINVAL);
  1082. goto bail;
  1083. }
  1084. ah = kmalloc(sizeof *ah, GFP_ATOMIC);
  1085. if (!ah) {
  1086. ret = ERR_PTR(-ENOMEM);
  1087. goto bail;
  1088. }
  1089. spin_lock_irqsave(&dev->n_ahs_lock, flags);
  1090. if (dev->n_ahs_allocated == ib_ipath_max_ahs) {
  1091. spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
  1092. kfree(ah);
  1093. ret = ERR_PTR(-ENOMEM);
  1094. goto bail;
  1095. }
  1096. dev->n_ahs_allocated++;
  1097. spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
  1098. /* ib_create_ah() will initialize ah->ibah. */
  1099. ah->attr = *ah_attr;
  1100. ret = &ah->ibah;
  1101. bail:
  1102. return ret;
  1103. }
  1104. /**
  1105. * ipath_destroy_ah - destroy an address handle
  1106. * @ibah: the AH to destroy
  1107. *
  1108. * This may be called from interrupt context.
  1109. */
  1110. static int ipath_destroy_ah(struct ib_ah *ibah)
  1111. {
  1112. struct ipath_ibdev *dev = to_idev(ibah->device);
  1113. struct ipath_ah *ah = to_iah(ibah);
  1114. unsigned long flags;
  1115. spin_lock_irqsave(&dev->n_ahs_lock, flags);
  1116. dev->n_ahs_allocated--;
  1117. spin_unlock_irqrestore(&dev->n_ahs_lock, flags);
  1118. kfree(ah);
  1119. return 0;
  1120. }
  1121. static int ipath_query_ah(struct ib_ah *ibah, struct ib_ah_attr *ah_attr)
  1122. {
  1123. struct ipath_ah *ah = to_iah(ibah);
  1124. *ah_attr = ah->attr;
  1125. return 0;
  1126. }
  1127. /**
  1128. * ipath_get_npkeys - return the size of the PKEY table for port 0
  1129. * @dd: the infinipath device
  1130. */
  1131. unsigned ipath_get_npkeys(struct ipath_devdata *dd)
  1132. {
  1133. return ARRAY_SIZE(dd->ipath_pd[0]->port_pkeys);
  1134. }
  1135. /**
  1136. * ipath_get_pkey - return the indexed PKEY from the port 0 PKEY table
  1137. * @dd: the infinipath device
  1138. * @index: the PKEY index
  1139. */
  1140. unsigned ipath_get_pkey(struct ipath_devdata *dd, unsigned index)
  1141. {
  1142. unsigned ret;
  1143. if (index >= ARRAY_SIZE(dd->ipath_pd[0]->port_pkeys))
  1144. ret = 0;
  1145. else
  1146. ret = dd->ipath_pd[0]->port_pkeys[index];
  1147. return ret;
  1148. }
  1149. static int ipath_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  1150. u16 *pkey)
  1151. {
  1152. struct ipath_ibdev *dev = to_idev(ibdev);
  1153. int ret;
  1154. if (index >= ipath_get_npkeys(dev->dd)) {
  1155. ret = -EINVAL;
  1156. goto bail;
  1157. }
  1158. *pkey = ipath_get_pkey(dev->dd, index);
  1159. ret = 0;
  1160. bail:
  1161. return ret;
  1162. }
  1163. /**
  1164. * ipath_alloc_ucontext - allocate a ucontest
  1165. * @ibdev: the infiniband device
  1166. * @udata: not used by the InfiniPath driver
  1167. */
  1168. static struct ib_ucontext *ipath_alloc_ucontext(struct ib_device *ibdev,
  1169. struct ib_udata *udata)
  1170. {
  1171. struct ipath_ucontext *context;
  1172. struct ib_ucontext *ret;
  1173. context = kmalloc(sizeof *context, GFP_KERNEL);
  1174. if (!context) {
  1175. ret = ERR_PTR(-ENOMEM);
  1176. goto bail;
  1177. }
  1178. ret = &context->ibucontext;
  1179. bail:
  1180. return ret;
  1181. }
  1182. static int ipath_dealloc_ucontext(struct ib_ucontext *context)
  1183. {
  1184. kfree(to_iucontext(context));
  1185. return 0;
  1186. }
  1187. static int ipath_verbs_register_sysfs(struct ib_device *dev);
  1188. static void __verbs_timer(unsigned long arg)
  1189. {
  1190. struct ipath_devdata *dd = (struct ipath_devdata *) arg;
  1191. /*
  1192. * If port 0 receive packet interrupts are not available, or
  1193. * can be missed, poll the receive queue
  1194. */
  1195. if (dd->ipath_flags & IPATH_POLL_RX_INTR)
  1196. ipath_kreceive(dd);
  1197. /* Handle verbs layer timeouts. */
  1198. ipath_ib_timer(dd->verbs_dev);
  1199. mod_timer(&dd->verbs_timer, jiffies + 1);
  1200. }
  1201. static int enable_timer(struct ipath_devdata *dd)
  1202. {
  1203. /*
  1204. * Early chips had a design flaw where the chip and kernel idea
  1205. * of the tail register don't always agree, and therefore we won't
  1206. * get an interrupt on the next packet received.
  1207. * If the board supports per packet receive interrupts, use it.
  1208. * Otherwise, the timer function periodically checks for packets
  1209. * to cover this case.
  1210. * Either way, the timer is needed for verbs layer related
  1211. * processing.
  1212. */
  1213. if (dd->ipath_flags & IPATH_GPIO_INTR) {
  1214. u64 val;
  1215. ipath_write_kreg(dd, dd->ipath_kregs->kr_debugportselect,
  1216. 0x2074076542310ULL);
  1217. /* Enable GPIO bit 2 interrupt */
  1218. val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_mask);
  1219. val |= (u64) (1 << IPATH_GPIO_PORT0_BIT);
  1220. ipath_write_kreg( dd, dd->ipath_kregs->kr_gpio_mask, val);
  1221. }
  1222. init_timer(&dd->verbs_timer);
  1223. dd->verbs_timer.function = __verbs_timer;
  1224. dd->verbs_timer.data = (unsigned long)dd;
  1225. dd->verbs_timer.expires = jiffies + 1;
  1226. add_timer(&dd->verbs_timer);
  1227. return 0;
  1228. }
  1229. static int disable_timer(struct ipath_devdata *dd)
  1230. {
  1231. /* Disable GPIO bit 2 interrupt */
  1232. if (dd->ipath_flags & IPATH_GPIO_INTR) {
  1233. u64 val;
  1234. /* Disable GPIO bit 2 interrupt */
  1235. val = ipath_read_kreg64(dd, dd->ipath_kregs->kr_gpio_mask);
  1236. val &= ~((u64) (1 << IPATH_GPIO_PORT0_BIT));
  1237. ipath_write_kreg( dd, dd->ipath_kregs->kr_gpio_mask, val);
  1238. /*
  1239. * We might want to undo changes to debugportselect,
  1240. * but how?
  1241. */
  1242. }
  1243. del_timer_sync(&dd->verbs_timer);
  1244. return 0;
  1245. }
  1246. /**
  1247. * ipath_register_ib_device - register our device with the infiniband core
  1248. * @dd: the device data structure
  1249. * Return the allocated ipath_ibdev pointer or NULL on error.
  1250. */
  1251. int ipath_register_ib_device(struct ipath_devdata *dd)
  1252. {
  1253. struct ipath_verbs_counters cntrs;
  1254. struct ipath_ibdev *idev;
  1255. struct ib_device *dev;
  1256. int ret;
  1257. idev = (struct ipath_ibdev *)ib_alloc_device(sizeof *idev);
  1258. if (idev == NULL) {
  1259. ret = -ENOMEM;
  1260. goto bail;
  1261. }
  1262. dev = &idev->ibdev;
  1263. /* Only need to initialize non-zero fields. */
  1264. spin_lock_init(&idev->n_pds_lock);
  1265. spin_lock_init(&idev->n_ahs_lock);
  1266. spin_lock_init(&idev->n_cqs_lock);
  1267. spin_lock_init(&idev->n_qps_lock);
  1268. spin_lock_init(&idev->n_srqs_lock);
  1269. spin_lock_init(&idev->n_mcast_grps_lock);
  1270. spin_lock_init(&idev->qp_table.lock);
  1271. spin_lock_init(&idev->lk_table.lock);
  1272. idev->sm_lid = __constant_be16_to_cpu(IB_LID_PERMISSIVE);
  1273. /* Set the prefix to the default value (see ch. 4.1.1) */
  1274. idev->gid_prefix = __constant_cpu_to_be64(0xfe80000000000000ULL);
  1275. ret = ipath_init_qp_table(idev, ib_ipath_qp_table_size);
  1276. if (ret)
  1277. goto err_qp;
  1278. /*
  1279. * The top ib_ipath_lkey_table_size bits are used to index the
  1280. * table. The lower 8 bits can be owned by the user (copied from
  1281. * the LKEY). The remaining bits act as a generation number or tag.
  1282. */
  1283. idev->lk_table.max = 1 << ib_ipath_lkey_table_size;
  1284. idev->lk_table.table = kzalloc(idev->lk_table.max *
  1285. sizeof(*idev->lk_table.table),
  1286. GFP_KERNEL);
  1287. if (idev->lk_table.table == NULL) {
  1288. ret = -ENOMEM;
  1289. goto err_lk;
  1290. }
  1291. spin_lock_init(&idev->pending_lock);
  1292. INIT_LIST_HEAD(&idev->pending[0]);
  1293. INIT_LIST_HEAD(&idev->pending[1]);
  1294. INIT_LIST_HEAD(&idev->pending[2]);
  1295. INIT_LIST_HEAD(&idev->piowait);
  1296. INIT_LIST_HEAD(&idev->rnrwait);
  1297. idev->pending_index = 0;
  1298. idev->port_cap_flags =
  1299. IB_PORT_SYS_IMAGE_GUID_SUP | IB_PORT_CLIENT_REG_SUP;
  1300. idev->pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
  1301. idev->pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
  1302. idev->pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
  1303. idev->pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
  1304. idev->pma_counter_select[5] = IB_PMA_PORT_XMIT_WAIT;
  1305. idev->link_width_enabled = 3; /* 1x or 4x */
  1306. /* Snapshot current HW counters to "clear" them. */
  1307. ipath_get_counters(dd, &cntrs);
  1308. idev->z_symbol_error_counter = cntrs.symbol_error_counter;
  1309. idev->z_link_error_recovery_counter =
  1310. cntrs.link_error_recovery_counter;
  1311. idev->z_link_downed_counter = cntrs.link_downed_counter;
  1312. idev->z_port_rcv_errors = cntrs.port_rcv_errors;
  1313. idev->z_port_rcv_remphys_errors =
  1314. cntrs.port_rcv_remphys_errors;
  1315. idev->z_port_xmit_discards = cntrs.port_xmit_discards;
  1316. idev->z_port_xmit_data = cntrs.port_xmit_data;
  1317. idev->z_port_rcv_data = cntrs.port_rcv_data;
  1318. idev->z_port_xmit_packets = cntrs.port_xmit_packets;
  1319. idev->z_port_rcv_packets = cntrs.port_rcv_packets;
  1320. idev->z_local_link_integrity_errors =
  1321. cntrs.local_link_integrity_errors;
  1322. idev->z_excessive_buffer_overrun_errors =
  1323. cntrs.excessive_buffer_overrun_errors;
  1324. /*
  1325. * The system image GUID is supposed to be the same for all
  1326. * IB HCAs in a single system but since there can be other
  1327. * device types in the system, we can't be sure this is unique.
  1328. */
  1329. if (!sys_image_guid)
  1330. sys_image_guid = dd->ipath_guid;
  1331. idev->sys_image_guid = sys_image_guid;
  1332. idev->ib_unit = dd->ipath_unit;
  1333. idev->dd = dd;
  1334. strlcpy(dev->name, "ipath%d", IB_DEVICE_NAME_MAX);
  1335. dev->owner = THIS_MODULE;
  1336. dev->node_guid = dd->ipath_guid;
  1337. dev->uverbs_abi_ver = IPATH_UVERBS_ABI_VERSION;
  1338. dev->uverbs_cmd_mask =
  1339. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  1340. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  1341. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  1342. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  1343. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  1344. (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
  1345. (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
  1346. (1ull << IB_USER_VERBS_CMD_QUERY_AH) |
  1347. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  1348. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  1349. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  1350. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  1351. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  1352. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  1353. (1ull << IB_USER_VERBS_CMD_POLL_CQ) |
  1354. (1ull << IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
  1355. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  1356. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  1357. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  1358. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  1359. (1ull << IB_USER_VERBS_CMD_POST_SEND) |
  1360. (1ull << IB_USER_VERBS_CMD_POST_RECV) |
  1361. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  1362. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  1363. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  1364. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  1365. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  1366. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  1367. (1ull << IB_USER_VERBS_CMD_POST_SRQ_RECV);
  1368. dev->node_type = RDMA_NODE_IB_CA;
  1369. dev->phys_port_cnt = 1;
  1370. dev->dma_device = &dd->pcidev->dev;
  1371. dev->class_dev.dev = dev->dma_device;
  1372. dev->query_device = ipath_query_device;
  1373. dev->modify_device = ipath_modify_device;
  1374. dev->query_port = ipath_query_port;
  1375. dev->modify_port = ipath_modify_port;
  1376. dev->query_pkey = ipath_query_pkey;
  1377. dev->query_gid = ipath_query_gid;
  1378. dev->alloc_ucontext = ipath_alloc_ucontext;
  1379. dev->dealloc_ucontext = ipath_dealloc_ucontext;
  1380. dev->alloc_pd = ipath_alloc_pd;
  1381. dev->dealloc_pd = ipath_dealloc_pd;
  1382. dev->create_ah = ipath_create_ah;
  1383. dev->destroy_ah = ipath_destroy_ah;
  1384. dev->query_ah = ipath_query_ah;
  1385. dev->create_srq = ipath_create_srq;
  1386. dev->modify_srq = ipath_modify_srq;
  1387. dev->query_srq = ipath_query_srq;
  1388. dev->destroy_srq = ipath_destroy_srq;
  1389. dev->create_qp = ipath_create_qp;
  1390. dev->modify_qp = ipath_modify_qp;
  1391. dev->query_qp = ipath_query_qp;
  1392. dev->destroy_qp = ipath_destroy_qp;
  1393. dev->post_send = ipath_post_send;
  1394. dev->post_recv = ipath_post_receive;
  1395. dev->post_srq_recv = ipath_post_srq_receive;
  1396. dev->create_cq = ipath_create_cq;
  1397. dev->destroy_cq = ipath_destroy_cq;
  1398. dev->resize_cq = ipath_resize_cq;
  1399. dev->poll_cq = ipath_poll_cq;
  1400. dev->req_notify_cq = ipath_req_notify_cq;
  1401. dev->get_dma_mr = ipath_get_dma_mr;
  1402. dev->reg_phys_mr = ipath_reg_phys_mr;
  1403. dev->reg_user_mr = ipath_reg_user_mr;
  1404. dev->dereg_mr = ipath_dereg_mr;
  1405. dev->alloc_fmr = ipath_alloc_fmr;
  1406. dev->map_phys_fmr = ipath_map_phys_fmr;
  1407. dev->unmap_fmr = ipath_unmap_fmr;
  1408. dev->dealloc_fmr = ipath_dealloc_fmr;
  1409. dev->attach_mcast = ipath_multicast_attach;
  1410. dev->detach_mcast = ipath_multicast_detach;
  1411. dev->process_mad = ipath_process_mad;
  1412. dev->mmap = ipath_mmap;
  1413. snprintf(dev->node_desc, sizeof(dev->node_desc),
  1414. IPATH_IDSTR " %s", init_utsname()->nodename);
  1415. ret = ib_register_device(dev);
  1416. if (ret)
  1417. goto err_reg;
  1418. if (ipath_verbs_register_sysfs(dev))
  1419. goto err_class;
  1420. enable_timer(dd);
  1421. goto bail;
  1422. err_class:
  1423. ib_unregister_device(dev);
  1424. err_reg:
  1425. kfree(idev->lk_table.table);
  1426. err_lk:
  1427. kfree(idev->qp_table.table);
  1428. err_qp:
  1429. ib_dealloc_device(dev);
  1430. ipath_dev_err(dd, "cannot register verbs: %d!\n", -ret);
  1431. idev = NULL;
  1432. bail:
  1433. dd->verbs_dev = idev;
  1434. return ret;
  1435. }
  1436. void ipath_unregister_ib_device(struct ipath_ibdev *dev)
  1437. {
  1438. struct ib_device *ibdev = &dev->ibdev;
  1439. disable_timer(dev->dd);
  1440. ib_unregister_device(ibdev);
  1441. if (!list_empty(&dev->pending[0]) ||
  1442. !list_empty(&dev->pending[1]) ||
  1443. !list_empty(&dev->pending[2]))
  1444. ipath_dev_err(dev->dd, "pending list not empty!\n");
  1445. if (!list_empty(&dev->piowait))
  1446. ipath_dev_err(dev->dd, "piowait list not empty!\n");
  1447. if (!list_empty(&dev->rnrwait))
  1448. ipath_dev_err(dev->dd, "rnrwait list not empty!\n");
  1449. if (!ipath_mcast_tree_empty())
  1450. ipath_dev_err(dev->dd, "multicast table memory leak!\n");
  1451. /*
  1452. * Note that ipath_unregister_ib_device() can be called before all
  1453. * the QPs are destroyed!
  1454. */
  1455. ipath_free_all_qps(&dev->qp_table);
  1456. kfree(dev->qp_table.table);
  1457. kfree(dev->lk_table.table);
  1458. ib_dealloc_device(ibdev);
  1459. }
  1460. static ssize_t show_rev(struct class_device *cdev, char *buf)
  1461. {
  1462. struct ipath_ibdev *dev =
  1463. container_of(cdev, struct ipath_ibdev, ibdev.class_dev);
  1464. return sprintf(buf, "%x\n", dev->dd->ipath_pcirev);
  1465. }
  1466. static ssize_t show_hca(struct class_device *cdev, char *buf)
  1467. {
  1468. struct ipath_ibdev *dev =
  1469. container_of(cdev, struct ipath_ibdev, ibdev.class_dev);
  1470. int ret;
  1471. ret = dev->dd->ipath_f_get_boardname(dev->dd, buf, 128);
  1472. if (ret < 0)
  1473. goto bail;
  1474. strcat(buf, "\n");
  1475. ret = strlen(buf);
  1476. bail:
  1477. return ret;
  1478. }
  1479. static ssize_t show_stats(struct class_device *cdev, char *buf)
  1480. {
  1481. struct ipath_ibdev *dev =
  1482. container_of(cdev, struct ipath_ibdev, ibdev.class_dev);
  1483. int i;
  1484. int len;
  1485. len = sprintf(buf,
  1486. "RC resends %d\n"
  1487. "RC no QACK %d\n"
  1488. "RC ACKs %d\n"
  1489. "RC SEQ NAKs %d\n"
  1490. "RC RDMA seq %d\n"
  1491. "RC RNR NAKs %d\n"
  1492. "RC OTH NAKs %d\n"
  1493. "RC timeouts %d\n"
  1494. "RC RDMA dup %d\n"
  1495. "RC stalls %d\n"
  1496. "piobuf wait %d\n"
  1497. "no piobuf %d\n"
  1498. "PKT drops %d\n"
  1499. "WQE errs %d\n",
  1500. dev->n_rc_resends, dev->n_rc_qacks, dev->n_rc_acks,
  1501. dev->n_seq_naks, dev->n_rdma_seq, dev->n_rnr_naks,
  1502. dev->n_other_naks, dev->n_timeouts,
  1503. dev->n_rdma_dup_busy, dev->n_rc_stalls, dev->n_piowait,
  1504. dev->n_no_piobuf, dev->n_pkt_drops, dev->n_wqe_errs);
  1505. for (i = 0; i < ARRAY_SIZE(dev->opstats); i++) {
  1506. const struct ipath_opcode_stats *si = &dev->opstats[i];
  1507. if (!si->n_packets && !si->n_bytes)
  1508. continue;
  1509. len += sprintf(buf + len, "%02x %llu/%llu\n", i,
  1510. (unsigned long long) si->n_packets,
  1511. (unsigned long long) si->n_bytes);
  1512. }
  1513. return len;
  1514. }
  1515. static CLASS_DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  1516. static CLASS_DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  1517. static CLASS_DEVICE_ATTR(board_id, S_IRUGO, show_hca, NULL);
  1518. static CLASS_DEVICE_ATTR(stats, S_IRUGO, show_stats, NULL);
  1519. static struct class_device_attribute *ipath_class_attributes[] = {
  1520. &class_device_attr_hw_rev,
  1521. &class_device_attr_hca_type,
  1522. &class_device_attr_board_id,
  1523. &class_device_attr_stats
  1524. };
  1525. static int ipath_verbs_register_sysfs(struct ib_device *dev)
  1526. {
  1527. int i;
  1528. int ret;
  1529. for (i = 0; i < ARRAY_SIZE(ipath_class_attributes); ++i)
  1530. if (class_device_create_file(&dev->class_dev,
  1531. ipath_class_attributes[i])) {
  1532. ret = 1;
  1533. goto bail;
  1534. }
  1535. ret = 0;
  1536. bail:
  1537. return ret;
  1538. }