via82cxxx.c 14 KB

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  1. /*
  2. *
  3. * Version 3.38
  4. *
  5. * VIA IDE driver for Linux. Supported southbridges:
  6. *
  7. * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b,
  8. * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a,
  9. * vt8235, vt8237, vt8237a
  10. *
  11. * Copyright (c) 2000-2002 Vojtech Pavlik
  12. *
  13. * Based on the work of:
  14. * Michel Aubry
  15. * Jeff Garzik
  16. * Andre Hedrick
  17. *
  18. * Documentation:
  19. * Obsolete device documentation publically available from via.com.tw
  20. * Current device documentation available under NDA only
  21. */
  22. /*
  23. * This program is free software; you can redistribute it and/or modify it
  24. * under the terms of the GNU General Public License version 2 as published by
  25. * the Free Software Foundation.
  26. */
  27. #include <linux/module.h>
  28. #include <linux/kernel.h>
  29. #include <linux/ioport.h>
  30. #include <linux/blkdev.h>
  31. #include <linux/pci.h>
  32. #include <linux/init.h>
  33. #include <linux/ide.h>
  34. #include <asm/io.h>
  35. #ifdef CONFIG_PPC_MULTIPLATFORM
  36. #include <asm/processor.h>
  37. #endif
  38. #include "ide-timing.h"
  39. #define DISPLAY_VIA_TIMINGS
  40. #define VIA_IDE_ENABLE 0x40
  41. #define VIA_IDE_CONFIG 0x41
  42. #define VIA_FIFO_CONFIG 0x43
  43. #define VIA_MISC_1 0x44
  44. #define VIA_MISC_2 0x45
  45. #define VIA_MISC_3 0x46
  46. #define VIA_DRIVE_TIMING 0x48
  47. #define VIA_8BIT_TIMING 0x4e
  48. #define VIA_ADDRESS_SETUP 0x4c
  49. #define VIA_UDMA_TIMING 0x50
  50. #define VIA_UDMA 0x007
  51. #define VIA_UDMA_NONE 0x000
  52. #define VIA_UDMA_33 0x001
  53. #define VIA_UDMA_66 0x002
  54. #define VIA_UDMA_100 0x003
  55. #define VIA_UDMA_133 0x004
  56. #define VIA_BAD_PREQ 0x010 /* Crashes if PREQ# till DDACK# set */
  57. #define VIA_BAD_CLK66 0x020 /* 66 MHz clock doesn't work correctly */
  58. #define VIA_SET_FIFO 0x040 /* Needs to have FIFO split set */
  59. #define VIA_NO_UNMASK 0x080 /* Doesn't work with IRQ unmasking on */
  60. #define VIA_BAD_ID 0x100 /* Has wrong vendor ID (0x1107) */
  61. #define VIA_BAD_AST 0x200 /* Don't touch Address Setup Timing */
  62. /*
  63. * VIA SouthBridge chips.
  64. */
  65. static struct via_isa_bridge {
  66. char *name;
  67. u16 id;
  68. u8 rev_min;
  69. u8 rev_max;
  70. u16 flags;
  71. } via_isa_bridges[] = {
  72. { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
  73. { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
  74. { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
  75. { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
  76. { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
  77. { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST },
  78. { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 },
  79. { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 },
  80. { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 },
  81. { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 },
  82. { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 },
  83. { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
  84. { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 },
  85. { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 },
  86. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO },
  87. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ },
  88. { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO },
  89. { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO },
  90. { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO },
  91. { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK },
  92. { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID },
  93. { NULL }
  94. };
  95. static unsigned int via_clock;
  96. static char *via_dma[] = { "MWDMA16", "UDMA33", "UDMA66", "UDMA100", "UDMA133" };
  97. struct via82cxxx_dev
  98. {
  99. struct via_isa_bridge *via_config;
  100. unsigned int via_80w;
  101. };
  102. /**
  103. * via_set_speed - write timing registers
  104. * @dev: PCI device
  105. * @dn: device
  106. * @timing: IDE timing data to use
  107. *
  108. * via_set_speed writes timing values to the chipset registers
  109. */
  110. static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing)
  111. {
  112. struct pci_dev *dev = hwif->pci_dev;
  113. struct via82cxxx_dev *vdev = ide_get_hwifdata(hwif);
  114. u8 t;
  115. if (~vdev->via_config->flags & VIA_BAD_AST) {
  116. pci_read_config_byte(dev, VIA_ADDRESS_SETUP, &t);
  117. t = (t & ~(3 << ((3 - dn) << 1))) | ((FIT(timing->setup, 1, 4) - 1) << ((3 - dn) << 1));
  118. pci_write_config_byte(dev, VIA_ADDRESS_SETUP, t);
  119. }
  120. pci_write_config_byte(dev, VIA_8BIT_TIMING + (1 - (dn >> 1)),
  121. ((FIT(timing->act8b, 1, 16) - 1) << 4) | (FIT(timing->rec8b, 1, 16) - 1));
  122. pci_write_config_byte(dev, VIA_DRIVE_TIMING + (3 - dn),
  123. ((FIT(timing->active, 1, 16) - 1) << 4) | (FIT(timing->recover, 1, 16) - 1));
  124. switch (vdev->via_config->flags & VIA_UDMA) {
  125. case VIA_UDMA_33: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 5) - 2)) : 0x03; break;
  126. case VIA_UDMA_66: t = timing->udma ? (0xe8 | (FIT(timing->udma, 2, 9) - 2)) : 0x0f; break;
  127. case VIA_UDMA_100: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
  128. case VIA_UDMA_133: t = timing->udma ? (0xe0 | (FIT(timing->udma, 2, 9) - 2)) : 0x07; break;
  129. default: return;
  130. }
  131. pci_write_config_byte(dev, VIA_UDMA_TIMING + (3 - dn), t);
  132. }
  133. /**
  134. * via_set_drive - configure transfer mode
  135. * @drive: Drive to set up
  136. * @speed: desired speed
  137. *
  138. * via_set_drive() computes timing values configures the drive and
  139. * the chipset to a desired transfer mode. It also can be called
  140. * by upper layers.
  141. */
  142. static int via_set_drive(ide_drive_t *drive, u8 speed)
  143. {
  144. ide_drive_t *peer = HWIF(drive)->drives + (~drive->dn & 1);
  145. struct via82cxxx_dev *vdev = ide_get_hwifdata(drive->hwif);
  146. struct ide_timing t, p;
  147. unsigned int T, UT;
  148. if (speed != XFER_PIO_SLOW)
  149. ide_config_drive_speed(drive, speed);
  150. T = 1000000000 / via_clock;
  151. switch (vdev->via_config->flags & VIA_UDMA) {
  152. case VIA_UDMA_33: UT = T; break;
  153. case VIA_UDMA_66: UT = T/2; break;
  154. case VIA_UDMA_100: UT = T/3; break;
  155. case VIA_UDMA_133: UT = T/4; break;
  156. default: UT = T;
  157. }
  158. ide_timing_compute(drive, speed, &t, T, UT);
  159. if (peer->present) {
  160. ide_timing_compute(peer, peer->current_speed, &p, T, UT);
  161. ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT);
  162. }
  163. via_set_speed(HWIF(drive), drive->dn, &t);
  164. if (!drive->init_speed)
  165. drive->init_speed = speed;
  166. drive->current_speed = speed;
  167. return 0;
  168. }
  169. /**
  170. * via82cxxx_tune_drive - PIO setup
  171. * @drive: drive to set up
  172. * @pio: mode to use (255 for 'best possible')
  173. *
  174. * A callback from the upper layers for PIO-only tuning.
  175. */
  176. static void via82cxxx_tune_drive(ide_drive_t *drive, u8 pio)
  177. {
  178. if (pio == 255) {
  179. via_set_drive(drive,
  180. ide_find_best_mode(drive, XFER_PIO | XFER_EPIO));
  181. return;
  182. }
  183. via_set_drive(drive, XFER_PIO_0 + min_t(u8, pio, 5));
  184. }
  185. /**
  186. * via82cxxx_ide_dma_check - set up for DMA if possible
  187. * @drive: IDE drive to set up
  188. *
  189. * Set up the drive for the highest supported speed considering the
  190. * driver, controller and cable
  191. */
  192. static int via82cxxx_ide_dma_check (ide_drive_t *drive)
  193. {
  194. ide_hwif_t *hwif = HWIF(drive);
  195. struct via82cxxx_dev *vdev = ide_get_hwifdata(hwif);
  196. u16 w80 = hwif->udma_four;
  197. u16 speed = ide_find_best_mode(drive,
  198. XFER_PIO | XFER_EPIO | XFER_SWDMA | XFER_MWDMA |
  199. (vdev->via_config->flags & VIA_UDMA ? XFER_UDMA : 0) |
  200. (w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_66 ? XFER_UDMA_66 : 0) |
  201. (w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_100 ? XFER_UDMA_100 : 0) |
  202. (w80 && (vdev->via_config->flags & VIA_UDMA) >= VIA_UDMA_133 ? XFER_UDMA_133 : 0));
  203. via_set_drive(drive, speed);
  204. if (drive->autodma && (speed & XFER_MODE) != XFER_PIO)
  205. return hwif->ide_dma_on(drive);
  206. return hwif->ide_dma_off_quietly(drive);
  207. }
  208. static struct via_isa_bridge *via_config_find(struct pci_dev **isa)
  209. {
  210. struct via_isa_bridge *via_config;
  211. u8 t;
  212. for (via_config = via_isa_bridges; via_config->id; via_config++)
  213. if ((*isa = pci_get_device(PCI_VENDOR_ID_VIA +
  214. !!(via_config->flags & VIA_BAD_ID),
  215. via_config->id, NULL))) {
  216. pci_read_config_byte(*isa, PCI_REVISION_ID, &t);
  217. if (t >= via_config->rev_min &&
  218. t <= via_config->rev_max)
  219. break;
  220. pci_dev_put(*isa);
  221. }
  222. return via_config;
  223. }
  224. /**
  225. * init_chipset_via82cxxx - initialization handler
  226. * @dev: PCI device
  227. * @name: Name of interface
  228. *
  229. * The initialization callback. Here we determine the IDE chip type
  230. * and initialize its drive independent registers.
  231. */
  232. static unsigned int __devinit init_chipset_via82cxxx(struct pci_dev *dev, const char *name)
  233. {
  234. struct pci_dev *isa = NULL;
  235. struct via_isa_bridge *via_config;
  236. u8 t, v;
  237. unsigned int u;
  238. /*
  239. * Find the ISA bridge to see how good the IDE is.
  240. */
  241. via_config = via_config_find(&isa);
  242. if (!via_config->id) {
  243. printk(KERN_WARNING "VP_IDE: Unknown VIA SouthBridge, disabling DMA.\n");
  244. pci_dev_put(isa);
  245. return -ENODEV;
  246. }
  247. /*
  248. * Setup or disable Clk66 if appropriate
  249. */
  250. if ((via_config->flags & VIA_UDMA) == VIA_UDMA_66) {
  251. /* Enable Clk66 */
  252. pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
  253. pci_write_config_dword(dev, VIA_UDMA_TIMING, u|0x80008);
  254. } else if (via_config->flags & VIA_BAD_CLK66) {
  255. /* Would cause trouble on 596a and 686 */
  256. pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
  257. pci_write_config_dword(dev, VIA_UDMA_TIMING, u & ~0x80008);
  258. }
  259. /*
  260. * Check whether interfaces are enabled.
  261. */
  262. pci_read_config_byte(dev, VIA_IDE_ENABLE, &v);
  263. /*
  264. * Set up FIFO sizes and thresholds.
  265. */
  266. pci_read_config_byte(dev, VIA_FIFO_CONFIG, &t);
  267. /* Disable PREQ# till DDACK# */
  268. if (via_config->flags & VIA_BAD_PREQ) {
  269. /* Would crash on 586b rev 41 */
  270. t &= 0x7f;
  271. }
  272. /* Fix FIFO split between channels */
  273. if (via_config->flags & VIA_SET_FIFO) {
  274. t &= (t & 0x9f);
  275. switch (v & 3) {
  276. case 2: t |= 0x00; break; /* 16 on primary */
  277. case 1: t |= 0x60; break; /* 16 on secondary */
  278. case 3: t |= 0x20; break; /* 8 pri 8 sec */
  279. }
  280. }
  281. pci_write_config_byte(dev, VIA_FIFO_CONFIG, t);
  282. /*
  283. * Determine system bus clock.
  284. */
  285. via_clock = system_bus_clock() * 1000;
  286. switch (via_clock) {
  287. case 33000: via_clock = 33333; break;
  288. case 37000: via_clock = 37500; break;
  289. case 41000: via_clock = 41666; break;
  290. }
  291. if (via_clock < 20000 || via_clock > 50000) {
  292. printk(KERN_WARNING "VP_IDE: User given PCI clock speed "
  293. "impossible (%d), using 33 MHz instead.\n", via_clock);
  294. printk(KERN_WARNING "VP_IDE: Use ide0=ata66 if you want "
  295. "to assume 80-wire cable.\n");
  296. via_clock = 33333;
  297. }
  298. /*
  299. * Print the boot message.
  300. */
  301. pci_read_config_byte(isa, PCI_REVISION_ID, &t);
  302. printk(KERN_INFO "VP_IDE: VIA %s (rev %02x) IDE %s "
  303. "controller on pci%s\n",
  304. via_config->name, t,
  305. via_dma[via_config->flags & VIA_UDMA],
  306. pci_name(dev));
  307. pci_dev_put(isa);
  308. return 0;
  309. }
  310. /*
  311. * Check and handle 80-wire cable presence
  312. */
  313. static void __devinit via_cable_detect(struct pci_dev *dev, struct via82cxxx_dev *vdev)
  314. {
  315. unsigned int u;
  316. int i;
  317. pci_read_config_dword(dev, VIA_UDMA_TIMING, &u);
  318. switch (vdev->via_config->flags & VIA_UDMA) {
  319. case VIA_UDMA_66:
  320. for (i = 24; i >= 0; i -= 8)
  321. if (((u >> (i & 16)) & 8) &&
  322. ((u >> i) & 0x20) &&
  323. (((u >> i) & 7) < 2)) {
  324. /*
  325. * 2x PCI clock and
  326. * UDMA w/ < 3T/cycle
  327. */
  328. vdev->via_80w |= (1 << (1 - (i >> 4)));
  329. }
  330. break;
  331. case VIA_UDMA_100:
  332. for (i = 24; i >= 0; i -= 8)
  333. if (((u >> i) & 0x10) ||
  334. (((u >> i) & 0x20) &&
  335. (((u >> i) & 7) < 4))) {
  336. /* BIOS 80-wire bit or
  337. * UDMA w/ < 60ns/cycle
  338. */
  339. vdev->via_80w |= (1 << (1 - (i >> 4)));
  340. }
  341. break;
  342. case VIA_UDMA_133:
  343. for (i = 24; i >= 0; i -= 8)
  344. if (((u >> i) & 0x10) ||
  345. (((u >> i) & 0x20) &&
  346. (((u >> i) & 7) < 6))) {
  347. /* BIOS 80-wire bit or
  348. * UDMA w/ < 60ns/cycle
  349. */
  350. vdev->via_80w |= (1 << (1 - (i >> 4)));
  351. }
  352. break;
  353. }
  354. }
  355. static void __devinit init_hwif_via82cxxx(ide_hwif_t *hwif)
  356. {
  357. struct via82cxxx_dev *vdev = kmalloc(sizeof(struct via82cxxx_dev),
  358. GFP_KERNEL);
  359. struct pci_dev *isa = NULL;
  360. int i;
  361. if (vdev == NULL) {
  362. printk(KERN_ERR "VP_IDE: out of memory :(\n");
  363. return;
  364. }
  365. memset(vdev, 0, sizeof(struct via82cxxx_dev));
  366. ide_set_hwifdata(hwif, vdev);
  367. vdev->via_config = via_config_find(&isa);
  368. via_cable_detect(hwif->pci_dev, vdev);
  369. hwif->autodma = 0;
  370. hwif->tuneproc = &via82cxxx_tune_drive;
  371. hwif->speedproc = &via_set_drive;
  372. #if defined(CONFIG_PPC_CHRP) && defined(CONFIG_PPC32)
  373. if(machine_is(chrp) && _chrp_type == _CHRP_Pegasos) {
  374. hwif->irq = hwif->channel ? 15 : 14;
  375. }
  376. #endif
  377. for (i = 0; i < 2; i++) {
  378. hwif->drives[i].io_32bit = 1;
  379. hwif->drives[i].unmask = (vdev->via_config->flags & VIA_NO_UNMASK) ? 0 : 1;
  380. hwif->drives[i].autotune = 1;
  381. hwif->drives[i].dn = hwif->channel * 2 + i;
  382. }
  383. if (!hwif->dma_base)
  384. return;
  385. hwif->atapi_dma = 1;
  386. hwif->ultra_mask = 0x7f;
  387. hwif->mwdma_mask = 0x07;
  388. hwif->swdma_mask = 0x07;
  389. if (!hwif->udma_four)
  390. hwif->udma_four = (vdev->via_80w >> hwif->channel) & 1;
  391. hwif->ide_dma_check = &via82cxxx_ide_dma_check;
  392. if (!noautodma)
  393. hwif->autodma = 1;
  394. hwif->drives[0].autodma = hwif->autodma;
  395. hwif->drives[1].autodma = hwif->autodma;
  396. }
  397. static ide_pci_device_t via82cxxx_chipsets[] __devinitdata = {
  398. { /* 0 */
  399. .name = "VP_IDE",
  400. .init_chipset = init_chipset_via82cxxx,
  401. .init_hwif = init_hwif_via82cxxx,
  402. .channels = 2,
  403. .autodma = NOAUTODMA,
  404. .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}},
  405. .bootable = ON_BOARD
  406. },{ /* 1 */
  407. .name = "VP_IDE",
  408. .init_chipset = init_chipset_via82cxxx,
  409. .init_hwif = init_hwif_via82cxxx,
  410. .channels = 2,
  411. .autodma = AUTODMA,
  412. .enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
  413. .bootable = ON_BOARD,
  414. }
  415. };
  416. static int __devinit via_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  417. {
  418. return ide_setup_pci_device(dev, &via82cxxx_chipsets[id->driver_data]);
  419. }
  420. static struct pci_device_id via_pci_tbl[] = {
  421. { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  422. { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  423. { PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
  424. { 0, },
  425. };
  426. MODULE_DEVICE_TABLE(pci, via_pci_tbl);
  427. static struct pci_driver driver = {
  428. .name = "VIA_IDE",
  429. .id_table = via_pci_tbl,
  430. .probe = via_init_one,
  431. };
  432. static int via_ide_init(void)
  433. {
  434. return ide_pci_register_driver(&driver);
  435. }
  436. module_init(via_ide_init);
  437. MODULE_AUTHOR("Vojtech Pavlik, Michel Aubry, Jeff Garzik, Andre Hedrick");
  438. MODULE_DESCRIPTION("PCI driver module for VIA IDE");
  439. MODULE_LICENSE("GPL");