trm290.c 11 KB

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  1. /*
  2. * linux/drivers/ide/pci/trm290.c Version 1.02 Mar. 18, 2000
  3. *
  4. * Copyright (c) 1997-1998 Mark Lord
  5. * May be copied or modified under the terms of the GNU General Public License
  6. *
  7. * June 22, 2004 - get rid of check_region
  8. * - Jesper Juhl
  9. *
  10. */
  11. /*
  12. * This module provides support for the bus-master IDE DMA function
  13. * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
  14. * including a "Precision Instruments" board. The TRM290 pre-dates
  15. * the sff-8038 standard (ide-dma.c) by a few months, and differs
  16. * significantly enough to warrant separate routines for some functions,
  17. * while re-using others from ide-dma.c.
  18. *
  19. * EXPERIMENTAL! It works for me (a sample of one).
  20. *
  21. * Works reliably for me in DMA mode (READs only),
  22. * DMA WRITEs are disabled by default (see #define below);
  23. *
  24. * DMA is not enabled automatically for this chipset,
  25. * but can be turned on manually (with "hdparm -d1") at run time.
  26. *
  27. * I need volunteers with "spare" drives for further testing
  28. * and development, and maybe to help figure out the peculiarities.
  29. * Even knowing the registers (below), some things behave strangely.
  30. */
  31. #define TRM290_NO_DMA_WRITES /* DMA writes seem unreliable sometimes */
  32. /*
  33. * TRM-290 PCI-IDE2 Bus Master Chip
  34. * ================================
  35. * The configuration registers are addressed in normal I/O port space
  36. * and are used as follows:
  37. *
  38. * trm290_base depends on jumper settings, and is probed for by ide-dma.c
  39. *
  40. * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
  41. * bit7 must always be written as "1"
  42. * bits6-2 undefined
  43. * bit1 1=legacy_compatible_mode, 0=native_pci_mode
  44. * bit0 1=test_mode, 0=normal(default)
  45. *
  46. * trm290_base+2 when READ: status register (byte, read-only)
  47. * bits7-2 undefined
  48. * bit1 channel0 busmaster interrupt status 0=none, 1=asserted
  49. * bit0 channel0 interrupt status 0=none, 1=asserted
  50. *
  51. * trm290_base+3 Interrupt mask register
  52. * bits7-5 undefined
  53. * bit4 legacy_header: 1=present, 0=absent
  54. * bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
  55. * bit2 channel1 interrupt status 0=none, 1=asserted (read only)
  56. * bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
  57. * bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
  58. *
  59. * trm290_base+1 "CPR" Config Pointer Register (byte)
  60. * bit7 1=autoincrement CPR bits 2-0 after each access of CDR
  61. * bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
  62. * bit5 0=enabled master burst access (default), 1=disable (write only)
  63. * bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
  64. * bit3 0=primary IDE channel, 1=secondary IDE channel
  65. * bits2-0 register index for accesses through CDR port
  66. *
  67. * trm290_base+0 "CDR" Config Data Register (word)
  68. * two sets of seven config registers,
  69. * selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
  70. * each index defined below:
  71. *
  72. * Index-0 Base address register for command block (word)
  73. * defaults: 0x1f0 for primary, 0x170 for secondary
  74. *
  75. * Index-1 general config register (byte)
  76. * bit7 1=DMA enable, 0=DMA disable
  77. * bit6 1=activate IDE_RESET, 0=no action (default)
  78. * bit5 1=enable IORDY, 0=disable IORDY (default)
  79. * bit4 0=16-bit data port(default), 1=8-bit (XT) data port
  80. * bit3 interrupt polarity: 1=active_low, 0=active_high(default)
  81. * bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
  82. * bit1 bus_master_mode(?): 1=enable, 0=disable(default)
  83. * bit0 enable_io_ports: 1=enable(default), 0=disable
  84. *
  85. * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
  86. * bits7-0 bits7-0 of readahead count
  87. *
  88. * Index-3 read-ahead config register (byte, write only)
  89. * bit7 1=enable_readahead, 0=disable_readahead(default)
  90. * bit6 1=clear_FIFO, 0=no_action
  91. * bit5 undefined
  92. * bit4 mode4 timing control: 1=enable, 0=disable(default)
  93. * bit3 undefined
  94. * bit2 undefined
  95. * bits1-0 bits9-8 of read-ahead count
  96. *
  97. * Index-4 base address register for control block (word)
  98. * defaults: 0x3f6 for primary, 0x376 for secondary
  99. *
  100. * Index-5 data port timings (shared by both drives) (byte)
  101. * standard PCI "clk" (clock) counts, default value = 0xf5
  102. *
  103. * bits7-6 setup time: 00=1clk, 01=2clk, 10=3clk, 11=4clk
  104. * bits5-3 hold time: 000=1clk, 001=2clk, 010=3clk,
  105. * 011=4clk, 100=5clk, 101=6clk,
  106. * 110=8clk, 111=12clk
  107. * bits2-0 active time: 000=2clk, 001=3clk, 010=4clk,
  108. * 011=5clk, 100=6clk, 101=8clk,
  109. * 110=12clk, 111=16clk
  110. *
  111. * Index-6 command/control port timings (shared by both drives) (byte)
  112. * same layout as Index-5, default value = 0xde
  113. *
  114. * Suggested CDR programming for PIO mode0 (600ns):
  115. * 0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde ; primary
  116. * 0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde ; secondary
  117. *
  118. * Suggested CDR programming for PIO mode3 (180ns):
  119. * 0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde ; primary
  120. * 0x0170,0x21,0xff,0x80,0x0376,0x09,0xde ; secondary
  121. *
  122. * Suggested CDR programming for PIO mode4 (120ns):
  123. * 0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde ; primary
  124. * 0x0170,0x21,0xff,0x80,0x0376,0x00,0xde ; secondary
  125. *
  126. */
  127. #include <linux/types.h>
  128. #include <linux/module.h>
  129. #include <linux/kernel.h>
  130. #include <linux/mm.h>
  131. #include <linux/ioport.h>
  132. #include <linux/interrupt.h>
  133. #include <linux/blkdev.h>
  134. #include <linux/init.h>
  135. #include <linux/hdreg.h>
  136. #include <linux/pci.h>
  137. #include <linux/delay.h>
  138. #include <linux/ide.h>
  139. #include <asm/io.h>
  140. static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
  141. {
  142. ide_hwif_t *hwif = HWIF(drive);
  143. u16 reg = 0;
  144. unsigned long flags;
  145. /* select PIO or DMA */
  146. reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
  147. local_irq_save(flags);
  148. if (reg != hwif->select_data) {
  149. hwif->select_data = reg;
  150. /* set PIO/DMA */
  151. hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
  152. hwif->OUTW(reg & 0xff, hwif->config_data);
  153. }
  154. /* enable IRQ if not probing */
  155. if (drive->present) {
  156. reg = hwif->INW(hwif->config_data + 3);
  157. reg &= 0x13;
  158. reg &= ~(1 << hwif->channel);
  159. hwif->OUTW(reg, hwif->config_data+3);
  160. }
  161. local_irq_restore(flags);
  162. }
  163. static void trm290_selectproc (ide_drive_t *drive)
  164. {
  165. trm290_prepare_drive(drive, drive->using_dma);
  166. }
  167. #ifdef CONFIG_BLK_DEV_IDEDMA
  168. static void trm290_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
  169. {
  170. ide_hwif_t *hwif = HWIF(drive);
  171. BUG_ON(HWGROUP(drive)->handler != NULL); /* paranoia check */
  172. ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
  173. /* issue cmd to drive */
  174. hwif->OUTB(command, IDE_COMMAND_REG);
  175. }
  176. static int trm290_ide_dma_setup(ide_drive_t *drive)
  177. {
  178. ide_hwif_t *hwif = drive->hwif;
  179. struct request *rq = hwif->hwgroup->rq;
  180. unsigned int count, rw;
  181. if (rq_data_dir(rq)) {
  182. #ifdef TRM290_NO_DMA_WRITES
  183. /* always use PIO for writes */
  184. trm290_prepare_drive(drive, 0); /* select PIO xfer */
  185. return 1;
  186. #endif
  187. rw = 1;
  188. } else
  189. rw = 2;
  190. if (!(count = ide_build_dmatable(drive, rq))) {
  191. /* try PIO instead of DMA */
  192. trm290_prepare_drive(drive, 0); /* select PIO xfer */
  193. return 1;
  194. }
  195. /* select DMA xfer */
  196. trm290_prepare_drive(drive, 1);
  197. hwif->OUTL(hwif->dmatable_dma|rw, hwif->dma_command);
  198. drive->waiting_for_dma = 1;
  199. /* start DMA */
  200. hwif->OUTW((count * 2) - 1, hwif->dma_status);
  201. return 0;
  202. }
  203. static void trm290_ide_dma_start(ide_drive_t *drive)
  204. {
  205. }
  206. static int trm290_ide_dma_end (ide_drive_t *drive)
  207. {
  208. ide_hwif_t *hwif = HWIF(drive);
  209. u16 status = 0;
  210. drive->waiting_for_dma = 0;
  211. /* purge DMA mappings */
  212. ide_destroy_dmatable(drive);
  213. status = hwif->INW(hwif->dma_status);
  214. return (status != 0x00ff);
  215. }
  216. static int trm290_ide_dma_test_irq (ide_drive_t *drive)
  217. {
  218. ide_hwif_t *hwif = HWIF(drive);
  219. u16 status = 0;
  220. status = hwif->INW(hwif->dma_status);
  221. return (status == 0x00ff);
  222. }
  223. #endif /* CONFIG_BLK_DEV_IDEDMA */
  224. /*
  225. * Invoked from ide-dma.c at boot time.
  226. */
  227. static void __devinit init_hwif_trm290(ide_hwif_t *hwif)
  228. {
  229. unsigned int cfgbase = 0;
  230. unsigned long flags;
  231. u8 reg = 0;
  232. struct pci_dev *dev = hwif->pci_dev;
  233. hwif->no_lba48 = 1;
  234. hwif->chipset = ide_trm290;
  235. cfgbase = pci_resource_start(dev, 4);
  236. if ((dev->class & 5) && cfgbase) {
  237. hwif->config_data = cfgbase;
  238. printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n",
  239. hwif->config_data);
  240. } else {
  241. hwif->config_data = 0x3df0;
  242. printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n",
  243. hwif->config_data);
  244. }
  245. local_irq_save(flags);
  246. /* put config reg into first byte of hwif->select_data */
  247. hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
  248. /* select PIO as default */
  249. hwif->select_data = 0x21;
  250. hwif->OUTB(hwif->select_data, hwif->config_data);
  251. /* get IRQ info */
  252. reg = hwif->INB(hwif->config_data+3);
  253. /* mask IRQs for both ports */
  254. reg = (reg & 0x10) | 0x03;
  255. hwif->OUTB(reg, hwif->config_data+3);
  256. local_irq_restore(flags);
  257. if ((reg & 0x10))
  258. /* legacy mode */
  259. hwif->irq = hwif->channel ? 15 : 14;
  260. else if (!hwif->irq && hwif->mate && hwif->mate->irq)
  261. /* sharing IRQ with mate */
  262. hwif->irq = hwif->mate->irq;
  263. ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
  264. #ifdef CONFIG_BLK_DEV_IDEDMA
  265. hwif->dma_setup = &trm290_ide_dma_setup;
  266. hwif->dma_exec_cmd = &trm290_ide_dma_exec_cmd;
  267. hwif->dma_start = &trm290_ide_dma_start;
  268. hwif->ide_dma_end = &trm290_ide_dma_end;
  269. hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq;
  270. #endif /* CONFIG_BLK_DEV_IDEDMA */
  271. hwif->selectproc = &trm290_selectproc;
  272. hwif->autodma = 0; /* play it safe for now */
  273. hwif->drives[0].autodma = hwif->autodma;
  274. hwif->drives[1].autodma = hwif->autodma;
  275. #if 1
  276. {
  277. /*
  278. * My trm290-based card doesn't seem to work with all possible values
  279. * for the control basereg, so this kludge ensures that we use only
  280. * values that are known to work. Ugh. -ml
  281. */
  282. u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
  283. static u16 next_offset = 0;
  284. u8 old_mask;
  285. hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1);
  286. old = hwif->INW(hwif->config_data);
  287. old &= ~1;
  288. old_mask = hwif->INB(old+2);
  289. if (old != compat && old_mask == 0xff) {
  290. /* leave lower 10 bits untouched */
  291. compat += (next_offset += 0x400);
  292. hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
  293. hwif->OUTW(compat|1, hwif->config_data);
  294. new = hwif->INW(hwif->config_data);
  295. printk(KERN_INFO "%s: control basereg workaround: "
  296. "old=0x%04x, new=0x%04x\n",
  297. hwif->name, old, new & ~1);
  298. }
  299. }
  300. #endif
  301. }
  302. static ide_pci_device_t trm290_chipset __devinitdata = {
  303. .name = "TRM290",
  304. .init_hwif = init_hwif_trm290,
  305. .channels = 2,
  306. .autodma = NOAUTODMA,
  307. .bootable = ON_BOARD,
  308. };
  309. static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  310. {
  311. return ide_setup_pci_device(dev, &trm290_chipset);
  312. }
  313. static struct pci_device_id trm290_pci_tbl[] = {
  314. { PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  315. { 0, },
  316. };
  317. MODULE_DEVICE_TABLE(pci, trm290_pci_tbl);
  318. static struct pci_driver driver = {
  319. .name = "TRM290_IDE",
  320. .id_table = trm290_pci_tbl,
  321. .probe = trm290_init_one,
  322. };
  323. static int trm290_ide_init(void)
  324. {
  325. return ide_pci_register_driver(&driver);
  326. }
  327. module_init(trm290_ide_init);
  328. MODULE_AUTHOR("Mark Lord");
  329. MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
  330. MODULE_LICENSE("GPL");