ns87415.c 8.3 KB

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  1. /*
  2. * linux/drivers/ide/pci/ns87415.c Version 2.00 Sep. 10, 2002
  3. *
  4. * Copyright (C) 1997-1998 Mark Lord <mlord@pobox.com>
  5. * Copyright (C) 1998 Eddie C. Dost <ecd@skynet.be>
  6. * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org>
  7. * Copyright (C) 2004 Grant Grundler <grundler at parisc-linux.org>
  8. *
  9. * Inspired by an earlier effort from David S. Miller <davem@redhat.com>
  10. */
  11. #include <linux/module.h>
  12. #include <linux/types.h>
  13. #include <linux/kernel.h>
  14. #include <linux/timer.h>
  15. #include <linux/mm.h>
  16. #include <linux/ioport.h>
  17. #include <linux/interrupt.h>
  18. #include <linux/blkdev.h>
  19. #include <linux/hdreg.h>
  20. #include <linux/pci.h>
  21. #include <linux/delay.h>
  22. #include <linux/ide.h>
  23. #include <linux/init.h>
  24. #include <asm/io.h>
  25. #ifdef CONFIG_SUPERIO
  26. /* SUPERIO 87560 is a PoS chip that NatSem denies exists.
  27. * Unfortunately, it's built-in on all Astro-based PA-RISC workstations
  28. * which use the integrated NS87514 cell for CD-ROM support.
  29. * i.e we have to support for CD-ROM installs.
  30. * See drivers/parisc/superio.c for more gory details.
  31. */
  32. #include <asm/superio.h>
  33. static unsigned long superio_ide_status[2];
  34. static unsigned long superio_ide_select[2];
  35. static unsigned long superio_ide_dma_status[2];
  36. #define SUPERIO_IDE_MAX_RETRIES 25
  37. /* Because of a defect in Super I/O, all reads of the PCI DMA status
  38. * registers, IDE status register and the IDE select register need to be
  39. * retried
  40. */
  41. static u8 superio_ide_inb (unsigned long port)
  42. {
  43. if (port == superio_ide_status[0] ||
  44. port == superio_ide_status[1] ||
  45. port == superio_ide_select[0] ||
  46. port == superio_ide_select[1] ||
  47. port == superio_ide_dma_status[0] ||
  48. port == superio_ide_dma_status[1]) {
  49. u8 tmp;
  50. int retries = SUPERIO_IDE_MAX_RETRIES;
  51. /* printk(" [ reading port 0x%x with retry ] ", port); */
  52. do {
  53. tmp = inb(port);
  54. if (tmp == 0)
  55. udelay(50);
  56. } while (tmp == 0 && retries-- > 0);
  57. return tmp;
  58. }
  59. return inb(port);
  60. }
  61. static void __devinit superio_ide_init_iops (struct hwif_s *hwif)
  62. {
  63. u32 base, dmabase;
  64. u8 tmp;
  65. struct pci_dev *pdev = hwif->pci_dev;
  66. u8 port = hwif->channel;
  67. base = pci_resource_start(pdev, port * 2) & ~3;
  68. dmabase = pci_resource_start(pdev, 4) & ~3;
  69. superio_ide_status[port] = base + IDE_STATUS_OFFSET;
  70. superio_ide_select[port] = base + IDE_SELECT_OFFSET;
  71. superio_ide_dma_status[port] = dmabase + (!port ? 2 : 0xa);
  72. /* Clear error/interrupt, enable dma */
  73. tmp = superio_ide_inb(superio_ide_dma_status[port]);
  74. outb(tmp | 0x66, superio_ide_dma_status[port]);
  75. /* We need to override inb to workaround a SuperIO errata */
  76. hwif->INB = superio_ide_inb;
  77. }
  78. static void __devinit init_iops_ns87415(ide_hwif_t *hwif)
  79. {
  80. if (PCI_SLOT(hwif->pci_dev->devfn) == 0xE) {
  81. /* Built-in - assume it's under superio. */
  82. superio_ide_init_iops(hwif);
  83. }
  84. }
  85. #endif
  86. static unsigned int ns87415_count = 0, ns87415_control[MAX_HWIFS] = { 0 };
  87. /*
  88. * This routine either enables/disables (according to drive->present)
  89. * the IRQ associated with the port (HWIF(drive)),
  90. * and selects either PIO or DMA handshaking for the next I/O operation.
  91. */
  92. static void ns87415_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
  93. {
  94. ide_hwif_t *hwif = HWIF(drive);
  95. unsigned int bit, other, new, *old = (unsigned int *) hwif->select_data;
  96. struct pci_dev *dev = hwif->pci_dev;
  97. unsigned long flags;
  98. local_irq_save(flags);
  99. new = *old;
  100. /* Adjust IRQ enable bit */
  101. bit = 1 << (8 + hwif->channel);
  102. new = drive->present ? (new & ~bit) : (new | bit);
  103. /* Select PIO or DMA, DMA may only be selected for one drive/channel. */
  104. bit = 1 << (20 + drive->select.b.unit + (hwif->channel << 1));
  105. other = 1 << (20 + (1 - drive->select.b.unit) + (hwif->channel << 1));
  106. new = use_dma ? ((new & ~other) | bit) : (new & ~bit);
  107. if (new != *old) {
  108. unsigned char stat;
  109. /*
  110. * Don't change DMA engine settings while Write Buffers
  111. * are busy.
  112. */
  113. (void) pci_read_config_byte(dev, 0x43, &stat);
  114. while (stat & 0x03) {
  115. udelay(1);
  116. (void) pci_read_config_byte(dev, 0x43, &stat);
  117. }
  118. *old = new;
  119. (void) pci_write_config_dword(dev, 0x40, new);
  120. /*
  121. * And let things settle...
  122. */
  123. udelay(10);
  124. }
  125. local_irq_restore(flags);
  126. }
  127. static void ns87415_selectproc (ide_drive_t *drive)
  128. {
  129. ns87415_prepare_drive (drive, drive->using_dma);
  130. }
  131. static int ns87415_ide_dma_end (ide_drive_t *drive)
  132. {
  133. ide_hwif_t *hwif = HWIF(drive);
  134. u8 dma_stat = 0, dma_cmd = 0;
  135. drive->waiting_for_dma = 0;
  136. dma_stat = hwif->INB(hwif->dma_status);
  137. /* get dma command mode */
  138. dma_cmd = hwif->INB(hwif->dma_command);
  139. /* stop DMA */
  140. hwif->OUTB(dma_cmd & ~1, hwif->dma_command);
  141. /* from ERRATA: clear the INTR & ERROR bits */
  142. dma_cmd = hwif->INB(hwif->dma_command);
  143. hwif->OUTB(dma_cmd|6, hwif->dma_command);
  144. /* and free any DMA resources */
  145. ide_destroy_dmatable(drive);
  146. /* verify good DMA status */
  147. return (dma_stat & 7) != 4;
  148. }
  149. static int ns87415_ide_dma_setup(ide_drive_t *drive)
  150. {
  151. /* select DMA xfer */
  152. ns87415_prepare_drive(drive, 1);
  153. if (!ide_dma_setup(drive))
  154. return 0;
  155. /* DMA failed: select PIO xfer */
  156. ns87415_prepare_drive(drive, 0);
  157. return 1;
  158. }
  159. static int ns87415_ide_dma_check (ide_drive_t *drive)
  160. {
  161. if (drive->media != ide_disk)
  162. return HWIF(drive)->ide_dma_off_quietly(drive);
  163. return __ide_dma_check(drive);
  164. }
  165. static void __devinit init_hwif_ns87415 (ide_hwif_t *hwif)
  166. {
  167. struct pci_dev *dev = hwif->pci_dev;
  168. unsigned int ctrl, using_inta;
  169. u8 progif;
  170. #ifdef __sparc_v9__
  171. int timeout;
  172. u8 stat;
  173. #endif
  174. hwif->autodma = 0;
  175. hwif->selectproc = &ns87415_selectproc;
  176. /*
  177. * We cannot probe for IRQ: both ports share common IRQ on INTA.
  178. * Also, leave IRQ masked during drive probing, to prevent infinite
  179. * interrupts from a potentially floating INTA..
  180. *
  181. * IRQs get unmasked in selectproc when drive is first used.
  182. */
  183. (void) pci_read_config_dword(dev, 0x40, &ctrl);
  184. (void) pci_read_config_byte(dev, 0x09, &progif);
  185. /* is irq in "native" mode? */
  186. using_inta = progif & (1 << (hwif->channel << 1));
  187. if (!using_inta)
  188. using_inta = ctrl & (1 << (4 + hwif->channel));
  189. if (hwif->mate) {
  190. hwif->select_data = hwif->mate->select_data;
  191. } else {
  192. hwif->select_data = (unsigned long)
  193. &ns87415_control[ns87415_count++];
  194. ctrl |= (1 << 8) | (1 << 9); /* mask both IRQs */
  195. if (using_inta)
  196. ctrl &= ~(1 << 6); /* unmask INTA */
  197. *((unsigned int *)hwif->select_data) = ctrl;
  198. (void) pci_write_config_dword(dev, 0x40, ctrl);
  199. /*
  200. * Set prefetch size to 512 bytes for both ports,
  201. * but don't turn on/off prefetching here.
  202. */
  203. pci_write_config_byte(dev, 0x55, 0xee);
  204. #ifdef __sparc_v9__
  205. /*
  206. * XXX: Reset the device, if we don't it will not respond
  207. * to SELECT_DRIVE() properly during first probe_hwif().
  208. */
  209. timeout = 10000;
  210. hwif->OUTB(12, hwif->io_ports[IDE_CONTROL_OFFSET]);
  211. udelay(10);
  212. hwif->OUTB(8, hwif->io_ports[IDE_CONTROL_OFFSET]);
  213. do {
  214. udelay(50);
  215. stat = hwif->INB(hwif->io_ports[IDE_STATUS_OFFSET]);
  216. if (stat == 0xff)
  217. break;
  218. } while ((stat & BUSY_STAT) && --timeout);
  219. #endif
  220. }
  221. if (!using_inta)
  222. hwif->irq = ide_default_irq(hwif->io_ports[IDE_DATA_OFFSET]);
  223. else if (!hwif->irq && hwif->mate && hwif->mate->irq)
  224. hwif->irq = hwif->mate->irq; /* share IRQ with mate */
  225. if (!hwif->dma_base)
  226. return;
  227. hwif->OUTB(0x60, hwif->dma_status);
  228. hwif->dma_setup = &ns87415_ide_dma_setup;
  229. hwif->ide_dma_check = &ns87415_ide_dma_check;
  230. hwif->ide_dma_end = &ns87415_ide_dma_end;
  231. if (!noautodma)
  232. hwif->autodma = 1;
  233. hwif->drives[0].autodma = hwif->autodma;
  234. hwif->drives[1].autodma = hwif->autodma;
  235. }
  236. static ide_pci_device_t ns87415_chipset __devinitdata = {
  237. .name = "NS87415",
  238. #ifdef CONFIG_SUPERIO
  239. .init_iops = init_iops_ns87415,
  240. #endif
  241. .init_hwif = init_hwif_ns87415,
  242. .channels = 2,
  243. .autodma = AUTODMA,
  244. .bootable = ON_BOARD,
  245. };
  246. static int __devinit ns87415_init_one(struct pci_dev *dev, const struct pci_device_id *id)
  247. {
  248. return ide_setup_pci_device(dev, &ns87415_chipset);
  249. }
  250. static struct pci_device_id ns87415_pci_tbl[] = {
  251. { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_87415, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
  252. { 0, },
  253. };
  254. MODULE_DEVICE_TABLE(pci, ns87415_pci_tbl);
  255. static struct pci_driver driver = {
  256. .name = "NS87415_IDE",
  257. .id_table = ns87415_pci_tbl,
  258. .probe = ns87415_init_one,
  259. };
  260. static int ns87415_ide_init(void)
  261. {
  262. return ide_pci_register_driver(&driver);
  263. }
  264. module_init(ns87415_ide_init);
  265. MODULE_AUTHOR("Mark Lord, Eddie Dost, Andre Hedrick");
  266. MODULE_DESCRIPTION("PCI driver module for NS87415 IDE");
  267. MODULE_LICENSE("GPL");