i2c-s3c2410.c 20 KB

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  1. /* linux/drivers/i2c/busses/i2c-s3c2410.c
  2. *
  3. * Copyright (C) 2004,2005 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2410 I2C Controller
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #include <linux/kernel.h>
  23. #include <linux/module.h>
  24. #include <linux/i2c.h>
  25. #include <linux/i2c-id.h>
  26. #include <linux/init.h>
  27. #include <linux/time.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/sched.h>
  30. #include <linux/delay.h>
  31. #include <linux/errno.h>
  32. #include <linux/err.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/clk.h>
  35. #include <asm/hardware.h>
  36. #include <asm/irq.h>
  37. #include <asm/io.h>
  38. #include <asm/arch/regs-gpio.h>
  39. #include <asm/arch/regs-iic.h>
  40. #include <asm/arch/iic.h>
  41. /* i2c controller state */
  42. enum s3c24xx_i2c_state {
  43. STATE_IDLE,
  44. STATE_START,
  45. STATE_READ,
  46. STATE_WRITE,
  47. STATE_STOP
  48. };
  49. struct s3c24xx_i2c {
  50. spinlock_t lock;
  51. wait_queue_head_t wait;
  52. struct i2c_msg *msg;
  53. unsigned int msg_num;
  54. unsigned int msg_idx;
  55. unsigned int msg_ptr;
  56. enum s3c24xx_i2c_state state;
  57. void __iomem *regs;
  58. struct clk *clk;
  59. struct device *dev;
  60. struct resource *irq;
  61. struct resource *ioarea;
  62. struct i2c_adapter adap;
  63. };
  64. /* default platform data to use if not supplied in the platform_device
  65. */
  66. static struct s3c2410_platform_i2c s3c24xx_i2c_default_platform = {
  67. .flags = 0,
  68. .slave_addr = 0x10,
  69. .bus_freq = 100*1000,
  70. .max_freq = 400*1000,
  71. .sda_delay = S3C2410_IICLC_SDA_DELAY5 | S3C2410_IICLC_FILTER_ON,
  72. };
  73. /* s3c24xx_i2c_is2440()
  74. *
  75. * return true is this is an s3c2440
  76. */
  77. static inline int s3c24xx_i2c_is2440(struct s3c24xx_i2c *i2c)
  78. {
  79. struct platform_device *pdev = to_platform_device(i2c->dev);
  80. return !strcmp(pdev->name, "s3c2440-i2c");
  81. }
  82. /* s3c24xx_i2c_get_platformdata
  83. *
  84. * get the platform data associated with the given device, or return
  85. * the default if there is none
  86. */
  87. static inline struct s3c2410_platform_i2c *s3c24xx_i2c_get_platformdata(struct device *dev)
  88. {
  89. if (dev->platform_data != NULL)
  90. return (struct s3c2410_platform_i2c *)dev->platform_data;
  91. return &s3c24xx_i2c_default_platform;
  92. }
  93. /* s3c24xx_i2c_master_complete
  94. *
  95. * complete the message and wake up the caller, using the given return code,
  96. * or zero to mean ok.
  97. */
  98. static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
  99. {
  100. dev_dbg(i2c->dev, "master_complete %d\n", ret);
  101. i2c->msg_ptr = 0;
  102. i2c->msg = NULL;
  103. i2c->msg_idx ++;
  104. i2c->msg_num = 0;
  105. if (ret)
  106. i2c->msg_idx = ret;
  107. wake_up(&i2c->wait);
  108. }
  109. static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
  110. {
  111. unsigned long tmp;
  112. tmp = readl(i2c->regs + S3C2410_IICCON);
  113. writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
  114. }
  115. static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
  116. {
  117. unsigned long tmp;
  118. tmp = readl(i2c->regs + S3C2410_IICCON);
  119. writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
  120. }
  121. /* irq enable/disable functions */
  122. static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
  123. {
  124. unsigned long tmp;
  125. tmp = readl(i2c->regs + S3C2410_IICCON);
  126. writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
  127. }
  128. static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
  129. {
  130. unsigned long tmp;
  131. tmp = readl(i2c->regs + S3C2410_IICCON);
  132. writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
  133. }
  134. /* s3c24xx_i2c_message_start
  135. *
  136. * put the start of a message onto the bus
  137. */
  138. static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
  139. struct i2c_msg *msg)
  140. {
  141. unsigned int addr = (msg->addr & 0x7f) << 1;
  142. unsigned long stat;
  143. unsigned long iiccon;
  144. stat = 0;
  145. stat |= S3C2410_IICSTAT_TXRXEN;
  146. if (msg->flags & I2C_M_RD) {
  147. stat |= S3C2410_IICSTAT_MASTER_RX;
  148. addr |= 1;
  149. } else
  150. stat |= S3C2410_IICSTAT_MASTER_TX;
  151. if (msg->flags & I2C_M_REV_DIR_ADDR)
  152. addr ^= 1;
  153. // todo - check for wether ack wanted or not
  154. s3c24xx_i2c_enable_ack(i2c);
  155. iiccon = readl(i2c->regs + S3C2410_IICCON);
  156. writel(stat, i2c->regs + S3C2410_IICSTAT);
  157. dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
  158. writeb(addr, i2c->regs + S3C2410_IICDS);
  159. // delay a bit and reset iiccon before setting start (per samsung)
  160. udelay(1);
  161. dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
  162. writel(iiccon, i2c->regs + S3C2410_IICCON);
  163. stat |= S3C2410_IICSTAT_START;
  164. writel(stat, i2c->regs + S3C2410_IICSTAT);
  165. }
  166. static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
  167. {
  168. unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
  169. dev_dbg(i2c->dev, "STOP\n");
  170. /* stop the transfer */
  171. iicstat &= ~ S3C2410_IICSTAT_START;
  172. writel(iicstat, i2c->regs + S3C2410_IICSTAT);
  173. i2c->state = STATE_STOP;
  174. s3c24xx_i2c_master_complete(i2c, ret);
  175. s3c24xx_i2c_disable_irq(i2c);
  176. }
  177. /* helper functions to determine the current state in the set of
  178. * messages we are sending */
  179. /* is_lastmsg()
  180. *
  181. * returns TRUE if the current message is the last in the set
  182. */
  183. static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
  184. {
  185. return i2c->msg_idx >= (i2c->msg_num - 1);
  186. }
  187. /* is_msglast
  188. *
  189. * returns TRUE if we this is the last byte in the current message
  190. */
  191. static inline int is_msglast(struct s3c24xx_i2c *i2c)
  192. {
  193. return i2c->msg_ptr == i2c->msg->len-1;
  194. }
  195. /* is_msgend
  196. *
  197. * returns TRUE if we reached the end of the current message
  198. */
  199. static inline int is_msgend(struct s3c24xx_i2c *i2c)
  200. {
  201. return i2c->msg_ptr >= i2c->msg->len;
  202. }
  203. /* i2s_s3c_irq_nextbyte
  204. *
  205. * process an interrupt and work out what to do
  206. */
  207. static int i2s_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
  208. {
  209. unsigned long tmp;
  210. unsigned char byte;
  211. int ret = 0;
  212. switch (i2c->state) {
  213. case STATE_IDLE:
  214. dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __FUNCTION__);
  215. goto out;
  216. break;
  217. case STATE_STOP:
  218. dev_err(i2c->dev, "%s: called in STATE_STOP\n", __FUNCTION__);
  219. s3c24xx_i2c_disable_irq(i2c);
  220. goto out_ack;
  221. case STATE_START:
  222. /* last thing we did was send a start condition on the
  223. * bus, or started a new i2c message
  224. */
  225. if (iicstat & S3C2410_IICSTAT_LASTBIT &&
  226. !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
  227. /* ack was not received... */
  228. dev_dbg(i2c->dev, "ack was not received\n");
  229. s3c24xx_i2c_stop(i2c, -EREMOTEIO);
  230. goto out_ack;
  231. }
  232. if (i2c->msg->flags & I2C_M_RD)
  233. i2c->state = STATE_READ;
  234. else
  235. i2c->state = STATE_WRITE;
  236. /* terminate the transfer if there is nothing to do
  237. * (used by the i2c probe to find devices */
  238. if (is_lastmsg(i2c) && i2c->msg->len == 0) {
  239. s3c24xx_i2c_stop(i2c, 0);
  240. goto out_ack;
  241. }
  242. if (i2c->state == STATE_READ)
  243. goto prepare_read;
  244. /* fall through to the write state, as we will need to
  245. * send a byte as well */
  246. case STATE_WRITE:
  247. /* we are writing data to the device... check for the
  248. * end of the message, and if so, work out what to do
  249. */
  250. retry_write:
  251. if (!is_msgend(i2c)) {
  252. byte = i2c->msg->buf[i2c->msg_ptr++];
  253. writeb(byte, i2c->regs + S3C2410_IICDS);
  254. } else if (!is_lastmsg(i2c)) {
  255. /* we need to go to the next i2c message */
  256. dev_dbg(i2c->dev, "WRITE: Next Message\n");
  257. i2c->msg_ptr = 0;
  258. i2c->msg_idx ++;
  259. i2c->msg++;
  260. /* check to see if we need to do another message */
  261. if (i2c->msg->flags & I2C_M_NOSTART) {
  262. if (i2c->msg->flags & I2C_M_RD) {
  263. /* cannot do this, the controller
  264. * forces us to send a new START
  265. * when we change direction */
  266. s3c24xx_i2c_stop(i2c, -EINVAL);
  267. }
  268. goto retry_write;
  269. } else {
  270. /* send the new start */
  271. s3c24xx_i2c_message_start(i2c, i2c->msg);
  272. i2c->state = STATE_START;
  273. }
  274. } else {
  275. /* send stop */
  276. s3c24xx_i2c_stop(i2c, 0);
  277. }
  278. break;
  279. case STATE_READ:
  280. /* we have a byte of data in the data register, do
  281. * something with it, and then work out wether we are
  282. * going to do any more read/write
  283. */
  284. if (!(i2c->msg->flags & I2C_M_IGNORE_NAK) &&
  285. !(is_msglast(i2c) && is_lastmsg(i2c))) {
  286. if (iicstat & S3C2410_IICSTAT_LASTBIT) {
  287. dev_dbg(i2c->dev, "READ: No Ack\n");
  288. s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
  289. goto out_ack;
  290. }
  291. }
  292. byte = readb(i2c->regs + S3C2410_IICDS);
  293. i2c->msg->buf[i2c->msg_ptr++] = byte;
  294. prepare_read:
  295. if (is_msglast(i2c)) {
  296. /* last byte of buffer */
  297. if (is_lastmsg(i2c))
  298. s3c24xx_i2c_disable_ack(i2c);
  299. } else if (is_msgend(i2c)) {
  300. /* ok, we've read the entire buffer, see if there
  301. * is anything else we need to do */
  302. if (is_lastmsg(i2c)) {
  303. /* last message, send stop and complete */
  304. dev_dbg(i2c->dev, "READ: Send Stop\n");
  305. s3c24xx_i2c_stop(i2c, 0);
  306. } else {
  307. /* go to the next transfer */
  308. dev_dbg(i2c->dev, "READ: Next Transfer\n");
  309. i2c->msg_ptr = 0;
  310. i2c->msg_idx++;
  311. i2c->msg++;
  312. }
  313. }
  314. break;
  315. }
  316. /* acknowlegde the IRQ and get back on with the work */
  317. out_ack:
  318. tmp = readl(i2c->regs + S3C2410_IICCON);
  319. tmp &= ~S3C2410_IICCON_IRQPEND;
  320. writel(tmp, i2c->regs + S3C2410_IICCON);
  321. out:
  322. return ret;
  323. }
  324. /* s3c24xx_i2c_irq
  325. *
  326. * top level IRQ servicing routine
  327. */
  328. static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
  329. {
  330. struct s3c24xx_i2c *i2c = dev_id;
  331. unsigned long status;
  332. unsigned long tmp;
  333. status = readl(i2c->regs + S3C2410_IICSTAT);
  334. if (status & S3C2410_IICSTAT_ARBITR) {
  335. // deal with arbitration loss
  336. dev_err(i2c->dev, "deal with arbitration loss\n");
  337. }
  338. if (i2c->state == STATE_IDLE) {
  339. dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
  340. tmp = readl(i2c->regs + S3C2410_IICCON);
  341. tmp &= ~S3C2410_IICCON_IRQPEND;
  342. writel(tmp, i2c->regs + S3C2410_IICCON);
  343. goto out;
  344. }
  345. /* pretty much this leaves us with the fact that we've
  346. * transmitted or received whatever byte we last sent */
  347. i2s_s3c_irq_nextbyte(i2c, status);
  348. out:
  349. return IRQ_HANDLED;
  350. }
  351. /* s3c24xx_i2c_set_master
  352. *
  353. * get the i2c bus for a master transaction
  354. */
  355. static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
  356. {
  357. unsigned long iicstat;
  358. int timeout = 400;
  359. while (timeout-- > 0) {
  360. iicstat = readl(i2c->regs + S3C2410_IICSTAT);
  361. if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
  362. return 0;
  363. msleep(1);
  364. }
  365. dev_dbg(i2c->dev, "timeout: GPEDAT is %08x\n",
  366. __raw_readl(S3C2410_GPEDAT));
  367. return -ETIMEDOUT;
  368. }
  369. /* s3c24xx_i2c_doxfer
  370. *
  371. * this starts an i2c transfer
  372. */
  373. static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c, struct i2c_msg *msgs, int num)
  374. {
  375. unsigned long timeout;
  376. int ret;
  377. ret = s3c24xx_i2c_set_master(i2c);
  378. if (ret != 0) {
  379. dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
  380. ret = -EAGAIN;
  381. goto out;
  382. }
  383. spin_lock_irq(&i2c->lock);
  384. i2c->msg = msgs;
  385. i2c->msg_num = num;
  386. i2c->msg_ptr = 0;
  387. i2c->msg_idx = 0;
  388. i2c->state = STATE_START;
  389. s3c24xx_i2c_enable_irq(i2c);
  390. s3c24xx_i2c_message_start(i2c, msgs);
  391. spin_unlock_irq(&i2c->lock);
  392. timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
  393. ret = i2c->msg_idx;
  394. /* having these next two as dev_err() makes life very
  395. * noisy when doing an i2cdetect */
  396. if (timeout == 0)
  397. dev_dbg(i2c->dev, "timeout\n");
  398. else if (ret != num)
  399. dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
  400. /* ensure the stop has been through the bus */
  401. msleep(1);
  402. out:
  403. return ret;
  404. }
  405. /* s3c24xx_i2c_xfer
  406. *
  407. * first port of call from the i2c bus code when an message needs
  408. * transferring across the i2c bus.
  409. */
  410. static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
  411. struct i2c_msg *msgs, int num)
  412. {
  413. struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
  414. int retry;
  415. int ret;
  416. for (retry = 0; retry < adap->retries; retry++) {
  417. ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
  418. if (ret != -EAGAIN)
  419. return ret;
  420. dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
  421. udelay(100);
  422. }
  423. return -EREMOTEIO;
  424. }
  425. /* declare our i2c functionality */
  426. static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
  427. {
  428. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_PROTOCOL_MANGLING;
  429. }
  430. /* i2c bus registration info */
  431. static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
  432. .master_xfer = s3c24xx_i2c_xfer,
  433. .functionality = s3c24xx_i2c_func,
  434. };
  435. static struct s3c24xx_i2c s3c24xx_i2c = {
  436. .lock = SPIN_LOCK_UNLOCKED,
  437. .wait = __WAIT_QUEUE_HEAD_INITIALIZER(s3c24xx_i2c.wait),
  438. .adap = {
  439. .name = "s3c2410-i2c",
  440. .owner = THIS_MODULE,
  441. .algo = &s3c24xx_i2c_algorithm,
  442. .retries = 2,
  443. .class = I2C_CLASS_HWMON,
  444. },
  445. };
  446. /* s3c24xx_i2c_calcdivisor
  447. *
  448. * return the divisor settings for a given frequency
  449. */
  450. static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
  451. unsigned int *div1, unsigned int *divs)
  452. {
  453. unsigned int calc_divs = clkin / wanted;
  454. unsigned int calc_div1;
  455. if (calc_divs > (16*16))
  456. calc_div1 = 512;
  457. else
  458. calc_div1 = 16;
  459. calc_divs += calc_div1-1;
  460. calc_divs /= calc_div1;
  461. if (calc_divs == 0)
  462. calc_divs = 1;
  463. if (calc_divs > 17)
  464. calc_divs = 17;
  465. *divs = calc_divs;
  466. *div1 = calc_div1;
  467. return clkin / (calc_divs * calc_div1);
  468. }
  469. /* freq_acceptable
  470. *
  471. * test wether a frequency is within the acceptable range of error
  472. */
  473. static inline int freq_acceptable(unsigned int freq, unsigned int wanted)
  474. {
  475. int diff = freq - wanted;
  476. return (diff >= -2 && diff <= 2);
  477. }
  478. /* s3c24xx_i2c_getdivisor
  479. *
  480. * work out a divisor for the user requested frequency setting,
  481. * either by the requested frequency, or scanning the acceptable
  482. * range of frequencies until something is found
  483. */
  484. static int s3c24xx_i2c_getdivisor(struct s3c24xx_i2c *i2c,
  485. struct s3c2410_platform_i2c *pdata,
  486. unsigned long *iicon,
  487. unsigned int *got)
  488. {
  489. unsigned long clkin = clk_get_rate(i2c->clk);
  490. unsigned int divs, div1;
  491. int freq;
  492. int start, end;
  493. clkin /= 1000; /* clkin now in KHz */
  494. dev_dbg(i2c->dev, "pdata %p, freq %lu %lu..%lu\n",
  495. pdata, pdata->bus_freq, pdata->min_freq, pdata->max_freq);
  496. if (pdata->bus_freq != 0) {
  497. freq = s3c24xx_i2c_calcdivisor(clkin, pdata->bus_freq/1000,
  498. &div1, &divs);
  499. if (freq_acceptable(freq, pdata->bus_freq/1000))
  500. goto found;
  501. }
  502. /* ok, we may have to search for something suitable... */
  503. start = (pdata->max_freq == 0) ? pdata->bus_freq : pdata->max_freq;
  504. end = pdata->min_freq;
  505. start /= 1000;
  506. end /= 1000;
  507. /* search loop... */
  508. for (; start > end; start--) {
  509. freq = s3c24xx_i2c_calcdivisor(clkin, start, &div1, &divs);
  510. if (freq_acceptable(freq, start))
  511. goto found;
  512. }
  513. /* cannot find frequency spec */
  514. return -EINVAL;
  515. found:
  516. *got = freq;
  517. *iicon |= (divs-1);
  518. *iicon |= (div1 == 512) ? S3C2410_IICCON_TXDIV_512 : 0;
  519. return 0;
  520. }
  521. /* s3c24xx_i2c_init
  522. *
  523. * initialise the controller, set the IO lines and frequency
  524. */
  525. static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
  526. {
  527. unsigned long iicon = S3C2410_IICCON_IRQEN | S3C2410_IICCON_ACKEN;
  528. struct s3c2410_platform_i2c *pdata;
  529. unsigned int freq;
  530. /* get the plafrom data */
  531. pdata = s3c24xx_i2c_get_platformdata(i2c->adap.dev.parent);
  532. /* inititalise the gpio */
  533. s3c2410_gpio_cfgpin(S3C2410_GPE15, S3C2410_GPE15_IICSDA);
  534. s3c2410_gpio_cfgpin(S3C2410_GPE14, S3C2410_GPE14_IICSCL);
  535. /* write slave address */
  536. writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
  537. dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
  538. /* we need to work out the divisors for the clock... */
  539. if (s3c24xx_i2c_getdivisor(i2c, pdata, &iicon, &freq) != 0) {
  540. dev_err(i2c->dev, "cannot meet bus frequency required\n");
  541. return -EINVAL;
  542. }
  543. /* todo - check that the i2c lines aren't being dragged anywhere */
  544. dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
  545. dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02lx\n", iicon);
  546. writel(iicon, i2c->regs + S3C2410_IICCON);
  547. /* check for s3c2440 i2c controller */
  548. if (s3c24xx_i2c_is2440(i2c)) {
  549. dev_dbg(i2c->dev, "S3C2440_IICLC=%08x\n", pdata->sda_delay);
  550. writel(pdata->sda_delay, i2c->regs + S3C2440_IICLC);
  551. }
  552. return 0;
  553. }
  554. static void s3c24xx_i2c_free(struct s3c24xx_i2c *i2c)
  555. {
  556. if (i2c->clk != NULL && !IS_ERR(i2c->clk)) {
  557. clk_disable(i2c->clk);
  558. clk_put(i2c->clk);
  559. i2c->clk = NULL;
  560. }
  561. if (i2c->regs != NULL) {
  562. iounmap(i2c->regs);
  563. i2c->regs = NULL;
  564. }
  565. if (i2c->ioarea != NULL) {
  566. release_resource(i2c->ioarea);
  567. kfree(i2c->ioarea);
  568. i2c->ioarea = NULL;
  569. }
  570. }
  571. /* s3c24xx_i2c_probe
  572. *
  573. * called by the bus driver when a suitable device is found
  574. */
  575. static int s3c24xx_i2c_probe(struct platform_device *pdev)
  576. {
  577. struct s3c24xx_i2c *i2c = &s3c24xx_i2c;
  578. struct resource *res;
  579. int ret;
  580. /* find the clock and enable it */
  581. i2c->dev = &pdev->dev;
  582. i2c->clk = clk_get(&pdev->dev, "i2c");
  583. if (IS_ERR(i2c->clk)) {
  584. dev_err(&pdev->dev, "cannot get clock\n");
  585. ret = -ENOENT;
  586. goto out;
  587. }
  588. dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
  589. clk_enable(i2c->clk);
  590. /* map the registers */
  591. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  592. if (res == NULL) {
  593. dev_err(&pdev->dev, "cannot find IO resource\n");
  594. ret = -ENOENT;
  595. goto out;
  596. }
  597. i2c->ioarea = request_mem_region(res->start, (res->end-res->start)+1,
  598. pdev->name);
  599. if (i2c->ioarea == NULL) {
  600. dev_err(&pdev->dev, "cannot request IO\n");
  601. ret = -ENXIO;
  602. goto out;
  603. }
  604. i2c->regs = ioremap(res->start, (res->end-res->start)+1);
  605. if (i2c->regs == NULL) {
  606. dev_err(&pdev->dev, "cannot map IO\n");
  607. ret = -ENXIO;
  608. goto out;
  609. }
  610. dev_dbg(&pdev->dev, "registers %p (%p, %p)\n", i2c->regs, i2c->ioarea, res);
  611. /* setup info block for the i2c core */
  612. i2c->adap.algo_data = i2c;
  613. i2c->adap.dev.parent = &pdev->dev;
  614. /* initialise the i2c controller */
  615. ret = s3c24xx_i2c_init(i2c);
  616. if (ret != 0)
  617. goto out;
  618. /* find the IRQ for this unit (note, this relies on the init call to
  619. * ensure no current IRQs pending
  620. */
  621. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  622. if (res == NULL) {
  623. dev_err(&pdev->dev, "cannot find IRQ\n");
  624. ret = -ENOENT;
  625. goto out;
  626. }
  627. ret = request_irq(res->start, s3c24xx_i2c_irq, IRQF_DISABLED,
  628. pdev->name, i2c);
  629. if (ret != 0) {
  630. dev_err(&pdev->dev, "cannot claim IRQ\n");
  631. goto out;
  632. }
  633. i2c->irq = res;
  634. dev_dbg(&pdev->dev, "irq resource %p (%ld)\n", res, res->start);
  635. ret = i2c_add_adapter(&i2c->adap);
  636. if (ret < 0) {
  637. dev_err(&pdev->dev, "failed to add bus to i2c core\n");
  638. goto out;
  639. }
  640. platform_set_drvdata(pdev, i2c);
  641. dev_info(&pdev->dev, "%s: S3C I2C adapter\n", i2c->adap.dev.bus_id);
  642. out:
  643. if (ret < 0)
  644. s3c24xx_i2c_free(i2c);
  645. return ret;
  646. }
  647. /* s3c24xx_i2c_remove
  648. *
  649. * called when device is removed from the bus
  650. */
  651. static int s3c24xx_i2c_remove(struct platform_device *pdev)
  652. {
  653. struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
  654. if (i2c != NULL) {
  655. s3c24xx_i2c_free(i2c);
  656. platform_set_drvdata(pdev, NULL);
  657. }
  658. return 0;
  659. }
  660. #ifdef CONFIG_PM
  661. static int s3c24xx_i2c_resume(struct platform_device *dev)
  662. {
  663. struct s3c24xx_i2c *i2c = platform_get_drvdata(dev);
  664. if (i2c != NULL)
  665. s3c24xx_i2c_init(i2c);
  666. return 0;
  667. }
  668. #else
  669. #define s3c24xx_i2c_resume NULL
  670. #endif
  671. /* device driver for platform bus bits */
  672. static struct platform_driver s3c2410_i2c_driver = {
  673. .probe = s3c24xx_i2c_probe,
  674. .remove = s3c24xx_i2c_remove,
  675. .resume = s3c24xx_i2c_resume,
  676. .driver = {
  677. .owner = THIS_MODULE,
  678. .name = "s3c2410-i2c",
  679. },
  680. };
  681. static struct platform_driver s3c2440_i2c_driver = {
  682. .probe = s3c24xx_i2c_probe,
  683. .remove = s3c24xx_i2c_remove,
  684. .resume = s3c24xx_i2c_resume,
  685. .driver = {
  686. .owner = THIS_MODULE,
  687. .name = "s3c2440-i2c",
  688. },
  689. };
  690. static int __init i2c_adap_s3c_init(void)
  691. {
  692. int ret;
  693. ret = platform_driver_register(&s3c2410_i2c_driver);
  694. if (ret == 0) {
  695. ret = platform_driver_register(&s3c2440_i2c_driver);
  696. if (ret)
  697. platform_driver_unregister(&s3c2410_i2c_driver);
  698. }
  699. return ret;
  700. }
  701. static void __exit i2c_adap_s3c_exit(void)
  702. {
  703. platform_driver_unregister(&s3c2410_i2c_driver);
  704. platform_driver_unregister(&s3c2440_i2c_driver);
  705. }
  706. module_init(i2c_adap_s3c_init);
  707. module_exit(i2c_adap_s3c_exit);
  708. MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
  709. MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
  710. MODULE_LICENSE("GPL");