omap_wdt.c 9.0 KB

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  1. /*
  2. * linux/drivers/char/watchdog/omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@redhat.com>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/kernel.h>
  31. #include <linux/fs.h>
  32. #include <linux/mm.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/watchdog.h>
  35. #include <linux/reboot.h>
  36. #include <linux/smp_lock.h>
  37. #include <linux/init.h>
  38. #include <linux/err.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/moduleparam.h>
  41. #include <linux/clk.h>
  42. #include <asm/io.h>
  43. #include <asm/uaccess.h>
  44. #include <asm/hardware.h>
  45. #include <asm/bitops.h>
  46. #include <asm/arch/prcm.h>
  47. #include "omap_wdt.h"
  48. static unsigned timer_margin;
  49. module_param(timer_margin, uint, 0);
  50. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  51. static int omap_wdt_users;
  52. static struct clk *armwdt_ck = NULL;
  53. static struct clk *mpu_wdt_ick = NULL;
  54. static struct clk *mpu_wdt_fck = NULL;
  55. static unsigned int wdt_trgr_pattern = 0x1234;
  56. static void omap_wdt_ping(void)
  57. {
  58. /* wait for posted write to complete */
  59. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
  60. cpu_relax();
  61. wdt_trgr_pattern = ~wdt_trgr_pattern;
  62. omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
  63. /* wait for posted write to complete */
  64. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
  65. cpu_relax();
  66. /* reloaded WCRR from WLDR */
  67. }
  68. static void omap_wdt_enable(void)
  69. {
  70. /* Sequence to enable the watchdog */
  71. omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
  72. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
  73. cpu_relax();
  74. omap_writel(0x4444, OMAP_WATCHDOG_SPR);
  75. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
  76. cpu_relax();
  77. }
  78. static void omap_wdt_disable(void)
  79. {
  80. /* sequence required to disable watchdog */
  81. omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  82. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
  83. cpu_relax();
  84. omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  85. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
  86. cpu_relax();
  87. }
  88. static void omap_wdt_adjust_timeout(unsigned new_timeout)
  89. {
  90. if (new_timeout < TIMER_MARGIN_MIN)
  91. new_timeout = TIMER_MARGIN_DEFAULT;
  92. if (new_timeout > TIMER_MARGIN_MAX)
  93. new_timeout = TIMER_MARGIN_MAX;
  94. timer_margin = new_timeout;
  95. }
  96. static void omap_wdt_set_timeout(void)
  97. {
  98. u32 pre_margin = GET_WLDR_VAL(timer_margin);
  99. /* just count up at 32 KHz */
  100. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
  101. cpu_relax();
  102. omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
  103. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
  104. cpu_relax();
  105. }
  106. /*
  107. * Allow only one task to hold it open
  108. */
  109. static int omap_wdt_open(struct inode *inode, struct file *file)
  110. {
  111. if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
  112. return -EBUSY;
  113. if (cpu_is_omap16xx())
  114. clk_enable(armwdt_ck); /* Enable the clock */
  115. if (cpu_is_omap24xx()) {
  116. clk_enable(mpu_wdt_ick); /* Enable the interface clock */
  117. clk_enable(mpu_wdt_fck); /* Enable the functional clock */
  118. }
  119. /* initialize prescaler */
  120. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
  121. cpu_relax();
  122. omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
  123. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
  124. cpu_relax();
  125. omap_wdt_set_timeout();
  126. omap_wdt_enable();
  127. return 0;
  128. }
  129. static int omap_wdt_release(struct inode *inode, struct file *file)
  130. {
  131. /*
  132. * Shut off the timer unless NOWAYOUT is defined.
  133. */
  134. #ifndef CONFIG_WATCHDOG_NOWAYOUT
  135. omap_wdt_disable();
  136. if (cpu_is_omap16xx()) {
  137. clk_disable(armwdt_ck); /* Disable the clock */
  138. clk_put(armwdt_ck);
  139. armwdt_ck = NULL;
  140. }
  141. if (cpu_is_omap24xx()) {
  142. clk_disable(mpu_wdt_ick); /* Disable the clock */
  143. clk_disable(mpu_wdt_fck); /* Disable the clock */
  144. clk_put(mpu_wdt_ick);
  145. clk_put(mpu_wdt_fck);
  146. mpu_wdt_ick = NULL;
  147. mpu_wdt_fck = NULL;
  148. }
  149. #else
  150. printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
  151. #endif
  152. omap_wdt_users = 0;
  153. return 0;
  154. }
  155. static ssize_t
  156. omap_wdt_write(struct file *file, const char __user *data,
  157. size_t len, loff_t *ppos)
  158. {
  159. /* Refresh LOAD_TIME. */
  160. if (len)
  161. omap_wdt_ping();
  162. return len;
  163. }
  164. static int
  165. omap_wdt_ioctl(struct inode *inode, struct file *file,
  166. unsigned int cmd, unsigned long arg)
  167. {
  168. int new_margin;
  169. static struct watchdog_info ident = {
  170. .identity = "OMAP Watchdog",
  171. .options = WDIOF_SETTIMEOUT,
  172. .firmware_version = 0,
  173. };
  174. switch (cmd) {
  175. default:
  176. return -ENOIOCTLCMD;
  177. case WDIOC_GETSUPPORT:
  178. return copy_to_user((struct watchdog_info __user *)arg, &ident,
  179. sizeof(ident));
  180. case WDIOC_GETSTATUS:
  181. return put_user(0, (int __user *)arg);
  182. case WDIOC_GETBOOTSTATUS:
  183. if (cpu_is_omap16xx())
  184. return put_user(omap_readw(ARM_SYSST),
  185. (int __user *)arg);
  186. if (cpu_is_omap24xx())
  187. return put_user(omap_prcm_get_reset_sources(),
  188. (int __user *)arg);
  189. case WDIOC_KEEPALIVE:
  190. omap_wdt_ping();
  191. return 0;
  192. case WDIOC_SETTIMEOUT:
  193. if (get_user(new_margin, (int __user *)arg))
  194. return -EFAULT;
  195. omap_wdt_adjust_timeout(new_margin);
  196. omap_wdt_disable();
  197. omap_wdt_set_timeout();
  198. omap_wdt_enable();
  199. omap_wdt_ping();
  200. /* Fall */
  201. case WDIOC_GETTIMEOUT:
  202. return put_user(timer_margin, (int __user *)arg);
  203. }
  204. }
  205. static struct file_operations omap_wdt_fops = {
  206. .owner = THIS_MODULE,
  207. .write = omap_wdt_write,
  208. .ioctl = omap_wdt_ioctl,
  209. .open = omap_wdt_open,
  210. .release = omap_wdt_release,
  211. };
  212. static struct miscdevice omap_wdt_miscdev = {
  213. .minor = WATCHDOG_MINOR,
  214. .name = "watchdog",
  215. .fops = &omap_wdt_fops
  216. };
  217. static int __init omap_wdt_probe(struct platform_device *pdev)
  218. {
  219. struct resource *res, *mem;
  220. int ret;
  221. /* reserve static register mappings */
  222. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  223. if (!res)
  224. return -ENOENT;
  225. mem = request_mem_region(res->start, res->end - res->start + 1,
  226. pdev->name);
  227. if (mem == NULL)
  228. return -EBUSY;
  229. platform_set_drvdata(pdev, mem);
  230. omap_wdt_users = 0;
  231. if (cpu_is_omap16xx()) {
  232. armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
  233. if (IS_ERR(armwdt_ck)) {
  234. ret = PTR_ERR(armwdt_ck);
  235. armwdt_ck = NULL;
  236. goto fail;
  237. }
  238. }
  239. if (cpu_is_omap24xx()) {
  240. mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
  241. if (IS_ERR(mpu_wdt_ick)) {
  242. ret = PTR_ERR(mpu_wdt_ick);
  243. mpu_wdt_ick = NULL;
  244. goto fail;
  245. }
  246. mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
  247. if (IS_ERR(mpu_wdt_fck)) {
  248. ret = PTR_ERR(mpu_wdt_fck);
  249. mpu_wdt_fck = NULL;
  250. goto fail;
  251. }
  252. }
  253. omap_wdt_disable();
  254. omap_wdt_adjust_timeout(timer_margin);
  255. omap_wdt_miscdev.dev = &pdev->dev;
  256. ret = misc_register(&omap_wdt_miscdev);
  257. if (ret)
  258. goto fail;
  259. pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
  260. /* autogate OCP interface clock */
  261. omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
  262. return 0;
  263. fail:
  264. if (armwdt_ck)
  265. clk_put(armwdt_ck);
  266. if (mpu_wdt_ick)
  267. clk_put(mpu_wdt_ick);
  268. if (mpu_wdt_fck)
  269. clk_put(mpu_wdt_fck);
  270. release_resource(mem);
  271. return ret;
  272. }
  273. static void omap_wdt_shutdown(struct platform_device *pdev)
  274. {
  275. omap_wdt_disable();
  276. }
  277. static int omap_wdt_remove(struct platform_device *pdev)
  278. {
  279. struct resource *mem = platform_get_drvdata(pdev);
  280. misc_deregister(&omap_wdt_miscdev);
  281. release_resource(mem);
  282. if (armwdt_ck)
  283. clk_put(armwdt_ck);
  284. if (mpu_wdt_ick)
  285. clk_put(mpu_wdt_ick);
  286. if (mpu_wdt_fck)
  287. clk_put(mpu_wdt_fck);
  288. return 0;
  289. }
  290. #ifdef CONFIG_PM
  291. /* REVISIT ... not clear this is the best way to handle system suspend; and
  292. * it's very inappropriate for selective device suspend (e.g. suspending this
  293. * through sysfs rather than by stopping the watchdog daemon). Also, this
  294. * may not play well enough with NOWAYOUT...
  295. */
  296. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  297. {
  298. if (omap_wdt_users)
  299. omap_wdt_disable();
  300. return 0;
  301. }
  302. static int omap_wdt_resume(struct platform_device *pdev)
  303. {
  304. if (omap_wdt_users) {
  305. omap_wdt_enable();
  306. omap_wdt_ping();
  307. }
  308. return 0;
  309. }
  310. #else
  311. #define omap_wdt_suspend NULL
  312. #define omap_wdt_resume NULL
  313. #endif
  314. static struct platform_driver omap_wdt_driver = {
  315. .probe = omap_wdt_probe,
  316. .remove = omap_wdt_remove,
  317. .shutdown = omap_wdt_shutdown,
  318. .suspend = omap_wdt_suspend,
  319. .resume = omap_wdt_resume,
  320. .driver = {
  321. .owner = THIS_MODULE,
  322. .name = "omap_wdt",
  323. },
  324. };
  325. static int __init omap_wdt_init(void)
  326. {
  327. return platform_driver_register(&omap_wdt_driver);
  328. }
  329. static void __exit omap_wdt_exit(void)
  330. {
  331. platform_driver_unregister(&omap_wdt_driver);
  332. }
  333. module_init(omap_wdt_init);
  334. module_exit(omap_wdt_exit);
  335. MODULE_AUTHOR("George G. Davis");
  336. MODULE_LICENSE("GPL");
  337. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);