cpu5wdt.c 6.7 KB

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  1. /*
  2. * sma cpu5 watchdog driver
  3. *
  4. * Copyright (C) 2003 Heiko Ronsdorf <hero@ihg.uni-duisburg.de>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/types.h>
  24. #include <linux/errno.h>
  25. #include <linux/miscdevice.h>
  26. #include <linux/fs.h>
  27. #include <linux/init.h>
  28. #include <linux/ioport.h>
  29. #include <linux/timer.h>
  30. #include <linux/completion.h>
  31. #include <linux/jiffies.h>
  32. #include <asm/io.h>
  33. #include <asm/uaccess.h>
  34. #include <linux/watchdog.h>
  35. /* adjustable parameters */
  36. static int verbose = 0;
  37. static int port = 0x91;
  38. static int ticks = 10000;
  39. #define PFX "cpu5wdt: "
  40. #define CPU5WDT_EXTENT 0x0A
  41. #define CPU5WDT_STATUS_REG 0x00
  42. #define CPU5WDT_TIME_A_REG 0x02
  43. #define CPU5WDT_TIME_B_REG 0x03
  44. #define CPU5WDT_MODE_REG 0x04
  45. #define CPU5WDT_TRIGGER_REG 0x07
  46. #define CPU5WDT_ENABLE_REG 0x08
  47. #define CPU5WDT_RESET_REG 0x09
  48. #define CPU5WDT_INTERVAL (HZ/10+1)
  49. /* some device data */
  50. static struct {
  51. struct completion stop;
  52. volatile int running;
  53. struct timer_list timer;
  54. volatile int queue;
  55. int default_ticks;
  56. unsigned long inuse;
  57. } cpu5wdt_device;
  58. /* generic helper functions */
  59. static void cpu5wdt_trigger(unsigned long unused)
  60. {
  61. if ( verbose > 2 )
  62. printk(KERN_DEBUG PFX "trigger at %i ticks\n", ticks);
  63. if( cpu5wdt_device.running )
  64. ticks--;
  65. /* keep watchdog alive */
  66. outb(1, port + CPU5WDT_TRIGGER_REG);
  67. /* requeue?? */
  68. if( cpu5wdt_device.queue && ticks ) {
  69. cpu5wdt_device.timer.expires = jiffies + CPU5WDT_INTERVAL;
  70. add_timer(&cpu5wdt_device.timer);
  71. }
  72. else {
  73. /* ticks doesn't matter anyway */
  74. complete(&cpu5wdt_device.stop);
  75. }
  76. }
  77. static void cpu5wdt_reset(void)
  78. {
  79. ticks = cpu5wdt_device.default_ticks;
  80. if ( verbose )
  81. printk(KERN_DEBUG PFX "reset (%i ticks)\n", (int) ticks);
  82. }
  83. static void cpu5wdt_start(void)
  84. {
  85. if ( !cpu5wdt_device.queue ) {
  86. cpu5wdt_device.queue = 1;
  87. outb(0, port + CPU5WDT_TIME_A_REG);
  88. outb(0, port + CPU5WDT_TIME_B_REG);
  89. outb(1, port + CPU5WDT_MODE_REG);
  90. outb(0, port + CPU5WDT_RESET_REG);
  91. outb(0, port + CPU5WDT_ENABLE_REG);
  92. cpu5wdt_device.timer.expires = jiffies + CPU5WDT_INTERVAL;
  93. add_timer(&cpu5wdt_device.timer);
  94. }
  95. /* if process dies, counter is not decremented */
  96. cpu5wdt_device.running++;
  97. }
  98. static int cpu5wdt_stop(void)
  99. {
  100. if ( cpu5wdt_device.running )
  101. cpu5wdt_device.running = 0;
  102. ticks = cpu5wdt_device.default_ticks;
  103. if ( verbose )
  104. printk(KERN_CRIT PFX "stop not possible\n");
  105. return -EIO;
  106. }
  107. /* filesystem operations */
  108. static int cpu5wdt_open(struct inode *inode, struct file *file)
  109. {
  110. if ( test_and_set_bit(0, &cpu5wdt_device.inuse) )
  111. return -EBUSY;
  112. return nonseekable_open(inode, file);
  113. }
  114. static int cpu5wdt_release(struct inode *inode, struct file *file)
  115. {
  116. clear_bit(0, &cpu5wdt_device.inuse);
  117. return 0;
  118. }
  119. static int cpu5wdt_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
  120. {
  121. void __user *argp = (void __user *)arg;
  122. unsigned int value;
  123. static struct watchdog_info ident =
  124. {
  125. .options = WDIOF_CARDRESET,
  126. .identity = "CPU5 WDT",
  127. };
  128. switch(cmd) {
  129. case WDIOC_KEEPALIVE:
  130. cpu5wdt_reset();
  131. break;
  132. case WDIOC_GETSTATUS:
  133. value = inb(port + CPU5WDT_STATUS_REG);
  134. value = (value >> 2) & 1;
  135. if ( copy_to_user(argp, &value, sizeof(int)) )
  136. return -EFAULT;
  137. break;
  138. case WDIOC_GETSUPPORT:
  139. if ( copy_to_user(argp, &ident, sizeof(ident)) )
  140. return -EFAULT;
  141. break;
  142. case WDIOC_SETOPTIONS:
  143. if ( copy_from_user(&value, argp, sizeof(int)) )
  144. return -EFAULT;
  145. switch(value) {
  146. case WDIOS_ENABLECARD:
  147. cpu5wdt_start();
  148. break;
  149. case WDIOS_DISABLECARD:
  150. return cpu5wdt_stop();
  151. default:
  152. return -EINVAL;
  153. }
  154. break;
  155. default:
  156. return -ENOTTY;
  157. }
  158. return 0;
  159. }
  160. static ssize_t cpu5wdt_write(struct file *file, const char __user *buf, size_t count, loff_t *ppos)
  161. {
  162. if ( !count )
  163. return -EIO;
  164. cpu5wdt_reset();
  165. return count;
  166. }
  167. static const struct file_operations cpu5wdt_fops = {
  168. .owner = THIS_MODULE,
  169. .llseek = no_llseek,
  170. .ioctl = cpu5wdt_ioctl,
  171. .open = cpu5wdt_open,
  172. .write = cpu5wdt_write,
  173. .release = cpu5wdt_release,
  174. };
  175. static struct miscdevice cpu5wdt_misc = {
  176. .minor = WATCHDOG_MINOR,
  177. .name = "watchdog",
  178. .fops = &cpu5wdt_fops,
  179. };
  180. /* init/exit function */
  181. static int __devinit cpu5wdt_init(void)
  182. {
  183. unsigned int val;
  184. int err;
  185. if ( verbose )
  186. printk(KERN_DEBUG PFX "port=0x%x, verbose=%i\n", port, verbose);
  187. if ( (err = misc_register(&cpu5wdt_misc)) < 0 ) {
  188. printk(KERN_ERR PFX "misc_register failed\n");
  189. goto no_misc;
  190. }
  191. if ( !request_region(port, CPU5WDT_EXTENT, PFX) ) {
  192. printk(KERN_ERR PFX "request_region failed\n");
  193. err = -EBUSY;
  194. goto no_port;
  195. }
  196. /* watchdog reboot? */
  197. val = inb(port + CPU5WDT_STATUS_REG);
  198. val = (val >> 2) & 1;
  199. if ( !val )
  200. printk(KERN_INFO PFX "sorry, was my fault\n");
  201. init_completion(&cpu5wdt_device.stop);
  202. cpu5wdt_device.queue = 0;
  203. clear_bit(0, &cpu5wdt_device.inuse);
  204. init_timer(&cpu5wdt_device.timer);
  205. cpu5wdt_device.timer.function = cpu5wdt_trigger;
  206. cpu5wdt_device.timer.data = 0;
  207. cpu5wdt_device.default_ticks = ticks;
  208. printk(KERN_INFO PFX "init success\n");
  209. return 0;
  210. no_port:
  211. misc_deregister(&cpu5wdt_misc);
  212. no_misc:
  213. return err;
  214. }
  215. static int __devinit cpu5wdt_init_module(void)
  216. {
  217. return cpu5wdt_init();
  218. }
  219. static void __devexit cpu5wdt_exit(void)
  220. {
  221. if ( cpu5wdt_device.queue ) {
  222. cpu5wdt_device.queue = 0;
  223. wait_for_completion(&cpu5wdt_device.stop);
  224. }
  225. misc_deregister(&cpu5wdt_misc);
  226. release_region(port, CPU5WDT_EXTENT);
  227. }
  228. static void __devexit cpu5wdt_exit_module(void)
  229. {
  230. cpu5wdt_exit();
  231. }
  232. /* module entry points */
  233. module_init(cpu5wdt_init_module);
  234. module_exit(cpu5wdt_exit_module);
  235. MODULE_AUTHOR("Heiko Ronsdorf <hero@ihg.uni-duisburg.de>");
  236. MODULE_DESCRIPTION("sma cpu5 watchdog driver");
  237. MODULE_SUPPORTED_DEVICE("sma cpu5 watchdog");
  238. MODULE_LICENSE("GPL");
  239. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  240. module_param(port, int, 0);
  241. MODULE_PARM_DESC(port, "base address of watchdog card, default is 0x91");
  242. module_param(verbose, int, 0);
  243. MODULE_PARM_DESC(verbose, "be verbose, default is 0 (no)");
  244. module_param(ticks, int, 0);
  245. MODULE_PARM_DESC(ticks, "count down ticks, default is 10000");