tpm_nsc.c 9.8 KB

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  1. /*
  2. * Copyright (C) 2004 IBM Corporation
  3. *
  4. * Authors:
  5. * Leendert van Doorn <leendert@watson.ibm.com>
  6. * Dave Safford <safford@watson.ibm.com>
  7. * Reiner Sailer <sailer@watson.ibm.com>
  8. * Kylene Hall <kjhall@us.ibm.com>
  9. *
  10. * Maintained by: <tpmdd_devel@lists.sourceforge.net>
  11. *
  12. * Device driver for TCG/TCPA TPM (trusted platform module).
  13. * Specifications at www.trustedcomputinggroup.org
  14. *
  15. * This program is free software; you can redistribute it and/or
  16. * modify it under the terms of the GNU General Public License as
  17. * published by the Free Software Foundation, version 2 of the
  18. * License.
  19. *
  20. */
  21. #include <linux/platform_device.h>
  22. #include "tpm.h"
  23. /* National definitions */
  24. enum tpm_nsc_addr{
  25. TPM_NSC_IRQ = 0x07,
  26. TPM_NSC_BASE0_HI = 0x60,
  27. TPM_NSC_BASE0_LO = 0x61,
  28. TPM_NSC_BASE1_HI = 0x62,
  29. TPM_NSC_BASE1_LO = 0x63
  30. };
  31. enum tpm_nsc_index {
  32. NSC_LDN_INDEX = 0x07,
  33. NSC_SID_INDEX = 0x20,
  34. NSC_LDC_INDEX = 0x30,
  35. NSC_DIO_INDEX = 0x60,
  36. NSC_CIO_INDEX = 0x62,
  37. NSC_IRQ_INDEX = 0x70,
  38. NSC_ITS_INDEX = 0x71
  39. };
  40. enum tpm_nsc_status_loc {
  41. NSC_STATUS = 0x01,
  42. NSC_COMMAND = 0x01,
  43. NSC_DATA = 0x00
  44. };
  45. /* status bits */
  46. enum tpm_nsc_status {
  47. NSC_STATUS_OBF = 0x01, /* output buffer full */
  48. NSC_STATUS_IBF = 0x02, /* input buffer full */
  49. NSC_STATUS_F0 = 0x04, /* F0 */
  50. NSC_STATUS_A2 = 0x08, /* A2 */
  51. NSC_STATUS_RDY = 0x10, /* ready to receive command */
  52. NSC_STATUS_IBR = 0x20 /* ready to receive data */
  53. };
  54. /* command bits */
  55. enum tpm_nsc_cmd_mode {
  56. NSC_COMMAND_NORMAL = 0x01, /* normal mode */
  57. NSC_COMMAND_EOC = 0x03,
  58. NSC_COMMAND_CANCEL = 0x22
  59. };
  60. /*
  61. * Wait for a certain status to appear
  62. */
  63. static int wait_for_stat(struct tpm_chip *chip, u8 mask, u8 val, u8 * data)
  64. {
  65. unsigned long stop;
  66. /* status immediately available check */
  67. *data = inb(chip->vendor.base + NSC_STATUS);
  68. if ((*data & mask) == val)
  69. return 0;
  70. /* wait for status */
  71. stop = jiffies + 10 * HZ;
  72. do {
  73. msleep(TPM_TIMEOUT);
  74. *data = inb(chip->vendor.base + 1);
  75. if ((*data & mask) == val)
  76. return 0;
  77. }
  78. while (time_before(jiffies, stop));
  79. return -EBUSY;
  80. }
  81. static int nsc_wait_for_ready(struct tpm_chip *chip)
  82. {
  83. int status;
  84. unsigned long stop;
  85. /* status immediately available check */
  86. status = inb(chip->vendor.base + NSC_STATUS);
  87. if (status & NSC_STATUS_OBF)
  88. status = inb(chip->vendor.base + NSC_DATA);
  89. if (status & NSC_STATUS_RDY)
  90. return 0;
  91. /* wait for status */
  92. stop = jiffies + 100;
  93. do {
  94. msleep(TPM_TIMEOUT);
  95. status = inb(chip->vendor.base + NSC_STATUS);
  96. if (status & NSC_STATUS_OBF)
  97. status = inb(chip->vendor.base + NSC_DATA);
  98. if (status & NSC_STATUS_RDY)
  99. return 0;
  100. }
  101. while (time_before(jiffies, stop));
  102. dev_info(chip->dev, "wait for ready failed\n");
  103. return -EBUSY;
  104. }
  105. static int tpm_nsc_recv(struct tpm_chip *chip, u8 * buf, size_t count)
  106. {
  107. u8 *buffer = buf;
  108. u8 data, *p;
  109. u32 size;
  110. __be32 *native_size;
  111. if (count < 6)
  112. return -EIO;
  113. if (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0) {
  114. dev_err(chip->dev, "F0 timeout\n");
  115. return -EIO;
  116. }
  117. if ((data =
  118. inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_NORMAL) {
  119. dev_err(chip->dev, "not in normal mode (0x%x)\n",
  120. data);
  121. return -EIO;
  122. }
  123. /* read the whole packet */
  124. for (p = buffer; p < &buffer[count]; p++) {
  125. if (wait_for_stat
  126. (chip, NSC_STATUS_OBF, NSC_STATUS_OBF, &data) < 0) {
  127. dev_err(chip->dev,
  128. "OBF timeout (while reading data)\n");
  129. return -EIO;
  130. }
  131. if (data & NSC_STATUS_F0)
  132. break;
  133. *p = inb(chip->vendor.base + NSC_DATA);
  134. }
  135. if ((data & NSC_STATUS_F0) == 0 &&
  136. (wait_for_stat(chip, NSC_STATUS_F0, NSC_STATUS_F0, &data) < 0)) {
  137. dev_err(chip->dev, "F0 not set\n");
  138. return -EIO;
  139. }
  140. if ((data = inb(chip->vendor.base + NSC_DATA)) != NSC_COMMAND_EOC) {
  141. dev_err(chip->dev,
  142. "expected end of command(0x%x)\n", data);
  143. return -EIO;
  144. }
  145. native_size = (__force __be32 *) (buf + 2);
  146. size = be32_to_cpu(*native_size);
  147. if (count < size)
  148. return -EIO;
  149. return size;
  150. }
  151. static int tpm_nsc_send(struct tpm_chip *chip, u8 * buf, size_t count)
  152. {
  153. u8 data;
  154. int i;
  155. /*
  156. * If we hit the chip with back to back commands it locks up
  157. * and never set IBF. Hitting it with this "hammer" seems to
  158. * fix it. Not sure why this is needed, we followed the flow
  159. * chart in the manual to the letter.
  160. */
  161. outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
  162. if (nsc_wait_for_ready(chip) != 0)
  163. return -EIO;
  164. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  165. dev_err(chip->dev, "IBF timeout\n");
  166. return -EIO;
  167. }
  168. outb(NSC_COMMAND_NORMAL, chip->vendor.base + NSC_COMMAND);
  169. if (wait_for_stat(chip, NSC_STATUS_IBR, NSC_STATUS_IBR, &data) < 0) {
  170. dev_err(chip->dev, "IBR timeout\n");
  171. return -EIO;
  172. }
  173. for (i = 0; i < count; i++) {
  174. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  175. dev_err(chip->dev,
  176. "IBF timeout (while writing data)\n");
  177. return -EIO;
  178. }
  179. outb(buf[i], chip->vendor.base + NSC_DATA);
  180. }
  181. if (wait_for_stat(chip, NSC_STATUS_IBF, 0, &data) < 0) {
  182. dev_err(chip->dev, "IBF timeout\n");
  183. return -EIO;
  184. }
  185. outb(NSC_COMMAND_EOC, chip->vendor.base + NSC_COMMAND);
  186. return count;
  187. }
  188. static void tpm_nsc_cancel(struct tpm_chip *chip)
  189. {
  190. outb(NSC_COMMAND_CANCEL, chip->vendor.base + NSC_COMMAND);
  191. }
  192. static u8 tpm_nsc_status(struct tpm_chip *chip)
  193. {
  194. return inb(chip->vendor.base + NSC_STATUS);
  195. }
  196. static const struct file_operations nsc_ops = {
  197. .owner = THIS_MODULE,
  198. .llseek = no_llseek,
  199. .open = tpm_open,
  200. .read = tpm_read,
  201. .write = tpm_write,
  202. .release = tpm_release,
  203. };
  204. static DEVICE_ATTR(pubek, S_IRUGO, tpm_show_pubek, NULL);
  205. static DEVICE_ATTR(pcrs, S_IRUGO, tpm_show_pcrs, NULL);
  206. static DEVICE_ATTR(caps, S_IRUGO, tpm_show_caps, NULL);
  207. static DEVICE_ATTR(cancel, S_IWUSR|S_IWGRP, NULL, tpm_store_cancel);
  208. static struct attribute * nsc_attrs[] = {
  209. &dev_attr_pubek.attr,
  210. &dev_attr_pcrs.attr,
  211. &dev_attr_caps.attr,
  212. &dev_attr_cancel.attr,
  213. NULL,
  214. };
  215. static struct attribute_group nsc_attr_grp = { .attrs = nsc_attrs };
  216. static const struct tpm_vendor_specific tpm_nsc = {
  217. .recv = tpm_nsc_recv,
  218. .send = tpm_nsc_send,
  219. .cancel = tpm_nsc_cancel,
  220. .status = tpm_nsc_status,
  221. .req_complete_mask = NSC_STATUS_OBF,
  222. .req_complete_val = NSC_STATUS_OBF,
  223. .req_canceled = NSC_STATUS_RDY,
  224. .attr_group = &nsc_attr_grp,
  225. .miscdev = { .fops = &nsc_ops, },
  226. };
  227. static struct platform_device *pdev = NULL;
  228. static void __devexit tpm_nsc_remove(struct device *dev)
  229. {
  230. struct tpm_chip *chip = dev_get_drvdata(dev);
  231. if ( chip ) {
  232. release_region(chip->vendor.base, 2);
  233. tpm_remove_hardware(chip->dev);
  234. }
  235. }
  236. static struct device_driver nsc_drv = {
  237. .name = "tpm_nsc",
  238. .bus = &platform_bus_type,
  239. .owner = THIS_MODULE,
  240. .suspend = tpm_pm_suspend,
  241. .resume = tpm_pm_resume,
  242. };
  243. static int __init init_nsc(void)
  244. {
  245. int rc = 0;
  246. int lo, hi, err;
  247. int nscAddrBase = TPM_ADDR;
  248. struct tpm_chip *chip;
  249. unsigned long base;
  250. /* verify that it is a National part (SID) */
  251. if (tpm_read_index(TPM_ADDR, NSC_SID_INDEX) != 0xEF) {
  252. nscAddrBase = (tpm_read_index(TPM_SUPERIO_ADDR, 0x2C)<<8)|
  253. (tpm_read_index(TPM_SUPERIO_ADDR, 0x2B)&0xFE);
  254. if (tpm_read_index(nscAddrBase, NSC_SID_INDEX) != 0xF6)
  255. return -ENODEV;
  256. }
  257. err = driver_register(&nsc_drv);
  258. if (err)
  259. return err;
  260. hi = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_HI);
  261. lo = tpm_read_index(nscAddrBase, TPM_NSC_BASE0_LO);
  262. base = (hi<<8) | lo;
  263. /* enable the DPM module */
  264. tpm_write_index(nscAddrBase, NSC_LDC_INDEX, 0x01);
  265. pdev = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
  266. if (!pdev) {
  267. rc = -ENOMEM;
  268. goto err_unreg_drv;
  269. }
  270. pdev->name = "tpm_nscl0";
  271. pdev->id = -1;
  272. pdev->num_resources = 0;
  273. pdev->dev.release = tpm_nsc_remove;
  274. pdev->dev.driver = &nsc_drv;
  275. if ((rc = platform_device_register(pdev)) < 0)
  276. goto err_free_dev;
  277. if (request_region(base, 2, "tpm_nsc0") == NULL ) {
  278. rc = -EBUSY;
  279. goto err_unreg_dev;
  280. }
  281. if (!(chip = tpm_register_hardware(&pdev->dev, &tpm_nsc))) {
  282. rc = -ENODEV;
  283. goto err_rel_reg;
  284. }
  285. dev_dbg(&pdev->dev, "NSC TPM detected\n");
  286. dev_dbg(&pdev->dev,
  287. "NSC LDN 0x%x, SID 0x%x, SRID 0x%x\n",
  288. tpm_read_index(nscAddrBase,0x07), tpm_read_index(nscAddrBase,0x20),
  289. tpm_read_index(nscAddrBase,0x27));
  290. dev_dbg(&pdev->dev,
  291. "NSC SIOCF1 0x%x SIOCF5 0x%x SIOCF6 0x%x SIOCF8 0x%x\n",
  292. tpm_read_index(nscAddrBase,0x21), tpm_read_index(nscAddrBase,0x25),
  293. tpm_read_index(nscAddrBase,0x26), tpm_read_index(nscAddrBase,0x28));
  294. dev_dbg(&pdev->dev, "NSC IO Base0 0x%x\n",
  295. (tpm_read_index(nscAddrBase,0x60) << 8) | tpm_read_index(nscAddrBase,0x61));
  296. dev_dbg(&pdev->dev, "NSC IO Base1 0x%x\n",
  297. (tpm_read_index(nscAddrBase,0x62) << 8) | tpm_read_index(nscAddrBase,0x63));
  298. dev_dbg(&pdev->dev, "NSC Interrupt number and wakeup 0x%x\n",
  299. tpm_read_index(nscAddrBase,0x70));
  300. dev_dbg(&pdev->dev, "NSC IRQ type select 0x%x\n",
  301. tpm_read_index(nscAddrBase,0x71));
  302. dev_dbg(&pdev->dev,
  303. "NSC DMA channel select0 0x%x, select1 0x%x\n",
  304. tpm_read_index(nscAddrBase,0x74), tpm_read_index(nscAddrBase,0x75));
  305. dev_dbg(&pdev->dev,
  306. "NSC Config "
  307. "0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
  308. tpm_read_index(nscAddrBase,0xF0), tpm_read_index(nscAddrBase,0xF1),
  309. tpm_read_index(nscAddrBase,0xF2), tpm_read_index(nscAddrBase,0xF3),
  310. tpm_read_index(nscAddrBase,0xF4), tpm_read_index(nscAddrBase,0xF5),
  311. tpm_read_index(nscAddrBase,0xF6), tpm_read_index(nscAddrBase,0xF7),
  312. tpm_read_index(nscAddrBase,0xF8), tpm_read_index(nscAddrBase,0xF9));
  313. dev_info(&pdev->dev,
  314. "NSC TPM revision %d\n",
  315. tpm_read_index(nscAddrBase, 0x27) & 0x1F);
  316. chip->vendor.base = base;
  317. return 0;
  318. err_rel_reg:
  319. release_region(base, 2);
  320. err_unreg_dev:
  321. platform_device_unregister(pdev);
  322. err_free_dev:
  323. kfree(pdev);
  324. err_unreg_drv:
  325. driver_unregister(&nsc_drv);
  326. return rc;
  327. }
  328. static void __exit cleanup_nsc(void)
  329. {
  330. if (pdev) {
  331. tpm_nsc_remove(&pdev->dev);
  332. platform_device_unregister(pdev);
  333. kfree(pdev);
  334. pdev = NULL;
  335. }
  336. driver_unregister(&nsc_drv);
  337. }
  338. module_init(init_nsc);
  339. module_exit(cleanup_nsc);
  340. MODULE_AUTHOR("Leendert van Doorn (leendert@watson.ibm.com)");
  341. MODULE_DESCRIPTION("TPM Driver");
  342. MODULE_VERSION("2.0");
  343. MODULE_LICENSE("GPL");