tlclk.c 23 KB

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  1. /*
  2. * Telecom Clock driver for Intel NetStructure(tm) MPCBL0010
  3. *
  4. * Copyright (C) 2005 Kontron Canada
  5. *
  6. * All rights reserved.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or (at
  11. * your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful, but
  14. * WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  16. * NON INFRINGEMENT. See the GNU General Public License for more
  17. * details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. *
  23. * Send feedback to <sebastien.bouchard@ca.kontron.com> and the current
  24. * Maintainer <mark.gross@intel.com>
  25. *
  26. * Description : This is the TELECOM CLOCK module driver for the ATCA
  27. * MPCBL0010 ATCA computer.
  28. */
  29. #include <linux/module.h>
  30. #include <linux/init.h>
  31. #include <linux/sched.h>
  32. #include <linux/kernel.h> /* printk() */
  33. #include <linux/fs.h> /* everything... */
  34. #include <linux/errno.h> /* error codes */
  35. #include <linux/slab.h>
  36. #include <linux/ioport.h>
  37. #include <linux/interrupt.h>
  38. #include <linux/spinlock.h>
  39. #include <linux/timer.h>
  40. #include <linux/sysfs.h>
  41. #include <linux/device.h>
  42. #include <linux/miscdevice.h>
  43. #include <linux/platform_device.h>
  44. #include <asm/io.h> /* inb/outb */
  45. #include <asm/uaccess.h>
  46. MODULE_AUTHOR("Sebastien Bouchard <sebastien.bouchard@ca.kontron.com>");
  47. MODULE_LICENSE("GPL");
  48. /*Hardware Reset of the PLL */
  49. #define RESET_ON 0x00
  50. #define RESET_OFF 0x01
  51. /* MODE SELECT */
  52. #define NORMAL_MODE 0x00
  53. #define HOLDOVER_MODE 0x10
  54. #define FREERUN_MODE 0x20
  55. /* FILTER SELECT */
  56. #define FILTER_6HZ 0x04
  57. #define FILTER_12HZ 0x00
  58. /* SELECT REFERENCE FREQUENCY */
  59. #define REF_CLK1_8kHz 0x00
  60. #define REF_CLK2_19_44MHz 0x02
  61. /* Select primary or secondary redundant clock */
  62. #define PRIMARY_CLOCK 0x00
  63. #define SECONDARY_CLOCK 0x01
  64. /* CLOCK TRANSMISSION DEFINE */
  65. #define CLK_8kHz 0xff
  66. #define CLK_16_384MHz 0xfb
  67. #define CLK_1_544MHz 0x00
  68. #define CLK_2_048MHz 0x01
  69. #define CLK_4_096MHz 0x02
  70. #define CLK_6_312MHz 0x03
  71. #define CLK_8_192MHz 0x04
  72. #define CLK_19_440MHz 0x06
  73. #define CLK_8_592MHz 0x08
  74. #define CLK_11_184MHz 0x09
  75. #define CLK_34_368MHz 0x0b
  76. #define CLK_44_736MHz 0x0a
  77. /* RECEIVED REFERENCE */
  78. #define AMC_B1 0
  79. #define AMC_B2 1
  80. /* HARDWARE SWITCHING DEFINE */
  81. #define HW_ENABLE 0x80
  82. #define HW_DISABLE 0x00
  83. /* HARDWARE SWITCHING MODE DEFINE */
  84. #define PLL_HOLDOVER 0x40
  85. #define LOST_CLOCK 0x00
  86. /* ALARMS DEFINE */
  87. #define UNLOCK_MASK 0x10
  88. #define HOLDOVER_MASK 0x20
  89. #define SEC_LOST_MASK 0x40
  90. #define PRI_LOST_MASK 0x80
  91. /* INTERRUPT CAUSE DEFINE */
  92. #define PRI_LOS_01_MASK 0x01
  93. #define PRI_LOS_10_MASK 0x02
  94. #define SEC_LOS_01_MASK 0x04
  95. #define SEC_LOS_10_MASK 0x08
  96. #define HOLDOVER_01_MASK 0x10
  97. #define HOLDOVER_10_MASK 0x20
  98. #define UNLOCK_01_MASK 0x40
  99. #define UNLOCK_10_MASK 0x80
  100. struct tlclk_alarms {
  101. __u32 lost_clocks;
  102. __u32 lost_primary_clock;
  103. __u32 lost_secondary_clock;
  104. __u32 primary_clock_back;
  105. __u32 secondary_clock_back;
  106. __u32 switchover_primary;
  107. __u32 switchover_secondary;
  108. __u32 pll_holdover;
  109. __u32 pll_end_holdover;
  110. __u32 pll_lost_sync;
  111. __u32 pll_sync;
  112. };
  113. /* Telecom clock I/O register definition */
  114. #define TLCLK_BASE 0xa08
  115. #define TLCLK_REG0 TLCLK_BASE
  116. #define TLCLK_REG1 (TLCLK_BASE+1)
  117. #define TLCLK_REG2 (TLCLK_BASE+2)
  118. #define TLCLK_REG3 (TLCLK_BASE+3)
  119. #define TLCLK_REG4 (TLCLK_BASE+4)
  120. #define TLCLK_REG5 (TLCLK_BASE+5)
  121. #define TLCLK_REG6 (TLCLK_BASE+6)
  122. #define TLCLK_REG7 (TLCLK_BASE+7)
  123. #define SET_PORT_BITS(port, mask, val) outb(((inb(port) & mask) | val), port)
  124. /* 0 = Dynamic allocation of the major device number */
  125. #define TLCLK_MAJOR 0
  126. /* sysfs interface definition:
  127. Upon loading the driver will create a sysfs directory under
  128. /sys/devices/platform/telco_clock.
  129. This directory exports the following interfaces. There operation is
  130. documented in the MCPBL0010 TPS under the Telecom Clock API section, 11.4.
  131. alarms :
  132. current_ref :
  133. received_ref_clk3a :
  134. received_ref_clk3b :
  135. enable_clk3a_output :
  136. enable_clk3b_output :
  137. enable_clka0_output :
  138. enable_clka1_output :
  139. enable_clkb0_output :
  140. enable_clkb1_output :
  141. filter_select :
  142. hardware_switching :
  143. hardware_switching_mode :
  144. telclock_version :
  145. mode_select :
  146. refalign :
  147. reset :
  148. select_amcb1_transmit_clock :
  149. select_amcb2_transmit_clock :
  150. select_redundant_clock :
  151. select_ref_frequency :
  152. All sysfs interfaces are integers in hex format, i.e echo 99 > refalign
  153. has the same effect as echo 0x99 > refalign.
  154. */
  155. static unsigned int telclk_interrupt;
  156. static int int_events; /* Event that generate a interrupt */
  157. static int got_event; /* if events processing have been done */
  158. static void switchover_timeout(unsigned long data);
  159. static struct timer_list switchover_timer =
  160. TIMER_INITIALIZER(switchover_timeout , 0, 0);
  161. static struct tlclk_alarms *alarm_events;
  162. static DEFINE_SPINLOCK(event_lock);
  163. static int tlclk_major = TLCLK_MAJOR;
  164. static irqreturn_t tlclk_interrupt(int irq, void *dev_id);
  165. static DECLARE_WAIT_QUEUE_HEAD(wq);
  166. static int tlclk_open(struct inode *inode, struct file *filp)
  167. {
  168. int result;
  169. /* Make sure there is no interrupt pending while
  170. * initialising interrupt handler */
  171. inb(TLCLK_REG6);
  172. /* This device is wired through the FPGA IO space of the ATCA blade
  173. * we can't share this IRQ */
  174. result = request_irq(telclk_interrupt, &tlclk_interrupt,
  175. IRQF_DISABLED, "telco_clock", tlclk_interrupt);
  176. if (result == -EBUSY) {
  177. printk(KERN_ERR "tlclk: Interrupt can't be reserved.\n");
  178. return -EBUSY;
  179. }
  180. inb(TLCLK_REG6); /* Clear interrupt events */
  181. return 0;
  182. }
  183. static int tlclk_release(struct inode *inode, struct file *filp)
  184. {
  185. free_irq(telclk_interrupt, tlclk_interrupt);
  186. return 0;
  187. }
  188. static ssize_t tlclk_read(struct file *filp, char __user *buf, size_t count,
  189. loff_t *f_pos)
  190. {
  191. if (count < sizeof(struct tlclk_alarms))
  192. return -EIO;
  193. wait_event_interruptible(wq, got_event);
  194. if (copy_to_user(buf, alarm_events, sizeof(struct tlclk_alarms)))
  195. return -EFAULT;
  196. memset(alarm_events, 0, sizeof(struct tlclk_alarms));
  197. got_event = 0;
  198. return sizeof(struct tlclk_alarms);
  199. }
  200. static ssize_t tlclk_write(struct file *filp, const char __user *buf, size_t count,
  201. loff_t *f_pos)
  202. {
  203. return 0;
  204. }
  205. static const struct file_operations tlclk_fops = {
  206. .read = tlclk_read,
  207. .write = tlclk_write,
  208. .open = tlclk_open,
  209. .release = tlclk_release,
  210. };
  211. static struct miscdevice tlclk_miscdev = {
  212. .minor = MISC_DYNAMIC_MINOR,
  213. .name = "telco_clock",
  214. .fops = &tlclk_fops,
  215. };
  216. static ssize_t show_current_ref(struct device *d,
  217. struct device_attribute *attr, char *buf)
  218. {
  219. unsigned long ret_val;
  220. unsigned long flags;
  221. spin_lock_irqsave(&event_lock, flags);
  222. ret_val = ((inb(TLCLK_REG1) & 0x08) >> 3);
  223. spin_unlock_irqrestore(&event_lock, flags);
  224. return sprintf(buf, "0x%lX\n", ret_val);
  225. }
  226. static DEVICE_ATTR(current_ref, S_IRUGO, show_current_ref, NULL);
  227. static ssize_t show_telclock_version(struct device *d,
  228. struct device_attribute *attr, char *buf)
  229. {
  230. unsigned long ret_val;
  231. unsigned long flags;
  232. spin_lock_irqsave(&event_lock, flags);
  233. ret_val = inb(TLCLK_REG5);
  234. spin_unlock_irqrestore(&event_lock, flags);
  235. return sprintf(buf, "0x%lX\n", ret_val);
  236. }
  237. static DEVICE_ATTR(telclock_version, S_IRUGO,
  238. show_telclock_version, NULL);
  239. static ssize_t show_alarms(struct device *d,
  240. struct device_attribute *attr, char *buf)
  241. {
  242. unsigned long ret_val;
  243. unsigned long flags;
  244. spin_lock_irqsave(&event_lock, flags);
  245. ret_val = (inb(TLCLK_REG2) & 0xf0);
  246. spin_unlock_irqrestore(&event_lock, flags);
  247. return sprintf(buf, "0x%lX\n", ret_val);
  248. }
  249. static DEVICE_ATTR(alarms, S_IRUGO, show_alarms, NULL);
  250. static ssize_t store_received_ref_clk3a(struct device *d,
  251. struct device_attribute *attr, const char *buf, size_t count)
  252. {
  253. unsigned long tmp;
  254. unsigned char val;
  255. unsigned long flags;
  256. sscanf(buf, "%lX", &tmp);
  257. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  258. val = (unsigned char)tmp;
  259. spin_lock_irqsave(&event_lock, flags);
  260. SET_PORT_BITS(TLCLK_REG1, 0xef, val);
  261. spin_unlock_irqrestore(&event_lock, flags);
  262. return strnlen(buf, count);
  263. }
  264. static DEVICE_ATTR(received_ref_clk3a, (S_IWUSR|S_IWGRP), NULL,
  265. store_received_ref_clk3a);
  266. static ssize_t store_received_ref_clk3b(struct device *d,
  267. struct device_attribute *attr, const char *buf, size_t count)
  268. {
  269. unsigned long tmp;
  270. unsigned char val;
  271. unsigned long flags;
  272. sscanf(buf, "%lX", &tmp);
  273. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  274. val = (unsigned char)tmp;
  275. spin_lock_irqsave(&event_lock, flags);
  276. SET_PORT_BITS(TLCLK_REG1, 0xdf, val << 1);
  277. spin_unlock_irqrestore(&event_lock, flags);
  278. return strnlen(buf, count);
  279. }
  280. static DEVICE_ATTR(received_ref_clk3b, (S_IWUSR|S_IWGRP), NULL,
  281. store_received_ref_clk3b);
  282. static ssize_t store_enable_clk3b_output(struct device *d,
  283. struct device_attribute *attr, const char *buf, size_t count)
  284. {
  285. unsigned long tmp;
  286. unsigned char val;
  287. unsigned long flags;
  288. sscanf(buf, "%lX", &tmp);
  289. dev_dbg(d, ": tmp = 0x%lX\n", tmp);
  290. val = (unsigned char)tmp;
  291. spin_lock_irqsave(&event_lock, flags);
  292. SET_PORT_BITS(TLCLK_REG3, 0x7f, val << 7);
  293. spin_unlock_irqrestore(&event_lock, flags);
  294. return strnlen(buf, count);
  295. }
  296. static DEVICE_ATTR(enable_clk3b_output, (S_IWUSR|S_IWGRP), NULL,
  297. store_enable_clk3b_output);
  298. static ssize_t store_enable_clk3a_output(struct device *d,
  299. struct device_attribute *attr, const char *buf, size_t count)
  300. {
  301. unsigned long flags;
  302. unsigned long tmp;
  303. unsigned char val;
  304. sscanf(buf, "%lX", &tmp);
  305. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  306. val = (unsigned char)tmp;
  307. spin_lock_irqsave(&event_lock, flags);
  308. SET_PORT_BITS(TLCLK_REG3, 0xbf, val << 6);
  309. spin_unlock_irqrestore(&event_lock, flags);
  310. return strnlen(buf, count);
  311. }
  312. static DEVICE_ATTR(enable_clk3a_output, (S_IWUSR|S_IWGRP), NULL,
  313. store_enable_clk3a_output);
  314. static ssize_t store_enable_clkb1_output(struct device *d,
  315. struct device_attribute *attr, const char *buf, size_t count)
  316. {
  317. unsigned long flags;
  318. unsigned long tmp;
  319. unsigned char val;
  320. sscanf(buf, "%lX", &tmp);
  321. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  322. val = (unsigned char)tmp;
  323. spin_lock_irqsave(&event_lock, flags);
  324. SET_PORT_BITS(TLCLK_REG2, 0xf7, val << 3);
  325. spin_unlock_irqrestore(&event_lock, flags);
  326. return strnlen(buf, count);
  327. }
  328. static DEVICE_ATTR(enable_clkb1_output, (S_IWUSR|S_IWGRP), NULL,
  329. store_enable_clkb1_output);
  330. static ssize_t store_enable_clka1_output(struct device *d,
  331. struct device_attribute *attr, const char *buf, size_t count)
  332. {
  333. unsigned long flags;
  334. unsigned long tmp;
  335. unsigned char val;
  336. sscanf(buf, "%lX", &tmp);
  337. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  338. val = (unsigned char)tmp;
  339. spin_lock_irqsave(&event_lock, flags);
  340. SET_PORT_BITS(TLCLK_REG2, 0xfb, val << 2);
  341. spin_unlock_irqrestore(&event_lock, flags);
  342. return strnlen(buf, count);
  343. }
  344. static DEVICE_ATTR(enable_clka1_output, (S_IWUSR|S_IWGRP), NULL,
  345. store_enable_clka1_output);
  346. static ssize_t store_enable_clkb0_output(struct device *d,
  347. struct device_attribute *attr, const char *buf, size_t count)
  348. {
  349. unsigned long flags;
  350. unsigned long tmp;
  351. unsigned char val;
  352. sscanf(buf, "%lX", &tmp);
  353. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  354. val = (unsigned char)tmp;
  355. spin_lock_irqsave(&event_lock, flags);
  356. SET_PORT_BITS(TLCLK_REG2, 0xfd, val << 1);
  357. spin_unlock_irqrestore(&event_lock, flags);
  358. return strnlen(buf, count);
  359. }
  360. static DEVICE_ATTR(enable_clkb0_output, (S_IWUSR|S_IWGRP), NULL,
  361. store_enable_clkb0_output);
  362. static ssize_t store_enable_clka0_output(struct device *d,
  363. struct device_attribute *attr, const char *buf, size_t count)
  364. {
  365. unsigned long flags;
  366. unsigned long tmp;
  367. unsigned char val;
  368. sscanf(buf, "%lX", &tmp);
  369. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  370. val = (unsigned char)tmp;
  371. spin_lock_irqsave(&event_lock, flags);
  372. SET_PORT_BITS(TLCLK_REG2, 0xfe, val);
  373. spin_unlock_irqrestore(&event_lock, flags);
  374. return strnlen(buf, count);
  375. }
  376. static DEVICE_ATTR(enable_clka0_output, (S_IWUSR|S_IWGRP), NULL,
  377. store_enable_clka0_output);
  378. static ssize_t store_select_amcb2_transmit_clock(struct device *d,
  379. struct device_attribute *attr, const char *buf, size_t count)
  380. {
  381. unsigned long flags;
  382. unsigned long tmp;
  383. unsigned char val;
  384. sscanf(buf, "%lX", &tmp);
  385. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  386. val = (unsigned char)tmp;
  387. spin_lock_irqsave(&event_lock, flags);
  388. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  389. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x28);
  390. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  391. } else if (val >= CLK_8_592MHz) {
  392. SET_PORT_BITS(TLCLK_REG3, 0xc7, 0x38);
  393. switch (val) {
  394. case CLK_8_592MHz:
  395. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  396. break;
  397. case CLK_11_184MHz:
  398. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  399. break;
  400. case CLK_34_368MHz:
  401. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  402. break;
  403. case CLK_44_736MHz:
  404. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  405. break;
  406. }
  407. } else
  408. SET_PORT_BITS(TLCLK_REG3, 0xc7, val << 3);
  409. spin_unlock_irqrestore(&event_lock, flags);
  410. return strnlen(buf, count);
  411. }
  412. static DEVICE_ATTR(select_amcb2_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  413. store_select_amcb2_transmit_clock);
  414. static ssize_t store_select_amcb1_transmit_clock(struct device *d,
  415. struct device_attribute *attr, const char *buf, size_t count)
  416. {
  417. unsigned long tmp;
  418. unsigned char val;
  419. unsigned long flags;
  420. sscanf(buf, "%lX", &tmp);
  421. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  422. val = (unsigned char)tmp;
  423. spin_lock_irqsave(&event_lock, flags);
  424. if ((val == CLK_8kHz) || (val == CLK_16_384MHz)) {
  425. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x5);
  426. SET_PORT_BITS(TLCLK_REG1, 0xfb, ~val);
  427. } else if (val >= CLK_8_592MHz) {
  428. SET_PORT_BITS(TLCLK_REG3, 0xf8, 0x7);
  429. switch (val) {
  430. case CLK_8_592MHz:
  431. SET_PORT_BITS(TLCLK_REG0, 0xfc, 1);
  432. break;
  433. case CLK_11_184MHz:
  434. SET_PORT_BITS(TLCLK_REG0, 0xfc, 0);
  435. break;
  436. case CLK_34_368MHz:
  437. SET_PORT_BITS(TLCLK_REG0, 0xfc, 3);
  438. break;
  439. case CLK_44_736MHz:
  440. SET_PORT_BITS(TLCLK_REG0, 0xfc, 2);
  441. break;
  442. }
  443. } else
  444. SET_PORT_BITS(TLCLK_REG3, 0xf8, val);
  445. spin_unlock_irqrestore(&event_lock, flags);
  446. return strnlen(buf, count);
  447. }
  448. static DEVICE_ATTR(select_amcb1_transmit_clock, (S_IWUSR|S_IWGRP), NULL,
  449. store_select_amcb1_transmit_clock);
  450. static ssize_t store_select_redundant_clock(struct device *d,
  451. struct device_attribute *attr, const char *buf, size_t count)
  452. {
  453. unsigned long tmp;
  454. unsigned char val;
  455. unsigned long flags;
  456. sscanf(buf, "%lX", &tmp);
  457. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  458. val = (unsigned char)tmp;
  459. spin_lock_irqsave(&event_lock, flags);
  460. SET_PORT_BITS(TLCLK_REG1, 0xfe, val);
  461. spin_unlock_irqrestore(&event_lock, flags);
  462. return strnlen(buf, count);
  463. }
  464. static DEVICE_ATTR(select_redundant_clock, (S_IWUSR|S_IWGRP), NULL,
  465. store_select_redundant_clock);
  466. static ssize_t store_select_ref_frequency(struct device *d,
  467. struct device_attribute *attr, const char *buf, size_t count)
  468. {
  469. unsigned long tmp;
  470. unsigned char val;
  471. unsigned long flags;
  472. sscanf(buf, "%lX", &tmp);
  473. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  474. val = (unsigned char)tmp;
  475. spin_lock_irqsave(&event_lock, flags);
  476. SET_PORT_BITS(TLCLK_REG1, 0xfd, val);
  477. spin_unlock_irqrestore(&event_lock, flags);
  478. return strnlen(buf, count);
  479. }
  480. static DEVICE_ATTR(select_ref_frequency, (S_IWUSR|S_IWGRP), NULL,
  481. store_select_ref_frequency);
  482. static ssize_t store_filter_select(struct device *d,
  483. struct device_attribute *attr, const char *buf, size_t count)
  484. {
  485. unsigned long tmp;
  486. unsigned char val;
  487. unsigned long flags;
  488. sscanf(buf, "%lX", &tmp);
  489. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  490. val = (unsigned char)tmp;
  491. spin_lock_irqsave(&event_lock, flags);
  492. SET_PORT_BITS(TLCLK_REG0, 0xfb, val);
  493. spin_unlock_irqrestore(&event_lock, flags);
  494. return strnlen(buf, count);
  495. }
  496. static DEVICE_ATTR(filter_select, (S_IWUSR|S_IWGRP), NULL, store_filter_select);
  497. static ssize_t store_hardware_switching_mode(struct device *d,
  498. struct device_attribute *attr, const char *buf, size_t count)
  499. {
  500. unsigned long tmp;
  501. unsigned char val;
  502. unsigned long flags;
  503. sscanf(buf, "%lX", &tmp);
  504. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  505. val = (unsigned char)tmp;
  506. spin_lock_irqsave(&event_lock, flags);
  507. SET_PORT_BITS(TLCLK_REG0, 0xbf, val);
  508. spin_unlock_irqrestore(&event_lock, flags);
  509. return strnlen(buf, count);
  510. }
  511. static DEVICE_ATTR(hardware_switching_mode, (S_IWUSR|S_IWGRP), NULL,
  512. store_hardware_switching_mode);
  513. static ssize_t store_hardware_switching(struct device *d,
  514. struct device_attribute *attr, const char *buf, size_t count)
  515. {
  516. unsigned long tmp;
  517. unsigned char val;
  518. unsigned long flags;
  519. sscanf(buf, "%lX", &tmp);
  520. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  521. val = (unsigned char)tmp;
  522. spin_lock_irqsave(&event_lock, flags);
  523. SET_PORT_BITS(TLCLK_REG0, 0x7f, val);
  524. spin_unlock_irqrestore(&event_lock, flags);
  525. return strnlen(buf, count);
  526. }
  527. static DEVICE_ATTR(hardware_switching, (S_IWUSR|S_IWGRP), NULL,
  528. store_hardware_switching);
  529. static ssize_t store_refalign (struct device *d,
  530. struct device_attribute *attr, const char *buf, size_t count)
  531. {
  532. unsigned long tmp;
  533. unsigned long flags;
  534. sscanf(buf, "%lX", &tmp);
  535. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  536. spin_lock_irqsave(&event_lock, flags);
  537. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  538. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0x08);
  539. SET_PORT_BITS(TLCLK_REG0, 0xf7, 0);
  540. spin_unlock_irqrestore(&event_lock, flags);
  541. return strnlen(buf, count);
  542. }
  543. static DEVICE_ATTR(refalign, (S_IWUSR|S_IWGRP), NULL, store_refalign);
  544. static ssize_t store_mode_select (struct device *d,
  545. struct device_attribute *attr, const char *buf, size_t count)
  546. {
  547. unsigned long tmp;
  548. unsigned char val;
  549. unsigned long flags;
  550. sscanf(buf, "%lX", &tmp);
  551. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  552. val = (unsigned char)tmp;
  553. spin_lock_irqsave(&event_lock, flags);
  554. SET_PORT_BITS(TLCLK_REG0, 0xcf, val);
  555. spin_unlock_irqrestore(&event_lock, flags);
  556. return strnlen(buf, count);
  557. }
  558. static DEVICE_ATTR(mode_select, (S_IWUSR|S_IWGRP), NULL, store_mode_select);
  559. static ssize_t store_reset (struct device *d,
  560. struct device_attribute *attr, const char *buf, size_t count)
  561. {
  562. unsigned long tmp;
  563. unsigned char val;
  564. unsigned long flags;
  565. sscanf(buf, "%lX", &tmp);
  566. dev_dbg(d, "tmp = 0x%lX\n", tmp);
  567. val = (unsigned char)tmp;
  568. spin_lock_irqsave(&event_lock, flags);
  569. SET_PORT_BITS(TLCLK_REG4, 0xfd, val);
  570. spin_unlock_irqrestore(&event_lock, flags);
  571. return strnlen(buf, count);
  572. }
  573. static DEVICE_ATTR(reset, (S_IWUSR|S_IWGRP), NULL, store_reset);
  574. static struct attribute *tlclk_sysfs_entries[] = {
  575. &dev_attr_current_ref.attr,
  576. &dev_attr_telclock_version.attr,
  577. &dev_attr_alarms.attr,
  578. &dev_attr_received_ref_clk3a.attr,
  579. &dev_attr_received_ref_clk3b.attr,
  580. &dev_attr_enable_clk3a_output.attr,
  581. &dev_attr_enable_clk3b_output.attr,
  582. &dev_attr_enable_clkb1_output.attr,
  583. &dev_attr_enable_clka1_output.attr,
  584. &dev_attr_enable_clkb0_output.attr,
  585. &dev_attr_enable_clka0_output.attr,
  586. &dev_attr_select_amcb1_transmit_clock.attr,
  587. &dev_attr_select_amcb2_transmit_clock.attr,
  588. &dev_attr_select_redundant_clock.attr,
  589. &dev_attr_select_ref_frequency.attr,
  590. &dev_attr_filter_select.attr,
  591. &dev_attr_hardware_switching_mode.attr,
  592. &dev_attr_hardware_switching.attr,
  593. &dev_attr_refalign.attr,
  594. &dev_attr_mode_select.attr,
  595. &dev_attr_reset.attr,
  596. NULL
  597. };
  598. static struct attribute_group tlclk_attribute_group = {
  599. .name = NULL, /* put in device directory */
  600. .attrs = tlclk_sysfs_entries,
  601. };
  602. static struct platform_device *tlclk_device;
  603. static int __init tlclk_init(void)
  604. {
  605. int ret;
  606. ret = register_chrdev(tlclk_major, "telco_clock", &tlclk_fops);
  607. if (ret < 0) {
  608. printk(KERN_ERR "tlclk: can't get major %d.\n", tlclk_major);
  609. return ret;
  610. }
  611. tlclk_major = ret;
  612. alarm_events = kzalloc( sizeof(struct tlclk_alarms), GFP_KERNEL);
  613. if (!alarm_events)
  614. goto out1;
  615. /* Read telecom clock IRQ number (Set by BIOS) */
  616. if (!request_region(TLCLK_BASE, 8, "telco_clock")) {
  617. printk(KERN_ERR "tlclk: request_region 0x%X failed.\n",
  618. TLCLK_BASE);
  619. ret = -EBUSY;
  620. goto out2;
  621. }
  622. telclk_interrupt = (inb(TLCLK_REG7) & 0x0f);
  623. if (0x0F == telclk_interrupt ) { /* not MCPBL0010 ? */
  624. printk(KERN_ERR "telclk_interrup = 0x%x non-mcpbl0010 hw.\n",
  625. telclk_interrupt);
  626. ret = -ENXIO;
  627. goto out3;
  628. }
  629. init_timer(&switchover_timer);
  630. ret = misc_register(&tlclk_miscdev);
  631. if (ret < 0) {
  632. printk(KERN_ERR "tlclk: misc_register returns %d.\n", ret);
  633. ret = -EBUSY;
  634. goto out3;
  635. }
  636. tlclk_device = platform_device_register_simple("telco_clock",
  637. -1, NULL, 0);
  638. if (!tlclk_device) {
  639. printk(KERN_ERR "tlclk: platform_device_register failed.\n");
  640. ret = -EBUSY;
  641. goto out4;
  642. }
  643. ret = sysfs_create_group(&tlclk_device->dev.kobj,
  644. &tlclk_attribute_group);
  645. if (ret) {
  646. printk(KERN_ERR "tlclk: failed to create sysfs device attributes.\n");
  647. sysfs_remove_group(&tlclk_device->dev.kobj,
  648. &tlclk_attribute_group);
  649. goto out5;
  650. }
  651. return 0;
  652. out5:
  653. platform_device_unregister(tlclk_device);
  654. out4:
  655. misc_deregister(&tlclk_miscdev);
  656. out3:
  657. release_region(TLCLK_BASE, 8);
  658. out2:
  659. kfree(alarm_events);
  660. out1:
  661. unregister_chrdev(tlclk_major, "telco_clock");
  662. return ret;
  663. }
  664. static void __exit tlclk_cleanup(void)
  665. {
  666. sysfs_remove_group(&tlclk_device->dev.kobj, &tlclk_attribute_group);
  667. platform_device_unregister(tlclk_device);
  668. misc_deregister(&tlclk_miscdev);
  669. unregister_chrdev(tlclk_major, "telco_clock");
  670. release_region(TLCLK_BASE, 8);
  671. del_timer_sync(&switchover_timer);
  672. kfree(alarm_events);
  673. }
  674. static void switchover_timeout(unsigned long data)
  675. {
  676. if ((data & 1)) {
  677. if ((inb(TLCLK_REG1) & 0x08) != (data & 0x08))
  678. alarm_events->switchover_primary++;
  679. } else {
  680. if ((inb(TLCLK_REG1) & 0x08) != (data & 0x08))
  681. alarm_events->switchover_secondary++;
  682. }
  683. /* Alarm processing is done, wake up read task */
  684. del_timer(&switchover_timer);
  685. got_event = 1;
  686. wake_up(&wq);
  687. }
  688. static irqreturn_t tlclk_interrupt(int irq, void *dev_id)
  689. {
  690. unsigned long flags;
  691. spin_lock_irqsave(&event_lock, flags);
  692. /* Read and clear interrupt events */
  693. int_events = inb(TLCLK_REG6);
  694. /* Primary_Los changed from 0 to 1 ? */
  695. if (int_events & PRI_LOS_01_MASK) {
  696. if (inb(TLCLK_REG2) & SEC_LOST_MASK)
  697. alarm_events->lost_clocks++;
  698. else
  699. alarm_events->lost_primary_clock++;
  700. }
  701. /* Primary_Los changed from 1 to 0 ? */
  702. if (int_events & PRI_LOS_10_MASK) {
  703. alarm_events->primary_clock_back++;
  704. SET_PORT_BITS(TLCLK_REG1, 0xFE, 1);
  705. }
  706. /* Secondary_Los changed from 0 to 1 ? */
  707. if (int_events & SEC_LOS_01_MASK) {
  708. if (inb(TLCLK_REG2) & PRI_LOST_MASK)
  709. alarm_events->lost_clocks++;
  710. else
  711. alarm_events->lost_secondary_clock++;
  712. }
  713. /* Secondary_Los changed from 1 to 0 ? */
  714. if (int_events & SEC_LOS_10_MASK) {
  715. alarm_events->secondary_clock_back++;
  716. SET_PORT_BITS(TLCLK_REG1, 0xFE, 0);
  717. }
  718. if (int_events & HOLDOVER_10_MASK)
  719. alarm_events->pll_end_holdover++;
  720. if (int_events & UNLOCK_01_MASK)
  721. alarm_events->pll_lost_sync++;
  722. if (int_events & UNLOCK_10_MASK)
  723. alarm_events->pll_sync++;
  724. /* Holdover changed from 0 to 1 ? */
  725. if (int_events & HOLDOVER_01_MASK) {
  726. alarm_events->pll_holdover++;
  727. /* TIMEOUT in ~10ms */
  728. switchover_timer.expires = jiffies + msecs_to_jiffies(10);
  729. switchover_timer.data = inb(TLCLK_REG1);
  730. add_timer(&switchover_timer);
  731. } else {
  732. got_event = 1;
  733. wake_up(&wq);
  734. }
  735. spin_unlock_irqrestore(&event_lock, flags);
  736. return IRQ_HANDLED;
  737. }
  738. module_init(tlclk_init);
  739. module_exit(tlclk_cleanup);