fdc-io.c 37 KB

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  1. /*
  2. * Copyright (C) 1993-1996 Bas Laarhoven,
  3. * (C) 1996-1997 Claus-Justus Heine.
  4. This program is free software; you can redistribute it and/or modify
  5. it under the terms of the GNU General Public License as published by
  6. the Free Software Foundation; either version 2, or (at your option)
  7. any later version.
  8. This program is distributed in the hope that it will be useful,
  9. but WITHOUT ANY WARRANTY; without even the implied warranty of
  10. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. GNU General Public License for more details.
  12. You should have received a copy of the GNU General Public License
  13. along with this program; see the file COPYING. If not, write to
  14. the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  15. *
  16. * $Source: /homes/cvs/ftape-stacked/ftape/lowlevel/fdc-io.c,v $
  17. * $Revision: 1.7.4.2 $
  18. * $Date: 1997/11/16 14:48:17 $
  19. *
  20. * This file contains the low-level floppy disk interface code
  21. * for the QIC-40/80/3010/3020 floppy-tape driver "ftape" for
  22. * Linux.
  23. */
  24. #include <linux/errno.h>
  25. #include <linux/sched.h>
  26. #include <linux/ioport.h>
  27. #include <linux/interrupt.h>
  28. #include <linux/kernel.h>
  29. #include <asm/system.h>
  30. #include <asm/io.h>
  31. #include <asm/dma.h>
  32. #include <asm/irq.h>
  33. #include <linux/ftape.h>
  34. #include <linux/qic117.h>
  35. #include "../lowlevel/ftape-tracing.h"
  36. #include "../lowlevel/fdc-io.h"
  37. #include "../lowlevel/fdc-isr.h"
  38. #include "../lowlevel/ftape-io.h"
  39. #include "../lowlevel/ftape-rw.h"
  40. #include "../lowlevel/ftape-ctl.h"
  41. #include "../lowlevel/ftape-calibr.h"
  42. #include "../lowlevel/fc-10.h"
  43. /* Global vars.
  44. */
  45. static int ftape_motor;
  46. volatile int ftape_current_cylinder = -1;
  47. volatile fdc_mode_enum fdc_mode = fdc_idle;
  48. fdc_config_info fdc;
  49. DECLARE_WAIT_QUEUE_HEAD(ftape_wait_intr);
  50. unsigned int ft_fdc_base = CONFIG_FT_FDC_BASE;
  51. unsigned int ft_fdc_irq = CONFIG_FT_FDC_IRQ;
  52. unsigned int ft_fdc_dma = CONFIG_FT_FDC_DMA;
  53. unsigned int ft_fdc_threshold = CONFIG_FT_FDC_THR; /* bytes */
  54. unsigned int ft_fdc_rate_limit = CONFIG_FT_FDC_MAX_RATE; /* bits/sec */
  55. int ft_probe_fc10 = CONFIG_FT_PROBE_FC10;
  56. int ft_mach2 = CONFIG_FT_MACH2;
  57. /* Local vars.
  58. */
  59. static spinlock_t fdc_io_lock;
  60. static unsigned int fdc_calibr_count;
  61. static unsigned int fdc_calibr_time;
  62. static int fdc_status;
  63. volatile __u8 fdc_head; /* FDC head from sector id */
  64. volatile __u8 fdc_cyl; /* FDC track from sector id */
  65. volatile __u8 fdc_sect; /* FDC sector from sector id */
  66. static int fdc_data_rate = 500; /* data rate (Kbps) */
  67. static int fdc_rate_code; /* data rate code (0 == 500 Kbps) */
  68. static int fdc_seek_rate = 2; /* step rate (msec) */
  69. static void (*do_ftape) (void);
  70. static int fdc_fifo_state; /* original fifo setting - fifo enabled */
  71. static int fdc_fifo_thr; /* original fifo setting - threshold */
  72. static int fdc_lock_state; /* original lock setting - locked */
  73. static int fdc_fifo_locked; /* has fifo && lock set ? */
  74. static __u8 fdc_precomp; /* default precomp. value (nsec) */
  75. static __u8 fdc_prec_code; /* fdc precomp. select code */
  76. static char ftape_id[] = "ftape"; /* used by request irq and free irq */
  77. static int fdc_set_seek_rate(int seek_rate);
  78. void fdc_catch_stray_interrupts(int count)
  79. {
  80. unsigned long flags;
  81. spin_lock_irqsave(&fdc_io_lock, flags);
  82. if (count == 0) {
  83. ft_expected_stray_interrupts = 0;
  84. } else {
  85. ft_expected_stray_interrupts += count;
  86. }
  87. spin_unlock_irqrestore(&fdc_io_lock, flags);
  88. }
  89. /* Wait during a timeout period for a given FDC status.
  90. * If usecs == 0 then just test status, else wait at least for usecs.
  91. * Returns -ETIME on timeout. Function must be calibrated first !
  92. */
  93. static int fdc_wait(unsigned int usecs, __u8 mask, __u8 state)
  94. {
  95. int count_1 = (fdc_calibr_count * usecs +
  96. fdc_calibr_count - 1) / fdc_calibr_time;
  97. do {
  98. fdc_status = inb_p(fdc.msr);
  99. if ((fdc_status & mask) == state) {
  100. return 0;
  101. }
  102. } while (count_1-- >= 0);
  103. return -ETIME;
  104. }
  105. int fdc_ready_wait(unsigned int usecs)
  106. {
  107. return fdc_wait(usecs, FDC_DATA_READY | FDC_BUSY, FDC_DATA_READY);
  108. }
  109. /* Why can't we just use udelay()?
  110. */
  111. static void fdc_usec_wait(unsigned int usecs)
  112. {
  113. fdc_wait(usecs, 0, 1); /* will always timeout ! */
  114. }
  115. static int fdc_ready_out_wait(unsigned int usecs)
  116. {
  117. fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
  118. return fdc_wait(usecs, FDC_DATA_OUT_READY, FDC_DATA_OUT_READY);
  119. }
  120. void fdc_wait_calibrate(void)
  121. {
  122. ftape_calibrate("fdc_wait",
  123. fdc_usec_wait, &fdc_calibr_count, &fdc_calibr_time);
  124. }
  125. /* Wait for a (short) while for the FDC to become ready
  126. * and transfer the next command byte.
  127. * Return -ETIME on timeout on getting ready (depends on hardware!).
  128. */
  129. static int fdc_write(const __u8 data)
  130. {
  131. fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
  132. if (fdc_wait(150, FDC_DATA_READY_MASK, FDC_DATA_IN_READY) < 0) {
  133. return -ETIME;
  134. } else {
  135. outb(data, fdc.fifo);
  136. return 0;
  137. }
  138. }
  139. /* Wait for a (short) while for the FDC to become ready
  140. * and transfer the next result byte.
  141. * Return -ETIME if timeout on getting ready (depends on hardware!).
  142. */
  143. static int fdc_read(__u8 * data)
  144. {
  145. fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
  146. if (fdc_wait(150, FDC_DATA_READY_MASK, FDC_DATA_OUT_READY) < 0) {
  147. return -ETIME;
  148. } else {
  149. *data = inb(fdc.fifo);
  150. return 0;
  151. }
  152. }
  153. /* Output a cmd_len long command string to the FDC.
  154. * The FDC should be ready to receive a new command or
  155. * an error (EBUSY or ETIME) will occur.
  156. */
  157. int fdc_command(const __u8 * cmd_data, int cmd_len)
  158. {
  159. int result = 0;
  160. unsigned long flags;
  161. int count = cmd_len;
  162. int retry = 0;
  163. #ifdef TESTING
  164. static unsigned int last_time;
  165. unsigned int time;
  166. #endif
  167. TRACE_FUN(ft_t_any);
  168. fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
  169. spin_lock_irqsave(&fdc_io_lock, flags);
  170. if (!in_interrupt())
  171. /* Yes, I know, too much comments inside this function
  172. * ...
  173. *
  174. * Yet another bug in the original driver. All that
  175. * havoc is caused by the fact that the isr() sends
  176. * itself a command to the floppy tape driver (pause,
  177. * micro step pause). Now, the problem is that
  178. * commands are transmitted via the fdc_seek
  179. * command. But: the fdc performs seeks in the
  180. * background i.e. it doesn't signal busy while
  181. * sending the step pulses to the drive. Therefore the
  182. * non-interrupt level driver has no chance to tell
  183. * whether the isr() just has issued a seek. Therefore
  184. * we HAVE TO have a look at the ft_hide_interrupt
  185. * flag: it signals the non-interrupt level part of
  186. * the driver that it has to wait for the fdc until it
  187. * has completet seeking.
  188. *
  189. * THIS WAS PRESUMABLY THE REASON FOR ALL THAT
  190. * "fdc_read timeout" errors, I HOPE :-)
  191. */
  192. if (ft_hide_interrupt) {
  193. restore_flags(flags);
  194. TRACE(ft_t_info,
  195. "Waiting for the isr() completing fdc_seek()");
  196. if (fdc_interrupt_wait(2 * FT_SECOND) < 0) {
  197. TRACE(ft_t_warn,
  198. "Warning: timeout waiting for isr() seek to complete");
  199. }
  200. if (ft_hide_interrupt || !ft_seek_completed) {
  201. /* There cannot be another
  202. * interrupt. The isr() only stops
  203. * the tape and the next interrupt
  204. * won't come until we have send our
  205. * command to the drive.
  206. */
  207. TRACE_ABORT(-EIO, ft_t_bug,
  208. "BUG? isr() is still seeking?\n"
  209. KERN_INFO "hide: %d\n"
  210. KERN_INFO "seek: %d",
  211. ft_hide_interrupt,
  212. ft_seek_completed);
  213. }
  214. fdc_usec_wait(FT_RQM_DELAY); /* wait for valid RQM status */
  215. spin_lock_irqsave(&fdc_io_lock, flags);
  216. }
  217. fdc_status = inb(fdc.msr);
  218. if ((fdc_status & FDC_DATA_READY_MASK) != FDC_DATA_IN_READY) {
  219. spin_unlock_irqrestore(&fdc_io_lock, flags);
  220. TRACE_ABORT(-EBUSY, ft_t_err, "fdc not ready");
  221. }
  222. fdc_mode = *cmd_data; /* used by isr */
  223. #ifdef TESTING
  224. if (fdc_mode == FDC_SEEK) {
  225. time = ftape_timediff(last_time, ftape_timestamp());
  226. if (time < 6000) {
  227. TRACE(ft_t_bug,"Warning: short timeout between seek commands: %d",
  228. time);
  229. }
  230. }
  231. #endif
  232. if (!in_interrupt()) {
  233. /* shouldn't be cleared if called from isr
  234. */
  235. ft_interrupt_seen = 0;
  236. }
  237. while (count) {
  238. result = fdc_write(*cmd_data);
  239. if (result < 0) {
  240. TRACE(ft_t_fdc_dma,
  241. "fdc_mode = %02x, status = %02x at index %d",
  242. (int) fdc_mode, (int) fdc_status,
  243. cmd_len - count);
  244. if (++retry <= 3) {
  245. TRACE(ft_t_warn, "fdc_write timeout, retry");
  246. } else {
  247. TRACE(ft_t_err, "fdc_write timeout, fatal");
  248. /* recover ??? */
  249. break;
  250. }
  251. } else {
  252. --count;
  253. ++cmd_data;
  254. }
  255. }
  256. #ifdef TESTING
  257. if (fdc_mode == FDC_SEEK) {
  258. last_time = ftape_timestamp();
  259. }
  260. #endif
  261. spin_unlock_irqrestore(&fdc_io_lock, flags);
  262. TRACE_EXIT result;
  263. }
  264. /* Input a res_len long result string from the FDC.
  265. * The FDC should be ready to send the result or an error
  266. * (EBUSY or ETIME) will occur.
  267. */
  268. int fdc_result(__u8 * res_data, int res_len)
  269. {
  270. int result = 0;
  271. unsigned long flags;
  272. int count = res_len;
  273. int retry = 0;
  274. TRACE_FUN(ft_t_any);
  275. spin_lock_irqsave(&fdc_io_lock, flags);
  276. fdc_status = inb(fdc.msr);
  277. if ((fdc_status & FDC_DATA_READY_MASK) != FDC_DATA_OUT_READY) {
  278. TRACE(ft_t_err, "fdc not ready");
  279. result = -EBUSY;
  280. } else while (count) {
  281. if (!(fdc_status & FDC_BUSY)) {
  282. spin_unlock_irqrestore(&fdc_io_lock, flags);
  283. TRACE_ABORT(-EIO, ft_t_err, "premature end of result phase");
  284. }
  285. result = fdc_read(res_data);
  286. if (result < 0) {
  287. TRACE(ft_t_fdc_dma,
  288. "fdc_mode = %02x, status = %02x at index %d",
  289. (int) fdc_mode,
  290. (int) fdc_status,
  291. res_len - count);
  292. if (++retry <= 3) {
  293. TRACE(ft_t_warn, "fdc_read timeout, retry");
  294. } else {
  295. TRACE(ft_t_err, "fdc_read timeout, fatal");
  296. /* recover ??? */
  297. break;
  298. ++retry;
  299. }
  300. } else {
  301. --count;
  302. ++res_data;
  303. }
  304. }
  305. spin_unlock_irqrestore(&fdc_io_lock, flags);
  306. fdc_usec_wait(FT_RQM_DELAY); /* allow FDC to negate BSY */
  307. TRACE_EXIT result;
  308. }
  309. /* Handle command and result phases for
  310. * commands without data phase.
  311. */
  312. static int fdc_issue_command(const __u8 * out_data, int out_count,
  313. __u8 * in_data, int in_count)
  314. {
  315. TRACE_FUN(ft_t_any);
  316. if (out_count > 0) {
  317. TRACE_CATCH(fdc_command(out_data, out_count),);
  318. }
  319. /* will take 24 - 30 usec for fdc_sense_drive_status and
  320. * fdc_sense_interrupt_status commands.
  321. * 35 fails sometimes (5/9/93 SJL)
  322. * On a loaded system it incidentally takes longer than
  323. * this for the fdc to get ready ! ?????? WHY ??????
  324. * So until we know what's going on use a very long timeout.
  325. */
  326. TRACE_CATCH(fdc_ready_out_wait(500 /* usec */),);
  327. if (in_count > 0) {
  328. TRACE_CATCH(fdc_result(in_data, in_count),
  329. TRACE(ft_t_err, "result phase aborted"));
  330. }
  331. TRACE_EXIT 0;
  332. }
  333. /* Wait for FDC interrupt with timeout (in milliseconds).
  334. * Signals are blocked so the wait will not be aborted.
  335. * Note: interrupts must be enabled ! (23/05/93 SJL)
  336. */
  337. int fdc_interrupt_wait(unsigned int time)
  338. {
  339. DECLARE_WAITQUEUE(wait,current);
  340. sigset_t old_sigmask;
  341. static int resetting;
  342. long timeout;
  343. TRACE_FUN(ft_t_fdc_dma);
  344. if (waitqueue_active(&ftape_wait_intr)) {
  345. TRACE_ABORT(-EIO, ft_t_err, "error: nested call");
  346. }
  347. /* timeout time will be up to USPT microseconds too long ! */
  348. timeout = (1000 * time + FT_USPT - 1) / FT_USPT;
  349. spin_lock_irq(&current->sighand->siglock);
  350. old_sigmask = current->blocked;
  351. sigfillset(&current->blocked);
  352. recalc_sigpending();
  353. spin_unlock_irq(&current->sighand->siglock);
  354. set_current_state(TASK_INTERRUPTIBLE);
  355. add_wait_queue(&ftape_wait_intr, &wait);
  356. while (!ft_interrupt_seen && timeout)
  357. timeout = schedule_timeout_interruptible(timeout);
  358. spin_lock_irq(&current->sighand->siglock);
  359. current->blocked = old_sigmask;
  360. recalc_sigpending();
  361. spin_unlock_irq(&current->sighand->siglock);
  362. remove_wait_queue(&ftape_wait_intr, &wait);
  363. /* the following IS necessary. True: as well
  364. * wake_up_interruptible() as the schedule() set TASK_RUNNING
  365. * when they wakeup a task, BUT: it may very well be that
  366. * ft_interrupt_seen is already set to 1 when we enter here
  367. * in which case schedule() gets never called, and
  368. * TASK_RUNNING never set. This has the funny effect that we
  369. * execute all the code until we leave kernel space, but then
  370. * the task is stopped (a task CANNOT be preempted while in
  371. * kernel mode. Sending a pair of SIGSTOP/SIGCONT to the
  372. * tasks wakes it up again. Funny! :-)
  373. */
  374. current->state = TASK_RUNNING;
  375. if (ft_interrupt_seen) { /* woken up by interrupt */
  376. ft_interrupt_seen = 0;
  377. TRACE_EXIT 0;
  378. }
  379. /* Original comment:
  380. * In first instance, next statement seems unnecessary since
  381. * it will be cleared in fdc_command. However, a small part of
  382. * the software seems to rely on this being cleared here
  383. * (ftape_close might fail) so stick to it until things get fixed !
  384. */
  385. /* My deeply sought of knowledge:
  386. * Behold NO! It is obvious. fdc_reset() doesn't call fdc_command()
  387. * but nevertheless uses fdc_interrupt_wait(). OF COURSE this needs to
  388. * be reset here.
  389. */
  390. ft_interrupt_seen = 0; /* clear for next call */
  391. if (!resetting) {
  392. resetting = 1; /* break infinite recursion if reset fails */
  393. TRACE(ft_t_any, "cleanup reset");
  394. fdc_reset();
  395. resetting = 0;
  396. }
  397. TRACE_EXIT (signal_pending(current)) ? -EINTR : -ETIME;
  398. }
  399. /* Start/stop drive motor. Enable DMA mode.
  400. */
  401. void fdc_motor(int motor)
  402. {
  403. int unit = ft_drive_sel;
  404. int data = unit | FDC_RESET_NOT | FDC_DMA_MODE;
  405. TRACE_FUN(ft_t_any);
  406. ftape_motor = motor;
  407. if (ftape_motor) {
  408. data |= FDC_MOTOR_0 << unit;
  409. TRACE(ft_t_noise, "turning motor %d on", unit);
  410. } else {
  411. TRACE(ft_t_noise, "turning motor %d off", unit);
  412. }
  413. if (ft_mach2) {
  414. outb_p(data, fdc.dor2);
  415. } else {
  416. outb_p(data, fdc.dor);
  417. }
  418. ftape_sleep(10 * FT_MILLISECOND);
  419. TRACE_EXIT;
  420. }
  421. static void fdc_update_dsr(void)
  422. {
  423. TRACE_FUN(ft_t_any);
  424. TRACE(ft_t_flow, "rate = %d Kbps, precomp = %d ns",
  425. fdc_data_rate, fdc_precomp);
  426. if (fdc.type >= i82077) {
  427. outb_p((fdc_rate_code & 0x03) | fdc_prec_code, fdc.dsr);
  428. } else {
  429. outb_p(fdc_rate_code & 0x03, fdc.ccr);
  430. }
  431. TRACE_EXIT;
  432. }
  433. void fdc_set_write_precomp(int precomp)
  434. {
  435. TRACE_FUN(ft_t_any);
  436. TRACE(ft_t_noise, "New precomp: %d nsec", precomp);
  437. fdc_precomp = precomp;
  438. /* write precompensation can be set in multiples of 41.67 nsec.
  439. * round the parameter to the nearest multiple and convert it
  440. * into a fdc setting. Note that 0 means default to the fdc,
  441. * 7 is used instead of that.
  442. */
  443. fdc_prec_code = ((fdc_precomp + 21) / 42) << 2;
  444. if (fdc_prec_code == 0 || fdc_prec_code > (6 << 2)) {
  445. fdc_prec_code = 7 << 2;
  446. }
  447. fdc_update_dsr();
  448. TRACE_EXIT;
  449. }
  450. /* Reprogram the 82078 registers to use Data Rate Table 1 on all drives.
  451. */
  452. static void fdc_set_drive_specs(void)
  453. {
  454. __u8 cmd[] = { FDC_DRIVE_SPEC, 0x00, 0x00, 0x00, 0x00, 0xc0};
  455. int result;
  456. TRACE_FUN(ft_t_any);
  457. TRACE(ft_t_flow, "Setting of drive specs called");
  458. if (fdc.type >= i82078_1) {
  459. cmd[1] = (0 << 5) | (2 << 2);
  460. cmd[2] = (1 << 5) | (2 << 2);
  461. cmd[3] = (2 << 5) | (2 << 2);
  462. cmd[4] = (3 << 5) | (2 << 2);
  463. result = fdc_command(cmd, NR_ITEMS(cmd));
  464. if (result < 0) {
  465. TRACE(ft_t_err, "Setting of drive specs failed");
  466. }
  467. }
  468. TRACE_EXIT;
  469. }
  470. /* Select clock for fdc, must correspond with tape drive setting !
  471. * This also influences the fdc timing so we must adjust some values.
  472. */
  473. int fdc_set_data_rate(int rate)
  474. {
  475. int bad_rate = 0;
  476. TRACE_FUN(ft_t_any);
  477. /* Select clock for fdc, must correspond with tape drive setting !
  478. * This also influences the fdc timing so we must adjust some values.
  479. */
  480. TRACE(ft_t_fdc_dma, "new rate = %d", rate);
  481. switch (rate) {
  482. case 250:
  483. fdc_rate_code = fdc_data_rate_250;
  484. break;
  485. case 500:
  486. fdc_rate_code = fdc_data_rate_500;
  487. break;
  488. case 1000:
  489. if (fdc.type < i82077) {
  490. bad_rate = 1;
  491. } else {
  492. fdc_rate_code = fdc_data_rate_1000;
  493. }
  494. break;
  495. case 2000:
  496. if (fdc.type < i82078_1) {
  497. bad_rate = 1;
  498. } else {
  499. fdc_rate_code = fdc_data_rate_2000;
  500. }
  501. break;
  502. default:
  503. bad_rate = 1;
  504. }
  505. if (bad_rate) {
  506. TRACE_ABORT(-EIO,
  507. ft_t_fdc_dma, "%d is not a valid data rate", rate);
  508. }
  509. fdc_data_rate = rate;
  510. fdc_update_dsr();
  511. fdc_set_seek_rate(fdc_seek_rate); /* clock changed! */
  512. ftape_udelay(1000);
  513. TRACE_EXIT 0;
  514. }
  515. /* keep the unit select if keep_select is != 0,
  516. */
  517. static void fdc_dor_reset(int keep_select)
  518. {
  519. __u8 fdc_ctl = ft_drive_sel;
  520. if (keep_select != 0) {
  521. fdc_ctl |= FDC_DMA_MODE;
  522. if (ftape_motor) {
  523. fdc_ctl |= FDC_MOTOR_0 << ft_drive_sel;
  524. }
  525. }
  526. ftape_udelay(10); /* ??? but seems to be necessary */
  527. if (ft_mach2) {
  528. outb_p(fdc_ctl & 0x0f, fdc.dor);
  529. outb_p(fdc_ctl, fdc.dor2);
  530. } else {
  531. outb_p(fdc_ctl, fdc.dor);
  532. }
  533. fdc_usec_wait(10); /* delay >= 14 fdc clocks */
  534. if (keep_select == 0) {
  535. fdc_ctl = 0;
  536. }
  537. fdc_ctl |= FDC_RESET_NOT;
  538. if (ft_mach2) {
  539. outb_p(fdc_ctl & 0x0f, fdc.dor);
  540. outb_p(fdc_ctl, fdc.dor2);
  541. } else {
  542. outb_p(fdc_ctl, fdc.dor);
  543. }
  544. }
  545. /* Reset the floppy disk controller. Leave the ftape_unit selected.
  546. */
  547. void fdc_reset(void)
  548. {
  549. int st0;
  550. int i;
  551. int dummy;
  552. unsigned long flags;
  553. TRACE_FUN(ft_t_any);
  554. spin_lock_irqsave(&fdc_io_lock, flags);
  555. fdc_dor_reset(1); /* keep unit selected */
  556. fdc_mode = fdc_idle;
  557. /* maybe the spin_lock_irq* pair is not necessary, BUT:
  558. * the following line MUST be here. Otherwise fdc_interrupt_wait()
  559. * won't wait. Note that fdc_reset() is called from
  560. * ftape_dumb_stop() when the fdc is busy transferring data. In this
  561. * case fdc_isr() MOST PROBABLY sets ft_interrupt_seen, and tries
  562. * to get the result bytes from the fdc etc. CLASH.
  563. */
  564. ft_interrupt_seen = 0;
  565. /* Program data rate
  566. */
  567. fdc_update_dsr(); /* restore data rate and precomp */
  568. spin_unlock_irqrestore(&fdc_io_lock, flags);
  569. /*
  570. * Wait for first polling cycle to complete
  571. */
  572. if (fdc_interrupt_wait(1 * FT_SECOND) < 0) {
  573. TRACE(ft_t_err, "no drive polling interrupt!");
  574. } else { /* clear all disk-changed statuses */
  575. for (i = 0; i < 4; ++i) {
  576. if(fdc_sense_interrupt_status(&st0, &dummy) != 0) {
  577. TRACE(ft_t_err, "sense failed for %d", i);
  578. }
  579. if (i == ft_drive_sel) {
  580. ftape_current_cylinder = dummy;
  581. }
  582. }
  583. TRACE(ft_t_noise, "drive polling completed");
  584. }
  585. /*
  586. * SPECIFY COMMAND
  587. */
  588. fdc_set_seek_rate(fdc_seek_rate);
  589. /*
  590. * DRIVE SPECIFICATION COMMAND (if fdc type known)
  591. */
  592. if (fdc.type >= i82078_1) {
  593. fdc_set_drive_specs();
  594. }
  595. TRACE_EXIT;
  596. }
  597. #if !defined(CLK_48MHZ)
  598. # define CLK_48MHZ 1
  599. #endif
  600. /* When we're done, put the fdc into reset mode so that the regular
  601. * floppy disk driver will figure out that something is wrong and
  602. * initialize the controller the way it wants.
  603. */
  604. void fdc_disable(void)
  605. {
  606. __u8 cmd1[] = {FDC_CONFIGURE, 0x00, 0x00, 0x00};
  607. __u8 cmd2[] = {FDC_LOCK};
  608. __u8 cmd3[] = {FDC_UNLOCK};
  609. __u8 stat[1];
  610. TRACE_FUN(ft_t_flow);
  611. if (!fdc_fifo_locked) {
  612. fdc_reset();
  613. TRACE_EXIT;
  614. }
  615. if (fdc_issue_command(cmd3, 1, stat, 1) < 0 || stat[0] != 0x00) {
  616. fdc_dor_reset(0);
  617. TRACE_ABORT(/**/, ft_t_bug,
  618. "couldn't unlock fifo, configuration remains changed");
  619. }
  620. fdc_fifo_locked = 0;
  621. if (CLK_48MHZ && fdc.type >= i82078) {
  622. cmd1[0] |= FDC_CLK48_BIT;
  623. }
  624. cmd1[2] = ((fdc_fifo_state) ? 0 : 0x20) + (fdc_fifo_thr - 1);
  625. if (fdc_command(cmd1, NR_ITEMS(cmd1)) < 0) {
  626. fdc_dor_reset(0);
  627. TRACE_ABORT(/**/, ft_t_bug,
  628. "couldn't reconfigure fifo to old state");
  629. }
  630. if (fdc_lock_state &&
  631. fdc_issue_command(cmd2, 1, stat, 1) < 0) {
  632. fdc_dor_reset(0);
  633. TRACE_ABORT(/**/, ft_t_bug, "couldn't lock old state again");
  634. }
  635. TRACE(ft_t_noise, "fifo restored: %sabled, thr. %d, %slocked",
  636. fdc_fifo_state ? "en" : "dis",
  637. fdc_fifo_thr, (fdc_lock_state) ? "" : "not ");
  638. fdc_dor_reset(0);
  639. TRACE_EXIT;
  640. }
  641. /* Specify FDC seek-rate (milliseconds)
  642. */
  643. static int fdc_set_seek_rate(int seek_rate)
  644. {
  645. /* set step rate, dma mode, and minimal head load and unload times
  646. */
  647. __u8 in[3] = { FDC_SPECIFY, 1, (1 << 1)};
  648. fdc_seek_rate = seek_rate;
  649. in[1] |= (16 - (fdc_data_rate * fdc_seek_rate) / 500) << 4;
  650. return fdc_command(in, 3);
  651. }
  652. /* Sense drive status: get unit's drive status (ST3)
  653. */
  654. int fdc_sense_drive_status(int *st3)
  655. {
  656. __u8 out[2];
  657. __u8 in[1];
  658. TRACE_FUN(ft_t_any);
  659. out[0] = FDC_SENSED;
  660. out[1] = ft_drive_sel;
  661. TRACE_CATCH(fdc_issue_command(out, 2, in, 1),);
  662. *st3 = in[0];
  663. TRACE_EXIT 0;
  664. }
  665. /* Sense Interrupt Status command:
  666. * should be issued at the end of each seek.
  667. * get ST0 and current cylinder.
  668. */
  669. int fdc_sense_interrupt_status(int *st0, int *current_cylinder)
  670. {
  671. __u8 out[1];
  672. __u8 in[2];
  673. TRACE_FUN(ft_t_any);
  674. out[0] = FDC_SENSEI;
  675. TRACE_CATCH(fdc_issue_command(out, 1, in, 2),);
  676. *st0 = in[0];
  677. *current_cylinder = in[1];
  678. TRACE_EXIT 0;
  679. }
  680. /* step to track
  681. */
  682. int fdc_seek(int track)
  683. {
  684. __u8 out[3];
  685. int st0, pcn;
  686. #ifdef TESTING
  687. unsigned int time;
  688. #endif
  689. TRACE_FUN(ft_t_any);
  690. out[0] = FDC_SEEK;
  691. out[1] = ft_drive_sel;
  692. out[2] = track;
  693. #ifdef TESTING
  694. time = ftape_timestamp();
  695. #endif
  696. /* We really need this command to work !
  697. */
  698. ft_seek_completed = 0;
  699. TRACE_CATCH(fdc_command(out, 3),
  700. fdc_reset();
  701. TRACE(ft_t_noise, "destination was: %d, resetting FDC...",
  702. track));
  703. /* Handle interrupts until ft_seek_completed or timeout.
  704. */
  705. for (;;) {
  706. TRACE_CATCH(fdc_interrupt_wait(2 * FT_SECOND),);
  707. if (ft_seek_completed) {
  708. TRACE_CATCH(fdc_sense_interrupt_status(&st0, &pcn),);
  709. if ((st0 & ST0_SEEK_END) == 0) {
  710. TRACE_ABORT(-EIO, ft_t_err,
  711. "no seek-end after seek completion !??");
  712. }
  713. break;
  714. }
  715. }
  716. #ifdef TESTING
  717. time = ftape_timediff(time, ftape_timestamp()) / abs(track - ftape_current_cylinder);
  718. if ((time < 900 || time > 3100) && abs(track - ftape_current_cylinder) > 5) {
  719. TRACE(ft_t_warn, "Wrong FDC STEP interval: %d usecs (%d)",
  720. time, track - ftape_current_cylinder);
  721. }
  722. #endif
  723. /* Verify whether we issued the right tape command.
  724. */
  725. /* Verify that we seek to the proper track. */
  726. if (pcn != track) {
  727. TRACE_ABORT(-EIO, ft_t_err, "bad seek..");
  728. }
  729. ftape_current_cylinder = track;
  730. TRACE_EXIT 0;
  731. }
  732. static int perpend_mode; /* set if fdc is in perpendicular mode */
  733. static int perpend_off(void)
  734. {
  735. __u8 perpend[] = {FDC_PERPEND, 0x00};
  736. TRACE_FUN(ft_t_any);
  737. if (perpend_mode) {
  738. /* Turn off perpendicular mode */
  739. perpend[1] = 0x80;
  740. TRACE_CATCH(fdc_command(perpend, 2),
  741. TRACE(ft_t_err,"Perpendicular mode exit failed!"));
  742. perpend_mode = 0;
  743. }
  744. TRACE_EXIT 0;
  745. }
  746. static int handle_perpend(int segment_id)
  747. {
  748. __u8 perpend[] = {FDC_PERPEND, 0x00};
  749. TRACE_FUN(ft_t_any);
  750. /* When writing QIC-3020 tapes, turn on perpendicular mode
  751. * if tape is moving in forward direction (even tracks).
  752. */
  753. if (ft_qic_std == QIC_TAPE_QIC3020 &&
  754. ((segment_id / ft_segments_per_track) & 1) == 0) {
  755. /* FIXME: some i82077 seem to support perpendicular mode as
  756. * well.
  757. */
  758. #if 0
  759. if (fdc.type < i82077AA) {}
  760. #else
  761. if (fdc.type < i82077 && ft_data_rate < 1000) {
  762. #endif
  763. /* fdc does not support perpendicular mode: complain
  764. */
  765. TRACE_ABORT(-EIO, ft_t_err,
  766. "Your FDC does not support QIC-3020.");
  767. }
  768. perpend[1] = 0x03 /* 0x83 + (0x4 << ft_drive_sel) */ ;
  769. TRACE_CATCH(fdc_command(perpend, 2),
  770. TRACE(ft_t_err,"Perpendicular mode entry failed!"));
  771. TRACE(ft_t_flow, "Perpendicular mode set");
  772. perpend_mode = 1;
  773. TRACE_EXIT 0;
  774. }
  775. TRACE_EXIT perpend_off();
  776. }
  777. static inline void fdc_setup_dma(char mode,
  778. volatile void *addr, unsigned int count)
  779. {
  780. /* Program the DMA controller.
  781. */
  782. disable_dma(fdc.dma);
  783. clear_dma_ff(fdc.dma);
  784. set_dma_mode(fdc.dma, mode);
  785. set_dma_addr(fdc.dma, virt_to_bus((void*)addr));
  786. set_dma_count(fdc.dma, count);
  787. enable_dma(fdc.dma);
  788. }
  789. /* Setup fdc and dma for formatting the next segment
  790. */
  791. int fdc_setup_formatting(buffer_struct * buff)
  792. {
  793. unsigned long flags;
  794. __u8 out[6] = {
  795. FDC_FORMAT, 0x00, 3, 4 * FT_SECTORS_PER_SEGMENT, 0x00, 0x6b
  796. };
  797. TRACE_FUN(ft_t_any);
  798. TRACE_CATCH(handle_perpend(buff->segment_id),);
  799. /* Program the DMA controller.
  800. */
  801. TRACE(ft_t_fdc_dma,
  802. "phys. addr. = %lx", virt_to_bus((void*) buff->ptr));
  803. spin_lock_irqsave(&fdc_io_lock, flags);
  804. fdc_setup_dma(DMA_MODE_WRITE, buff->ptr, FT_SECTORS_PER_SEGMENT * 4);
  805. /* Issue FDC command to start reading/writing.
  806. */
  807. out[1] = ft_drive_sel;
  808. out[4] = buff->gap3;
  809. TRACE_CATCH(fdc_setup_error = fdc_command(out, sizeof(out)),
  810. restore_flags(flags); fdc_mode = fdc_idle);
  811. spin_unlock_irqrestore(&fdc_io_lock, flags);
  812. TRACE_EXIT 0;
  813. }
  814. /* Setup Floppy Disk Controller and DMA to read or write the next cluster
  815. * of good sectors from or to the current segment.
  816. */
  817. int fdc_setup_read_write(buffer_struct * buff, __u8 operation)
  818. {
  819. unsigned long flags;
  820. __u8 out[9];
  821. int dma_mode;
  822. TRACE_FUN(ft_t_any);
  823. switch(operation) {
  824. case FDC_VERIFY:
  825. if (fdc.type < i82077) {
  826. operation = FDC_READ;
  827. }
  828. case FDC_READ:
  829. case FDC_READ_DELETED:
  830. dma_mode = DMA_MODE_READ;
  831. TRACE(ft_t_fdc_dma, "xfer %d sectors to 0x%p",
  832. buff->sector_count, buff->ptr);
  833. TRACE_CATCH(perpend_off(),);
  834. break;
  835. case FDC_WRITE_DELETED:
  836. TRACE(ft_t_noise, "deleting segment %d", buff->segment_id);
  837. case FDC_WRITE:
  838. dma_mode = DMA_MODE_WRITE;
  839. /* When writing QIC-3020 tapes, turn on perpendicular mode
  840. * if tape is moving in forward direction (even tracks).
  841. */
  842. TRACE_CATCH(handle_perpend(buff->segment_id),);
  843. TRACE(ft_t_fdc_dma, "xfer %d sectors from 0x%p",
  844. buff->sector_count, buff->ptr);
  845. break;
  846. default:
  847. TRACE_ABORT(-EIO,
  848. ft_t_bug, "bug: invalid operation parameter");
  849. }
  850. TRACE(ft_t_fdc_dma, "phys. addr. = %lx",virt_to_bus((void*)buff->ptr));
  851. spin_lock_irqsave(&fdc_io_lock, flags);
  852. if (operation != FDC_VERIFY) {
  853. fdc_setup_dma(dma_mode, buff->ptr,
  854. FT_SECTOR_SIZE * buff->sector_count);
  855. }
  856. /* Issue FDC command to start reading/writing.
  857. */
  858. out[0] = operation;
  859. out[1] = ft_drive_sel;
  860. out[2] = buff->cyl;
  861. out[3] = buff->head;
  862. out[4] = buff->sect + buff->sector_offset;
  863. out[5] = 3; /* Sector size of 1K. */
  864. out[6] = out[4] + buff->sector_count - 1; /* last sector */
  865. out[7] = 109; /* Gap length. */
  866. out[8] = 0xff; /* No limit to transfer size. */
  867. TRACE(ft_t_fdc_dma, "C: 0x%02x, H: 0x%02x, R: 0x%02x, cnt: 0x%02x",
  868. out[2], out[3], out[4], out[6] - out[4] + 1);
  869. spin_unlock_irqrestore(&fdc_io_lock, flags);
  870. TRACE_CATCH(fdc_setup_error = fdc_command(out, 9),fdc_mode = fdc_idle);
  871. TRACE_EXIT 0;
  872. }
  873. int fdc_fifo_threshold(__u8 threshold,
  874. int *fifo_state, int *lock_state, int *fifo_thr)
  875. {
  876. const __u8 cmd0[] = {FDC_DUMPREGS};
  877. __u8 cmd1[] = {FDC_CONFIGURE, 0, (0x0f & (threshold - 1)), 0};
  878. const __u8 cmd2[] = {FDC_LOCK};
  879. const __u8 cmd3[] = {FDC_UNLOCK};
  880. __u8 reg[10];
  881. __u8 stat;
  882. int i;
  883. int result;
  884. TRACE_FUN(ft_t_any);
  885. if (CLK_48MHZ && fdc.type >= i82078) {
  886. cmd1[0] |= FDC_CLK48_BIT;
  887. }
  888. /* Dump fdc internal registers for examination
  889. */
  890. TRACE_CATCH(fdc_command(cmd0, NR_ITEMS(cmd0)),
  891. TRACE(ft_t_warn, "dumpreg cmd failed, fifo unchanged"));
  892. /* Now read fdc internal registers from fifo
  893. */
  894. for (i = 0; i < (int)NR_ITEMS(reg); ++i) {
  895. fdc_read(&reg[i]);
  896. TRACE(ft_t_fdc_dma, "Register %d = 0x%02x", i, reg[i]);
  897. }
  898. if (fifo_state && lock_state && fifo_thr) {
  899. *fifo_state = (reg[8] & 0x20) == 0;
  900. *lock_state = reg[7] & 0x80;
  901. *fifo_thr = 1 + (reg[8] & 0x0f);
  902. }
  903. TRACE(ft_t_noise,
  904. "original fifo state: %sabled, threshold %d, %slocked",
  905. ((reg[8] & 0x20) == 0) ? "en" : "dis",
  906. 1 + (reg[8] & 0x0f), (reg[7] & 0x80) ? "" : "not ");
  907. /* If fdc is already locked, unlock it first ! */
  908. if (reg[7] & 0x80) {
  909. fdc_ready_wait(100);
  910. TRACE_CATCH(fdc_issue_command(cmd3, NR_ITEMS(cmd3), &stat, 1),
  911. TRACE(ft_t_bug, "FDC unlock command failed, "
  912. "configuration unchanged"));
  913. }
  914. fdc_fifo_locked = 0;
  915. /* Enable fifo and set threshold at xx bytes to allow a
  916. * reasonably large latency and reduce number of dma bursts.
  917. */
  918. fdc_ready_wait(100);
  919. if ((result = fdc_command(cmd1, NR_ITEMS(cmd1))) < 0) {
  920. TRACE(ft_t_bug, "configure cmd failed, fifo unchanged");
  921. }
  922. /* Now lock configuration so reset will not change it
  923. */
  924. if(fdc_issue_command(cmd2, NR_ITEMS(cmd2), &stat, 1) < 0 ||
  925. stat != 0x10) {
  926. TRACE_ABORT(-EIO, ft_t_bug,
  927. "FDC lock command failed, stat = 0x%02x", stat);
  928. }
  929. fdc_fifo_locked = 1;
  930. TRACE_EXIT result;
  931. }
  932. static int fdc_fifo_enable(void)
  933. {
  934. TRACE_FUN(ft_t_any);
  935. if (fdc_fifo_locked) {
  936. TRACE_ABORT(0, ft_t_warn, "Fifo not enabled because locked");
  937. }
  938. TRACE_CATCH(fdc_fifo_threshold(ft_fdc_threshold /* bytes */,
  939. &fdc_fifo_state,
  940. &fdc_lock_state,
  941. &fdc_fifo_thr),);
  942. TRACE_CATCH(fdc_fifo_threshold(ft_fdc_threshold /* bytes */,
  943. NULL, NULL, NULL),);
  944. TRACE_EXIT 0;
  945. }
  946. /* Determine fd controller type
  947. */
  948. static __u8 fdc_save_state[2];
  949. static int fdc_probe(void)
  950. {
  951. __u8 cmd[1];
  952. __u8 stat[16]; /* must be able to hold dumpregs & save results */
  953. int i;
  954. TRACE_FUN(ft_t_any);
  955. /* Try to find out what kind of fd controller we have to deal with
  956. * Scheme borrowed from floppy driver:
  957. * first try if FDC_DUMPREGS command works
  958. * (this indicates that we have a 82072 or better)
  959. * then try the FDC_VERSION command (82072 doesn't support this)
  960. * then try the FDC_UNLOCK command (some older 82077's don't support this)
  961. * then try the FDC_PARTID command (82078's support this)
  962. */
  963. cmd[0] = FDC_DUMPREGS;
  964. if (fdc_issue_command(cmd, 1, stat, 1) != 0) {
  965. TRACE_ABORT(no_fdc, ft_t_bug, "No FDC found");
  966. }
  967. if (stat[0] == 0x80) {
  968. /* invalid command: must be pre 82072 */
  969. TRACE_ABORT(i8272,
  970. ft_t_warn, "Type 8272A/765A compatible FDC found");
  971. }
  972. fdc_result(&stat[1], 9);
  973. fdc_save_state[0] = stat[7];
  974. fdc_save_state[1] = stat[8];
  975. cmd[0] = FDC_VERSION;
  976. if (fdc_issue_command(cmd, 1, stat, 1) < 0 || stat[0] == 0x80) {
  977. TRACE_ABORT(i8272, ft_t_warn, "Type 82072 FDC found");
  978. }
  979. if (*stat != 0x90) {
  980. TRACE_ABORT(i8272, ft_t_warn, "Unknown FDC found");
  981. }
  982. cmd[0] = FDC_UNLOCK;
  983. if(fdc_issue_command(cmd, 1, stat, 1) < 0 || stat[0] != 0x00) {
  984. TRACE_ABORT(i8272, ft_t_warn,
  985. "Type pre-1991 82077 FDC found, "
  986. "treating it like a 82072");
  987. }
  988. if (fdc_save_state[0] & 0x80) { /* was locked */
  989. cmd[0] = FDC_LOCK; /* restore lock */
  990. (void)fdc_issue_command(cmd, 1, stat, 1);
  991. TRACE(ft_t_warn, "FDC is already locked");
  992. }
  993. /* Test for a i82078 FDC */
  994. cmd[0] = FDC_PARTID;
  995. if (fdc_issue_command(cmd, 1, stat, 1) < 0 || stat[0] == 0x80) {
  996. /* invalid command: not a i82078xx type FDC */
  997. for (i = 0; i < 4; ++i) {
  998. outb_p(i, fdc.tdr);
  999. if ((inb_p(fdc.tdr) & 0x03) != i) {
  1000. TRACE_ABORT(i82077,
  1001. ft_t_warn, "Type 82077 FDC found");
  1002. }
  1003. }
  1004. TRACE_ABORT(i82077AA, ft_t_warn, "Type 82077AA FDC found");
  1005. }
  1006. /* FDC_PARTID cmd succeeded */
  1007. switch (stat[0] >> 5) {
  1008. case 0x0:
  1009. /* i82078SL or i82078-1. The SL part cannot run at
  1010. * 2Mbps (the SL and -1 dies are identical; they are
  1011. * speed graded after production, according to Intel).
  1012. * Some SL's can be detected by doing a SAVE cmd and
  1013. * look at bit 7 of the first byte (the SEL3V# bit).
  1014. * If it is 0, the part runs off 3Volts, and hence it
  1015. * is a SL.
  1016. */
  1017. cmd[0] = FDC_SAVE;
  1018. if(fdc_issue_command(cmd, 1, stat, 16) < 0) {
  1019. TRACE(ft_t_err, "FDC_SAVE failed. Dunno why");
  1020. /* guess we better claim the fdc to be a i82078 */
  1021. TRACE_ABORT(i82078,
  1022. ft_t_warn,
  1023. "Type i82078 FDC (i suppose) found");
  1024. }
  1025. if ((stat[0] & FDC_SEL3V_BIT)) {
  1026. /* fdc running off 5Volts; Pray that it's a i82078-1
  1027. */
  1028. TRACE_ABORT(i82078_1, ft_t_warn,
  1029. "Type i82078-1 or 5Volt i82078SL FDC found");
  1030. }
  1031. TRACE_ABORT(i82078, ft_t_warn,
  1032. "Type 3Volt i82078SL FDC (1Mbps) found");
  1033. case 0x1:
  1034. case 0x2: /* S82078B */
  1035. /* The '78B isn't '78 compatible. Detect it as a '77AA */
  1036. TRACE_ABORT(i82077AA, ft_t_warn, "Type i82077AA FDC found");
  1037. case 0x3: /* NSC PC8744 core; used in several super-IO chips */
  1038. TRACE_ABORT(i82077AA,
  1039. ft_t_warn, "Type 82077AA compatible FDC found");
  1040. default:
  1041. TRACE(ft_t_warn, "A previously undetected FDC found");
  1042. TRACE_ABORT(i82077AA, ft_t_warn,
  1043. "Treating it as a 82077AA. Please report partid= %d",
  1044. stat[0]);
  1045. } /* switch(stat[ 0] >> 5) */
  1046. TRACE_EXIT no_fdc;
  1047. }
  1048. static int fdc_request_regions(void)
  1049. {
  1050. TRACE_FUN(ft_t_flow);
  1051. if (ft_mach2 || ft_probe_fc10) {
  1052. if (!request_region(fdc.sra, 8, "fdc (ft)")) {
  1053. #ifndef BROKEN_FLOPPY_DRIVER
  1054. TRACE_EXIT -EBUSY;
  1055. #else
  1056. TRACE(ft_t_warn,
  1057. "address 0x%03x occupied (by floppy driver?), using it anyway", fdc.sra);
  1058. #endif
  1059. }
  1060. } else {
  1061. if (!request_region(fdc.sra, 6, "fdc (ft)")) {
  1062. #ifndef BROKEN_FLOPPY_DRIVER
  1063. TRACE_EXIT -EBUSY;
  1064. #else
  1065. TRACE(ft_t_warn,
  1066. "address 0x%03x occupied (by floppy driver?), using it anyway", fdc.sra);
  1067. #endif
  1068. }
  1069. if (!request_region(fdc.sra + 7, 1, "fdc (ft)")) {
  1070. #ifndef BROKEN_FLOPPY_DRIVER
  1071. release_region(fdc.sra, 6);
  1072. TRACE_EXIT -EBUSY;
  1073. #else
  1074. TRACE(ft_t_warn,
  1075. "address 0x%03x occupied (by floppy driver?), using it anyway", fdc.sra + 7);
  1076. #endif
  1077. }
  1078. }
  1079. TRACE_EXIT 0;
  1080. }
  1081. void fdc_release_regions(void)
  1082. {
  1083. TRACE_FUN(ft_t_flow);
  1084. if (fdc.sra != 0) {
  1085. if (fdc.dor2 != 0) {
  1086. release_region(fdc.sra, 8);
  1087. } else {
  1088. release_region(fdc.sra, 6);
  1089. release_region(fdc.dir, 1);
  1090. }
  1091. }
  1092. TRACE_EXIT;
  1093. }
  1094. static int fdc_config_regs(unsigned int fdc_base,
  1095. unsigned int fdc_irq,
  1096. unsigned int fdc_dma)
  1097. {
  1098. TRACE_FUN(ft_t_flow);
  1099. fdc.irq = fdc_irq;
  1100. fdc.dma = fdc_dma;
  1101. fdc.sra = fdc_base;
  1102. fdc.srb = fdc_base + 1;
  1103. fdc.dor = fdc_base + 2;
  1104. fdc.tdr = fdc_base + 3;
  1105. fdc.msr = fdc.dsr = fdc_base + 4;
  1106. fdc.fifo = fdc_base + 5;
  1107. fdc.dir = fdc.ccr = fdc_base + 7;
  1108. fdc.dor2 = (ft_mach2 || ft_probe_fc10) ? fdc_base + 6 : 0;
  1109. TRACE_CATCH(fdc_request_regions(), fdc.sra = 0);
  1110. TRACE_EXIT 0;
  1111. }
  1112. static int fdc_config(void)
  1113. {
  1114. static int already_done;
  1115. TRACE_FUN(ft_t_any);
  1116. if (already_done) {
  1117. TRACE_CATCH(fdc_request_regions(),);
  1118. *(fdc.hook) = fdc_isr; /* hook our handler in */
  1119. TRACE_EXIT 0;
  1120. }
  1121. if (ft_probe_fc10) {
  1122. int fc_type;
  1123. TRACE_CATCH(fdc_config_regs(ft_fdc_base,
  1124. ft_fdc_irq, ft_fdc_dma),);
  1125. fc_type = fc10_enable();
  1126. if (fc_type != 0) {
  1127. TRACE(ft_t_warn, "FC-%c0 controller found", '0' + fc_type);
  1128. fdc.type = fc10;
  1129. fdc.hook = &do_ftape;
  1130. *(fdc.hook) = fdc_isr; /* hook our handler in */
  1131. already_done = 1;
  1132. TRACE_EXIT 0;
  1133. } else {
  1134. TRACE(ft_t_warn, "FC-10/20 controller not found");
  1135. fdc_release_regions();
  1136. fdc.type = no_fdc;
  1137. ft_probe_fc10 = 0;
  1138. ft_fdc_base = 0x3f0;
  1139. ft_fdc_irq = 6;
  1140. ft_fdc_dma = 2;
  1141. }
  1142. }
  1143. TRACE(ft_t_warn, "fdc base: 0x%x, irq: %d, dma: %d",
  1144. ft_fdc_base, ft_fdc_irq, ft_fdc_dma);
  1145. TRACE_CATCH(fdc_config_regs(ft_fdc_base, ft_fdc_irq, ft_fdc_dma),);
  1146. fdc.hook = &do_ftape;
  1147. *(fdc.hook) = fdc_isr; /* hook our handler in */
  1148. already_done = 1;
  1149. TRACE_EXIT 0;
  1150. }
  1151. static irqreturn_t ftape_interrupt(int irq, void *dev_id)
  1152. {
  1153. void (*handler) (void) = *fdc.hook;
  1154. int handled = 0;
  1155. TRACE_FUN(ft_t_any);
  1156. *fdc.hook = NULL;
  1157. if (handler) {
  1158. handled = 1;
  1159. handler();
  1160. } else {
  1161. TRACE(ft_t_bug, "Unexpected ftape interrupt");
  1162. }
  1163. TRACE_EXIT IRQ_RETVAL(handled);
  1164. }
  1165. static int fdc_grab_irq_and_dma(void)
  1166. {
  1167. TRACE_FUN(ft_t_any);
  1168. if (fdc.hook == &do_ftape) {
  1169. /* Get fast interrupt handler.
  1170. */
  1171. if (request_irq(fdc.irq, ftape_interrupt,
  1172. IRQF_DISABLED, "ft", ftape_id)) {
  1173. TRACE_ABORT(-EIO, ft_t_bug,
  1174. "Unable to grab IRQ%d for ftape driver",
  1175. fdc.irq);
  1176. }
  1177. if (request_dma(fdc.dma, ftape_id)) {
  1178. free_irq(fdc.irq, ftape_id);
  1179. TRACE_ABORT(-EIO, ft_t_bug,
  1180. "Unable to grab DMA%d for ftape driver",
  1181. fdc.dma);
  1182. }
  1183. }
  1184. if (ft_fdc_base != 0x3f0 && (ft_fdc_dma == 2 || ft_fdc_irq == 6)) {
  1185. /* Using same dma channel or irq as standard fdc, need
  1186. * to disable the dma-gate on the std fdc. This
  1187. * couldn't be done in the floppy driver as some
  1188. * laptops are using the dma-gate to enter a low power
  1189. * or even suspended state :-(
  1190. */
  1191. outb_p(FDC_RESET_NOT, 0x3f2);
  1192. TRACE(ft_t_noise, "DMA-gate on standard fdc disabled");
  1193. }
  1194. TRACE_EXIT 0;
  1195. }
  1196. int fdc_release_irq_and_dma(void)
  1197. {
  1198. TRACE_FUN(ft_t_any);
  1199. if (fdc.hook == &do_ftape) {
  1200. disable_dma(fdc.dma); /* just in case... */
  1201. free_dma(fdc.dma);
  1202. free_irq(fdc.irq, ftape_id);
  1203. }
  1204. if (ft_fdc_base != 0x3f0 && (ft_fdc_dma == 2 || ft_fdc_irq == 6)) {
  1205. /* Using same dma channel as standard fdc, need to
  1206. * disable the dma-gate on the std fdc. This couldn't
  1207. * be done in the floppy driver as some laptops are
  1208. * using the dma-gate to enter a low power or even
  1209. * suspended state :-(
  1210. */
  1211. outb_p(FDC_RESET_NOT | FDC_DMA_MODE, 0x3f2);
  1212. TRACE(ft_t_noise, "DMA-gate on standard fdc enabled again");
  1213. }
  1214. TRACE_EXIT 0;
  1215. }
  1216. int fdc_init(void)
  1217. {
  1218. TRACE_FUN(ft_t_any);
  1219. /* find a FDC to use */
  1220. TRACE_CATCH(fdc_config(),);
  1221. TRACE_CATCH(fdc_grab_irq_and_dma(), fdc_release_regions());
  1222. ftape_motor = 0;
  1223. fdc_catch_stray_interrupts(0); /* clear number of awainted
  1224. * stray interrupte
  1225. */
  1226. fdc_catch_stray_interrupts(1); /* one always comes (?) */
  1227. TRACE(ft_t_flow, "resetting fdc");
  1228. fdc_set_seek_rate(2); /* use nominal QIC step rate */
  1229. fdc_reset(); /* init fdc & clear track counters */
  1230. if (fdc.type == no_fdc) { /* no FC-10 or FC-20 found */
  1231. fdc.type = fdc_probe();
  1232. fdc_reset(); /* update with new knowledge */
  1233. }
  1234. if (fdc.type == no_fdc) {
  1235. fdc_release_irq_and_dma();
  1236. fdc_release_regions();
  1237. TRACE_EXIT -ENXIO;
  1238. }
  1239. if (fdc.type >= i82077) {
  1240. if (fdc_fifo_enable() < 0) {
  1241. TRACE(ft_t_warn, "couldn't enable fdc fifo !");
  1242. } else {
  1243. TRACE(ft_t_flow, "fdc fifo enabled and locked");
  1244. }
  1245. }
  1246. TRACE_EXIT 0;
  1247. }