i810_drv.h 7.7 KB

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  1. /* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
  2. * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
  3. *
  4. * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
  5. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  6. * All rights reserved.
  7. *
  8. * Permission is hereby granted, free of charge, to any person obtaining a
  9. * copy of this software and associated documentation files (the "Software"),
  10. * to deal in the Software without restriction, including without limitation
  11. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  12. * and/or sell copies of the Software, and to permit persons to whom the
  13. * Software is furnished to do so, subject to the following conditions:
  14. *
  15. * The above copyright notice and this permission notice (including the next
  16. * paragraph) shall be included in all copies or substantial portions of the
  17. * Software.
  18. *
  19. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22. * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  23. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  24. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  25. * DEALINGS IN THE SOFTWARE.
  26. *
  27. * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
  28. * Jeff Hartmann <jhartmann@valinux.com>
  29. *
  30. */
  31. #ifndef _I810_DRV_H_
  32. #define _I810_DRV_H_
  33. /* General customization:
  34. */
  35. #define DRIVER_AUTHOR "VA Linux Systems Inc."
  36. #define DRIVER_NAME "i810"
  37. #define DRIVER_DESC "Intel i810"
  38. #define DRIVER_DATE "20030605"
  39. /* Interface history
  40. *
  41. * 1.1 - XFree86 4.1
  42. * 1.2 - XvMC interfaces
  43. * - XFree86 4.2
  44. * 1.2.1 - Disable copying code (leave stub ioctls for backwards compatibility)
  45. * - Remove requirement for interrupt (leave stubs again)
  46. * 1.3 - Add page flipping.
  47. * 1.4 - fix DRM interface
  48. */
  49. #define DRIVER_MAJOR 1
  50. #define DRIVER_MINOR 4
  51. #define DRIVER_PATCHLEVEL 0
  52. typedef struct drm_i810_buf_priv {
  53. u32 *in_use;
  54. int my_use_idx;
  55. int currently_mapped;
  56. void *virtual;
  57. void *kernel_virtual;
  58. } drm_i810_buf_priv_t;
  59. typedef struct _drm_i810_ring_buffer {
  60. int tail_mask;
  61. unsigned long Start;
  62. unsigned long End;
  63. unsigned long Size;
  64. u8 *virtual_start;
  65. int head;
  66. int tail;
  67. int space;
  68. } drm_i810_ring_buffer_t;
  69. typedef struct drm_i810_private {
  70. drm_map_t *sarea_map;
  71. drm_map_t *mmio_map;
  72. drm_i810_sarea_t *sarea_priv;
  73. drm_i810_ring_buffer_t ring;
  74. void *hw_status_page;
  75. unsigned long counter;
  76. dma_addr_t dma_status_page;
  77. drm_buf_t *mmap_buffer;
  78. u32 front_di1, back_di1, zi1;
  79. int back_offset;
  80. int depth_offset;
  81. int overlay_offset;
  82. int overlay_physical;
  83. int w, h;
  84. int pitch;
  85. int back_pitch;
  86. int depth_pitch;
  87. int do_boxes;
  88. int dma_used;
  89. int current_page;
  90. int page_flipping;
  91. wait_queue_head_t irq_queue;
  92. atomic_t irq_received;
  93. atomic_t irq_emitted;
  94. int front_offset;
  95. } drm_i810_private_t;
  96. /* i810_dma.c */
  97. extern int i810_driver_dma_quiescent(drm_device_t * dev);
  98. extern void i810_driver_reclaim_buffers_locked(drm_device_t * dev,
  99. struct file *filp);
  100. extern int i810_driver_load(struct drm_device *, unsigned long flags);
  101. extern void i810_driver_lastclose(drm_device_t * dev);
  102. extern void i810_driver_preclose(drm_device_t * dev, DRMFILE filp);
  103. extern void i810_driver_reclaim_buffers_locked(drm_device_t * dev,
  104. struct file *filp);
  105. extern int i810_driver_device_is_agp(drm_device_t * dev);
  106. extern drm_ioctl_desc_t i810_ioctls[];
  107. extern int i810_max_ioctl;
  108. #define I810_BASE(reg) ((unsigned long) \
  109. dev_priv->mmio_map->handle)
  110. #define I810_ADDR(reg) (I810_BASE(reg) + reg)
  111. #define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg)
  112. #define I810_READ(reg) I810_DEREF(reg)
  113. #define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0)
  114. #define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg)
  115. #define I810_READ16(reg) I810_DEREF16(reg)
  116. #define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0)
  117. #define I810_VERBOSE 0
  118. #define RING_LOCALS unsigned int outring, ringmask; \
  119. volatile char *virt;
  120. #define BEGIN_LP_RING(n) do { \
  121. if (I810_VERBOSE) \
  122. DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", n, __FUNCTION__); \
  123. if (dev_priv->ring.space < n*4) \
  124. i810_wait_ring(dev, n*4); \
  125. dev_priv->ring.space -= n*4; \
  126. outring = dev_priv->ring.tail; \
  127. ringmask = dev_priv->ring.tail_mask; \
  128. virt = dev_priv->ring.virtual_start; \
  129. } while (0)
  130. #define ADVANCE_LP_RING() do { \
  131. if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \
  132. dev_priv->ring.tail = outring; \
  133. I810_WRITE(LP_RING + RING_TAIL, outring); \
  134. } while(0)
  135. #define OUT_RING(n) do { \
  136. if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
  137. *(volatile unsigned int *)(virt + outring) = n; \
  138. outring += 4; \
  139. outring &= ringmask; \
  140. } while (0)
  141. #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
  142. #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
  143. #define CMD_REPORT_HEAD (7<<23)
  144. #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
  145. #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
  146. #define INST_PARSER_CLIENT 0x00000000
  147. #define INST_OP_FLUSH 0x02000000
  148. #define INST_FLUSH_MAP_CACHE 0x00000001
  149. #define BB1_START_ADDR_MASK (~0x7)
  150. #define BB1_PROTECTED (1<<0)
  151. #define BB1_UNPROTECTED (0<<0)
  152. #define BB2_END_ADDR_MASK (~0x7)
  153. #define I810REG_HWSTAM 0x02098
  154. #define I810REG_INT_IDENTITY_R 0x020a4
  155. #define I810REG_INT_MASK_R 0x020a8
  156. #define I810REG_INT_ENABLE_R 0x020a0
  157. #define LP_RING 0x2030
  158. #define HP_RING 0x2040
  159. #define RING_TAIL 0x00
  160. #define TAIL_ADDR 0x000FFFF8
  161. #define RING_HEAD 0x04
  162. #define HEAD_WRAP_COUNT 0xFFE00000
  163. #define HEAD_WRAP_ONE 0x00200000
  164. #define HEAD_ADDR 0x001FFFFC
  165. #define RING_START 0x08
  166. #define START_ADDR 0x00FFFFF8
  167. #define RING_LEN 0x0C
  168. #define RING_NR_PAGES 0x000FF000
  169. #define RING_REPORT_MASK 0x00000006
  170. #define RING_REPORT_64K 0x00000002
  171. #define RING_REPORT_128K 0x00000004
  172. #define RING_NO_REPORT 0x00000000
  173. #define RING_VALID_MASK 0x00000001
  174. #define RING_VALID 0x00000001
  175. #define RING_INVALID 0x00000000
  176. #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
  177. #define SC_UPDATE_SCISSOR (0x1<<1)
  178. #define SC_ENABLE_MASK (0x1<<0)
  179. #define SC_ENABLE (0x1<<0)
  180. #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
  181. #define SCI_YMIN_MASK (0xffff<<16)
  182. #define SCI_XMIN_MASK (0xffff<<0)
  183. #define SCI_YMAX_MASK (0xffff<<16)
  184. #define SCI_XMAX_MASK (0xffff<<0)
  185. #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
  186. #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
  187. #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x2)
  188. #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
  189. #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
  190. #define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24))
  191. #define CMD_OP_Z_BUFFER_INFO ((0x0<<29)|(0x16<<23))
  192. #define CMD_OP_DESTBUFFER_INFO ((0x0<<29)|(0x15<<23))
  193. #define CMD_OP_FRONTBUFFER_INFO ((0x0<<29)|(0x14<<23))
  194. #define CMD_OP_WAIT_FOR_EVENT ((0x0<<29)|(0x03<<23))
  195. #define BR00_BITBLT_CLIENT 0x40000000
  196. #define BR00_OP_COLOR_BLT 0x10000000
  197. #define BR00_OP_SRC_COPY_BLT 0x10C00000
  198. #define BR13_SOLID_PATTERN 0x80000000
  199. #define WAIT_FOR_PLANE_A_SCANLINES (1<<1)
  200. #define WAIT_FOR_PLANE_A_FLIP (1<<2)
  201. #define WAIT_FOR_VBLANK (1<<3)
  202. #endif