pata_sil680.c 10 KB

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  1. /*
  2. * pata_sil680.c - SIL680 PATA for new ATA layer
  3. * (C) 2005 Red Hat Inc
  4. * Alan Cox <alan@redhat.com>
  5. *
  6. * based upon
  7. *
  8. * linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
  9. *
  10. * Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
  11. * Copyright (C) 2003 Red Hat <alan@redhat.com>
  12. *
  13. * May be copied or modified under the terms of the GNU General Public License
  14. *
  15. * Documentation publically available.
  16. *
  17. * If you have strange problems with nVidia chipset systems please
  18. * see the SI support documentation and update your system BIOS
  19. * if neccessary
  20. *
  21. * TODO
  22. * If we know all our devices are LBA28 (or LBA28 sized) we could use
  23. * the command fifo mode.
  24. */
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/pci.h>
  28. #include <linux/init.h>
  29. #include <linux/blkdev.h>
  30. #include <linux/delay.h>
  31. #include <scsi/scsi_host.h>
  32. #include <linux/libata.h>
  33. #define DRV_NAME "pata_sil680"
  34. #define DRV_VERSION "0.3.2"
  35. /**
  36. * sil680_selreg - return register base
  37. * @hwif: interface
  38. * @r: config offset
  39. *
  40. * Turn a config register offset into the right address in either
  41. * PCI space or MMIO space to access the control register in question
  42. * Thankfully this is a configuration operation so isnt performance
  43. * criticial.
  44. */
  45. static unsigned long sil680_selreg(struct ata_port *ap, int r)
  46. {
  47. unsigned long base = 0xA0 + r;
  48. base += (ap->port_no << 4);
  49. return base;
  50. }
  51. /**
  52. * sil680_seldev - return register base
  53. * @hwif: interface
  54. * @r: config offset
  55. *
  56. * Turn a config register offset into the right address in either
  57. * PCI space or MMIO space to access the control register in question
  58. * including accounting for the unit shift.
  59. */
  60. static unsigned long sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
  61. {
  62. unsigned long base = 0xA0 + r;
  63. base += (ap->port_no << 4);
  64. base |= adev->devno ? 2 : 0;
  65. return base;
  66. }
  67. /**
  68. * sil680_cable_detect - cable detection
  69. * @ap: ATA port
  70. *
  71. * Perform cable detection. The SIL680 stores this in PCI config
  72. * space for us.
  73. */
  74. static int sil680_cable_detect(struct ata_port *ap) {
  75. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  76. unsigned long addr = sil680_selreg(ap, 0);
  77. u8 ata66;
  78. pci_read_config_byte(pdev, addr, &ata66);
  79. if (ata66 & 1)
  80. return ATA_CBL_PATA80;
  81. else
  82. return ATA_CBL_PATA40;
  83. }
  84. static int sil680_pre_reset(struct ata_port *ap)
  85. {
  86. ap->cbl = sil680_cable_detect(ap);
  87. return ata_std_prereset(ap);
  88. }
  89. /**
  90. * sil680_bus_reset - reset the SIL680 bus
  91. * @ap: ATA port to reset
  92. *
  93. * Perform the SIL680 housekeeping when doing an ATA bus reset
  94. */
  95. static int sil680_bus_reset(struct ata_port *ap,unsigned int *classes)
  96. {
  97. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  98. unsigned long addr = sil680_selreg(ap, 0);
  99. u8 reset;
  100. pci_read_config_byte(pdev, addr, &reset);
  101. pci_write_config_byte(pdev, addr, reset | 0x03);
  102. udelay(25);
  103. pci_write_config_byte(pdev, addr, reset);
  104. return ata_std_softreset(ap, classes);
  105. }
  106. static void sil680_error_handler(struct ata_port *ap)
  107. {
  108. ata_bmdma_drive_eh(ap, sil680_pre_reset, sil680_bus_reset, NULL, ata_std_postreset);
  109. }
  110. /**
  111. * sil680_set_piomode - set initial PIO mode data
  112. * @ap: ATA interface
  113. * @adev: ATA device
  114. *
  115. * Program the SIL680 registers for PIO mode. Note that the task speed
  116. * registers are shared between the devices so we must pick the lowest
  117. * mode for command work.
  118. */
  119. static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
  120. {
  121. static u16 speed_p[5] = { 0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1 };
  122. static u16 speed_t[5] = { 0x328A, 0x1281, 0x1281, 0x10C3, 0x10C1 };
  123. unsigned long tfaddr = sil680_selreg(ap, 0x02);
  124. unsigned long addr = sil680_seldev(ap, adev, 0x04);
  125. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  126. int pio = adev->pio_mode - XFER_PIO_0;
  127. int lowest_pio = pio;
  128. u16 reg;
  129. struct ata_device *pair = ata_dev_pair(adev);
  130. if (pair != NULL && adev->pio_mode > pair->pio_mode)
  131. lowest_pio = pair->pio_mode - XFER_PIO_0;
  132. pci_write_config_word(pdev, addr, speed_p[pio]);
  133. pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
  134. pci_read_config_word(pdev, tfaddr-2, &reg);
  135. reg &= ~0x0200; /* Clear IORDY */
  136. if (ata_pio_need_iordy(adev))
  137. reg |= 0x0200; /* Enable IORDY */
  138. pci_write_config_word(pdev, tfaddr-2, reg);
  139. }
  140. /**
  141. * sil680_set_dmamode - set initial DMA mode data
  142. * @ap: ATA interface
  143. * @adev: ATA device
  144. *
  145. * Program the MWDMA/UDMA modes for the sil680 k
  146. * chipset. The MWDMA mode values are pulled from a lookup table
  147. * while the chipset uses mode number for UDMA.
  148. */
  149. static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
  150. {
  151. static u8 ultra_table[2][7] = {
  152. { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
  153. { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
  154. };
  155. static u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
  156. struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  157. unsigned long ma = sil680_seldev(ap, adev, 0x08);
  158. unsigned long ua = sil680_seldev(ap, adev, 0x0C);
  159. unsigned long addr_mask = 0x80 + 4 * ap->port_no;
  160. int port_shift = adev->devno * 4;
  161. u8 scsc, mode;
  162. u16 multi, ultra;
  163. pci_read_config_byte(pdev, 0x8A, &scsc);
  164. pci_read_config_byte(pdev, addr_mask, &mode);
  165. pci_read_config_word(pdev, ma, &multi);
  166. pci_read_config_word(pdev, ua, &ultra);
  167. /* Mask timing bits */
  168. ultra &= ~0x3F;
  169. mode &= ~(0x03 << port_shift);
  170. /* Extract scsc */
  171. scsc = (scsc & 0x30) ? 1: 0;
  172. if (adev->dma_mode >= XFER_UDMA_0) {
  173. multi = 0x10C1;
  174. ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
  175. mode |= (0x03 << port_shift);
  176. } else {
  177. multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
  178. mode |= (0x02 << port_shift);
  179. }
  180. pci_write_config_byte(pdev, addr_mask, mode);
  181. pci_write_config_word(pdev, ma, multi);
  182. pci_write_config_word(pdev, ua, ultra);
  183. }
  184. static struct scsi_host_template sil680_sht = {
  185. .module = THIS_MODULE,
  186. .name = DRV_NAME,
  187. .ioctl = ata_scsi_ioctl,
  188. .queuecommand = ata_scsi_queuecmd,
  189. .can_queue = ATA_DEF_QUEUE,
  190. .this_id = ATA_SHT_THIS_ID,
  191. .sg_tablesize = LIBATA_MAX_PRD,
  192. .max_sectors = ATA_MAX_SECTORS,
  193. .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
  194. .emulated = ATA_SHT_EMULATED,
  195. .use_clustering = ATA_SHT_USE_CLUSTERING,
  196. .proc_name = DRV_NAME,
  197. .dma_boundary = ATA_DMA_BOUNDARY,
  198. .slave_configure = ata_scsi_slave_config,
  199. .bios_param = ata_std_bios_param,
  200. };
  201. static struct ata_port_operations sil680_port_ops = {
  202. .port_disable = ata_port_disable,
  203. .set_piomode = sil680_set_piomode,
  204. .set_dmamode = sil680_set_dmamode,
  205. .mode_filter = ata_pci_default_filter,
  206. .tf_load = ata_tf_load,
  207. .tf_read = ata_tf_read,
  208. .check_status = ata_check_status,
  209. .exec_command = ata_exec_command,
  210. .dev_select = ata_std_dev_select,
  211. .freeze = ata_bmdma_freeze,
  212. .thaw = ata_bmdma_thaw,
  213. .error_handler = sil680_error_handler,
  214. .post_internal_cmd = ata_bmdma_post_internal_cmd,
  215. .bmdma_setup = ata_bmdma_setup,
  216. .bmdma_start = ata_bmdma_start,
  217. .bmdma_stop = ata_bmdma_stop,
  218. .bmdma_status = ata_bmdma_status,
  219. .qc_prep = ata_qc_prep,
  220. .qc_issue = ata_qc_issue_prot,
  221. .data_xfer = ata_pio_data_xfer,
  222. .irq_handler = ata_interrupt,
  223. .irq_clear = ata_bmdma_irq_clear,
  224. .port_start = ata_port_start,
  225. .port_stop = ata_port_stop,
  226. .host_stop = ata_host_stop
  227. };
  228. static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
  229. {
  230. static struct ata_port_info info = {
  231. .sht = &sil680_sht,
  232. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  233. .pio_mask = 0x1f,
  234. .mwdma_mask = 0x07,
  235. .udma_mask = 0x7f,
  236. .port_ops = &sil680_port_ops
  237. };
  238. static struct ata_port_info info_slow = {
  239. .sht = &sil680_sht,
  240. .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
  241. .pio_mask = 0x1f,
  242. .mwdma_mask = 0x07,
  243. .udma_mask = 0x3f,
  244. .port_ops = &sil680_port_ops
  245. };
  246. static struct ata_port_info *port_info[2] = {&info, &info};
  247. static int printed_version;
  248. u32 class_rev = 0;
  249. u8 tmpbyte = 0;
  250. if (!printed_version++)
  251. dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
  252. pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class_rev);
  253. class_rev &= 0xff;
  254. /* FIXME: double check */
  255. pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
  256. pci_write_config_byte(pdev, 0x80, 0x00);
  257. pci_write_config_byte(pdev, 0x84, 0x00);
  258. pci_read_config_byte(pdev, 0x8A, &tmpbyte);
  259. printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
  260. tmpbyte & 1, tmpbyte & 0x30);
  261. switch(tmpbyte & 0x30) {
  262. case 0x00:
  263. /* 133 clock attempt to force it on */
  264. pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
  265. break;
  266. case 0x30:
  267. /* if clocking is disabled */
  268. /* 133 clock attempt to force it on */
  269. pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
  270. break;
  271. case 0x10:
  272. /* 133 already */
  273. break;
  274. case 0x20:
  275. /* BIOS set PCI x2 clocking */
  276. break;
  277. }
  278. pci_read_config_byte(pdev, 0x8A, &tmpbyte);
  279. printk(KERN_INFO "sil680: BA5_EN = %d clock = %02X\n",
  280. tmpbyte & 1, tmpbyte & 0x30);
  281. if ((tmpbyte & 0x30) == 0)
  282. port_info[0] = port_info[1] = &info_slow;
  283. pci_write_config_byte(pdev, 0xA1, 0x72);
  284. pci_write_config_word(pdev, 0xA2, 0x328A);
  285. pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
  286. pci_write_config_dword(pdev, 0xA8, 0x43924392);
  287. pci_write_config_dword(pdev, 0xAC, 0x40094009);
  288. pci_write_config_byte(pdev, 0xB1, 0x72);
  289. pci_write_config_word(pdev, 0xB2, 0x328A);
  290. pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
  291. pci_write_config_dword(pdev, 0xB8, 0x43924392);
  292. pci_write_config_dword(pdev, 0xBC, 0x40094009);
  293. switch(tmpbyte & 0x30) {
  294. case 0x00: printk(KERN_INFO "sil680: 100MHz clock.\n");break;
  295. case 0x10: printk(KERN_INFO "sil680: 133MHz clock.\n");break;
  296. case 0x20: printk(KERN_INFO "sil680: Using PCI clock.\n");break;
  297. /* This last case is _NOT_ ok */
  298. case 0x30: printk(KERN_ERR "sil680: Clock disabled ?\n");
  299. return -EIO;
  300. }
  301. return ata_pci_init_one(pdev, port_info, 2);
  302. }
  303. static const struct pci_device_id sil680[] = {
  304. { PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
  305. { },
  306. };
  307. static struct pci_driver sil680_pci_driver = {
  308. .name = DRV_NAME,
  309. .id_table = sil680,
  310. .probe = sil680_init_one,
  311. .remove = ata_pci_remove_one
  312. };
  313. static int __init sil680_init(void)
  314. {
  315. return pci_register_driver(&sil680_pci_driver);
  316. }
  317. static void __exit sil680_exit(void)
  318. {
  319. pci_unregister_driver(&sil680_pci_driver);
  320. }
  321. MODULE_AUTHOR("Alan Cox");
  322. MODULE_DESCRIPTION("low-level driver for SI680 PATA");
  323. MODULE_LICENSE("GPL");
  324. MODULE_DEVICE_TABLE(pci, sil680);
  325. MODULE_VERSION(DRV_VERSION);
  326. module_init(sil680_init);
  327. module_exit(sil680_exit);