pci-sh7780.c 4.2 KB

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  1. /*
  2. * Low-Level PCI Support for the SH7780
  3. *
  4. * Dustin McIntire (dustin@sensoria.com)
  5. * Derived from arch/i386/kernel/pci-*.c which bore the message:
  6. * (c) 1999--2000 Martin Mares <mj@ucw.cz>
  7. *
  8. * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
  9. * With cleanup by Paul van Gool <pvangool@mimotech.com>
  10. *
  11. * May be copied or modified under the terms of the GNU General Public
  12. * License. See linux/COPYING for more information.
  13. *
  14. */
  15. #undef DEBUG
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/pci.h>
  20. #include <linux/errno.h>
  21. #include <linux/delay.h>
  22. #include "pci-sh4.h"
  23. /*
  24. * Initialization. Try all known PCI access methods. Note that we support
  25. * using both PCI BIOS and direct access: in such cases, we use I/O ports
  26. * to access config space.
  27. *
  28. * Note that the platform specific initialization (BSC registers, and memory
  29. * space mapping) will be called via the platform defined function
  30. * pcibios_init_platform().
  31. */
  32. static int __init sh7780_pci_init(void)
  33. {
  34. unsigned int id;
  35. int ret;
  36. pr_debug("PCI: Starting intialization.\n");
  37. outl(0x00000001, SH7780_PCI_VCR2); /* Enable PCIC */
  38. /* check for SH7780/SH7780R hardware */
  39. id = pci_read_reg(SH7780_PCIVID);
  40. if ((id != ((SH7780_DEVICE_ID << 16) | SH7780_VENDOR_ID)) &&
  41. (id != ((SH7781_DEVICE_ID << 16) | SH7780_VENDOR_ID))) {
  42. printk(KERN_ERR "PCI: This is not an SH7780 (%x)\n", id);
  43. return -ENODEV;
  44. }
  45. /* Setup the INTC */
  46. ctrl_outl(0x00200000, INTC_ICR0); /* INTC SH-4 Mode */
  47. ctrl_outl(0x00078000, INTC_INT2MSKCR); /* enable PCIINTA - PCIINTD */
  48. ctrl_outl(0x40000000, INTC_INTMSK1); /* disable IRL4-7 Interrupt */
  49. ctrl_outl(0x0000fffe, INTC_INTMSK2); /* disable IRL4-7 Interrupt */
  50. ctrl_outl(0x80000000, INTC_INTMSKCLR1); /* enable IRL0-3 Interrupt */
  51. ctrl_outl(0xfffe0000, INTC_INTMSKCLR2); /* enable IRL0-3 Interrupt */
  52. if ((ret = sh4_pci_check_direct()) != 0)
  53. return ret;
  54. return pcibios_init_platform();
  55. }
  56. core_initcall(sh7780_pci_init);
  57. int __init sh7780_pcic_init(struct sh4_pci_address_map *map)
  58. {
  59. u32 word;
  60. /*
  61. * This code is unused for some boards as it is done in the
  62. * bootloader and doing it here means the MAC addresses loaded
  63. * by the bootloader get lost.
  64. */
  65. if (!(map->flags & SH4_PCIC_NO_RESET)) {
  66. /* toggle PCI reset pin */
  67. word = SH4_PCICR_PREFIX | SH4_PCICR_PRST;
  68. pci_write_reg(word, SH4_PCICR);
  69. /* Wait for a long time... not 1 sec. but long enough */
  70. mdelay(100);
  71. word = SH4_PCICR_PREFIX;
  72. pci_write_reg(word, SH4_PCICR);
  73. }
  74. /* set the command/status bits to:
  75. * Wait Cycle Control + Parity Enable + Bus Master +
  76. * Mem space enable
  77. */
  78. pci_write_reg(0x00000046, SH7780_PCICMD);
  79. /* define this host as the host bridge */
  80. word = PCI_BASE_CLASS_BRIDGE << 24;
  81. pci_write_reg(word, SH7780_PCIRID);
  82. /* Set IO and Mem windows to local address
  83. * Make PCI and local address the same for easy 1 to 1 mapping
  84. * Window0 = map->window0.size @ non-cached area base = SDRAM
  85. * Window1 = map->window1.size @ cached area base = SDRAM
  86. */
  87. word = ((map->window0.size - 1) & 0x1ff00001) | 0x01;
  88. pci_write_reg(0x07f00001, SH4_PCILSR0);
  89. word = ((map->window1.size - 1) & 0x1ff00001) | 0x01;
  90. pci_write_reg(0x00000001, SH4_PCILSR1);
  91. /* Set the values on window 0 PCI config registers */
  92. word = P2SEGADDR(map->window0.base);
  93. pci_write_reg(0xa8000000, SH4_PCILAR0);
  94. pci_write_reg(0x08000000, SH7780_PCIMBAR0);
  95. /* Set the values on window 1 PCI config registers */
  96. word = P2SEGADDR(map->window1.base);
  97. pci_write_reg(0x00000000, SH4_PCILAR1);
  98. pci_write_reg(0x00000000, SH7780_PCIMBAR1);
  99. /* Map IO space into PCI IO window
  100. * The IO window is 64K-PCIBIOS_MIN_IO in size
  101. * IO addresses will be translated to the
  102. * PCI IO window base address
  103. */
  104. pr_debug("PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n",
  105. PCIBIOS_MIN_IO, (64 << 10),
  106. SH7780_PCI_IO_BASE + PCIBIOS_MIN_IO);
  107. /* NOTE: I'm ignoring the PCI error IRQs for now..
  108. * TODO: add support for the internal error interrupts and
  109. * DMA interrupts...
  110. */
  111. #ifdef CONFIG_SH_R7780RP
  112. pci_fixup_pcic();
  113. #endif
  114. /* SH7780 init done, set central function init complete */
  115. /* use round robin mode to stop a device starving/overruning */
  116. word = SH4_PCICR_PREFIX | SH4_PCICR_CFIN | SH4_PCICR_FTO;
  117. pci_write_reg(word, SH4_PCICR);
  118. return 1;
  119. }