mpc85xx_cds_common.h 2.3 KB

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  1. /*
  2. * MPC85xx CDS board definitions
  3. *
  4. * Maintainer: Kumar Gala <galak@kernel.crashing.org>
  5. *
  6. * Copyright 2004 Freescale Semiconductor, Inc
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. *
  13. */
  14. #ifndef __MACH_MPC85XX_CDS_H__
  15. #define __MACH_MPC85XX_CDS_H__
  16. #include <linux/serial.h>
  17. #include <asm/ppcboot.h>
  18. #include <linux/initrd.h>
  19. #include <syslib/ppc85xx_setup.h>
  20. #define BOARD_CCSRBAR ((uint)0xe0000000)
  21. #define CCSRBAR_SIZE ((uint)1024*1024)
  22. /* CADMUS info */
  23. #define CADMUS_BASE (0xf8004000)
  24. #define CADMUS_SIZE (256)
  25. #define CM_VER (0)
  26. #define CM_CSR (1)
  27. #define CM_RST (2)
  28. /* CDS NVRAM/RTC */
  29. #define CDS_RTC_ADDR (0xf8000000)
  30. #define CDS_RTC_SIZE (8 * 1024)
  31. /* PCI config */
  32. #define PCI1_CFG_ADDR_OFFSET (0x8000)
  33. #define PCI1_CFG_DATA_OFFSET (0x8004)
  34. #define PCI2_CFG_ADDR_OFFSET (0x9000)
  35. #define PCI2_CFG_DATA_OFFSET (0x9004)
  36. /* PCI interrupt controller */
  37. #define PIRQ0A MPC85xx_IRQ_EXT0
  38. #define PIRQ0B MPC85xx_IRQ_EXT1
  39. #define PIRQ0C MPC85xx_IRQ_EXT2
  40. #define PIRQ0D MPC85xx_IRQ_EXT3
  41. #define PIRQ1A MPC85xx_IRQ_EXT11
  42. /* PCI 1 memory map */
  43. #define MPC85XX_PCI1_LOWER_IO 0x00000000
  44. #define MPC85XX_PCI1_UPPER_IO 0x00ffffff
  45. #define MPC85XX_PCI1_LOWER_MEM 0x80000000
  46. #define MPC85XX_PCI1_UPPER_MEM 0x9fffffff
  47. #define MPC85XX_PCI1_IO_BASE 0xe2000000
  48. #define MPC85XX_PCI1_MEM_OFFSET 0x00000000
  49. #define MPC85XX_PCI1_IO_SIZE 0x01000000
  50. /* PCI 2 memory map */
  51. /* Note: the standard PPC fixups will cause IO space to get bumped by
  52. * hose->io_base_virt - isa_io_base => MPC85XX_PCI1_IO_SIZE */
  53. #define MPC85XX_PCI2_LOWER_IO 0x00000000
  54. #define MPC85XX_PCI2_UPPER_IO 0x00ffffff
  55. #define MPC85XX_PCI2_LOWER_MEM 0xa0000000
  56. #define MPC85XX_PCI2_UPPER_MEM 0xbfffffff
  57. #define MPC85XX_PCI2_IO_BASE 0xe3000000
  58. #define MPC85XX_PCI2_MEM_OFFSET 0x00000000
  59. #define MPC85XX_PCI2_IO_SIZE 0x01000000
  60. #define NR_8259_INTS 16
  61. #define CPM_IRQ_OFFSET NR_8259_INTS
  62. #endif /* __MACH_MPC85XX_CDS_H__ */