ibmnp405h.c 4.8 KB

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  1. /*
  2. * Author: Armin Kuster <akuster@mvista.com>
  3. *
  4. * 2000-2002 (c) MontaVista, Software, Inc. This file is licensed under
  5. * the terms of the GNU General Public License version 2. This program
  6. * is licensed "as is" without any warranty of any kind, whether express
  7. * or implied.
  8. */
  9. #include <linux/init.h>
  10. #include <asm/ocp.h>
  11. #include <platforms/4xx/ibmnp405h.h>
  12. static struct ocp_func_emac_data ibmnp405h_emac0_def = {
  13. .rgmii_idx = -1, /* No RGMII */
  14. .rgmii_mux = -1, /* No RGMII */
  15. .zmii_idx = 0, /* ZMII device index */
  16. .zmii_mux = 0, /* ZMII input of this EMAC */
  17. .mal_idx = 0, /* MAL device index */
  18. .mal_rx_chan = 0, /* MAL rx channel number */
  19. .mal_tx_chan = 0, /* MAL tx channel number */
  20. .wol_irq = 41, /* WOL interrupt number */
  21. .mdio_idx = -1, /* No shared MDIO */
  22. .tah_idx = -1, /* No TAH */
  23. };
  24. static struct ocp_func_emac_data ibmnp405h_emac1_def = {
  25. .rgmii_idx = -1, /* No RGMII */
  26. .rgmii_mux = -1, /* No RGMII */
  27. .zmii_idx = 0, /* ZMII device index */
  28. .zmii_mux = 1, /* ZMII input of this EMAC */
  29. .mal_idx = 0, /* MAL device index */
  30. .mal_rx_chan = 1, /* MAL rx channel number */
  31. .mal_tx_chan = 2, /* MAL tx channel number */
  32. .wol_irq = 41, /* WOL interrupt number */
  33. .mdio_idx = -1, /* No shared MDIO */
  34. .tah_idx = -1, /* No TAH */
  35. };
  36. static struct ocp_func_emac_data ibmnp405h_emac2_def = {
  37. .rgmii_idx = -1, /* No RGMII */
  38. .rgmii_mux = -1, /* No RGMII */
  39. .zmii_idx = 0, /* ZMII device index */
  40. .zmii_mux = 2, /* ZMII input of this EMAC */
  41. .mal_idx = 0, /* MAL device index */
  42. .mal_rx_chan = 2, /* MAL rx channel number */
  43. .mal_tx_chan = 4, /* MAL tx channel number */
  44. .wol_irq = 41, /* WOL interrupt number */
  45. .mdio_idx = -1, /* No shared MDIO */
  46. .tah_idx = -1, /* No TAH */
  47. };
  48. static struct ocp_func_emac_data ibmnp405h_emac3_def = {
  49. .rgmii_idx = -1, /* No RGMII */
  50. .rgmii_mux = -1, /* No RGMII */
  51. .zmii_idx = 0, /* ZMII device index */
  52. .zmii_mux = 3, /* ZMII input of this EMAC */
  53. .mal_idx = 0, /* MAL device index */
  54. .mal_rx_chan = 3, /* MAL rx channel number */
  55. .mal_tx_chan = 6, /* MAL tx channel number */
  56. .wol_irq = 41, /* WOL interrupt number */
  57. .mdio_idx = -1, /* No shared MDIO */
  58. .tah_idx = -1, /* No TAH */
  59. };
  60. OCP_SYSFS_EMAC_DATA()
  61. static struct ocp_func_mal_data ibmnp405h_mal0_def = {
  62. .num_tx_chans = 8, /* Number of TX channels */
  63. .num_rx_chans = 4, /* Number of RX channels */
  64. .txeob_irq = 17, /* TX End Of Buffer IRQ */
  65. .rxeob_irq = 18, /* RX End Of Buffer IRQ */
  66. .txde_irq = 46, /* TX Descriptor Error IRQ */
  67. .rxde_irq = 47, /* RX Descriptor Error IRQ */
  68. .serr_irq = 45, /* MAL System Error IRQ */
  69. .dcr_base = DCRN_MAL_BASE /* MAL0_CFG DCR number */
  70. };
  71. OCP_SYSFS_MAL_DATA()
  72. static struct ocp_func_iic_data ibmnp405h_iic0_def = {
  73. .fast_mode = 0, /* Use standad mode (100Khz) */
  74. };
  75. OCP_SYSFS_IIC_DATA()
  76. struct ocp_def core_ocp[] = {
  77. { .vendor = OCP_VENDOR_IBM,
  78. .function = OCP_FUNC_OPB,
  79. .index = 0,
  80. .paddr = 0xEF600000,
  81. .irq = OCP_IRQ_NA,
  82. .pm = OCP_CPM_NA,
  83. },
  84. { .vendor = OCP_VENDOR_IBM,
  85. .function = OCP_FUNC_16550,
  86. .index = 0,
  87. .paddr = UART0_IO_BASE,
  88. .irq = UART0_INT,
  89. .pm = IBM_CPM_UART0
  90. },
  91. { .vendor = OCP_VENDOR_IBM,
  92. .function = OCP_FUNC_16550,
  93. .index = 1,
  94. .paddr = UART1_IO_BASE,
  95. .irq = UART1_INT,
  96. .pm = IBM_CPM_UART1
  97. },
  98. { .vendor = OCP_VENDOR_IBM,
  99. .function = OCP_FUNC_IIC,
  100. .paddr = 0xEF600500,
  101. .irq = 2,
  102. .pm = IBM_CPM_IIC0,
  103. .additions = &ibmnp405h_iic0_def,
  104. .show = &ocp_show_iic_data
  105. },
  106. { .vendor = OCP_VENDOR_IBM,
  107. .function = OCP_FUNC_GPIO,
  108. .paddr = 0xEF600700,
  109. .irq = OCP_IRQ_NA,
  110. .pm = IBM_CPM_GPIO0
  111. },
  112. { .vendor = OCP_VENDOR_IBM,
  113. .function = OCP_FUNC_MAL,
  114. .paddr = OCP_PADDR_NA,
  115. .irq = OCP_IRQ_NA,
  116. .pm = OCP_CPM_NA,
  117. .additions = &ibmnp405h_mal0_def,
  118. .show = &ocp_show_mal_data,
  119. },
  120. { .vendor = OCP_VENDOR_IBM,
  121. .function = OCP_FUNC_EMAC,
  122. .index = 0,
  123. .paddr = EMAC0_BASE,
  124. .irq = 37,
  125. .pm = IBM_CPM_EMAC0,
  126. .additions = &ibmnp405h_emac0_def,
  127. .show = &ocp_show_emac_data,
  128. },
  129. { .vendor = OCP_VENDOR_IBM,
  130. .function = OCP_FUNC_EMAC,
  131. .index = 1,
  132. .paddr = 0xEF600900,
  133. .irq = 38,
  134. .pm = IBM_CPM_EMAC1,
  135. .additions = &ibmnp405h_emac1_def,
  136. .show = &ocp_show_emac_data,
  137. },
  138. { .vendor = OCP_VENDOR_IBM,
  139. .function = OCP_FUNC_EMAC,
  140. .index = 2,
  141. .paddr = 0xEF600a00,
  142. .irq = 39,
  143. .pm = IBM_CPM_EMAC2,
  144. .additions = &ibmnp405h_emac2_def,
  145. .show = &ocp_show_emac_data,
  146. },
  147. { .vendor = OCP_VENDOR_IBM,
  148. .function = OCP_FUNC_EMAC,
  149. .index = 3,
  150. .paddr = 0xEF600b00,
  151. .irq = 40,
  152. .pm = IBM_CPM_EMAC3,
  153. .additions = &ibmnp405h_emac3_def,
  154. .show = &ocp_show_emac_data,
  155. },
  156. { .vendor = OCP_VENDOR_IBM,
  157. .function = OCP_FUNC_ZMII,
  158. .paddr = 0xEF600C10,
  159. .irq = OCP_IRQ_NA,
  160. .pm = OCP_CPM_NA,
  161. },
  162. { .vendor = OCP_VENDOR_INVALID
  163. }
  164. };