tlb_64.c 5.5 KB

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  1. /*
  2. * This file contains the routines for flushing entries from the
  3. * TLB and MMU hash table.
  4. *
  5. * Derived from arch/ppc64/mm/init.c:
  6. * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  7. *
  8. * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
  9. * and Cort Dougan (PReP) (cort@cs.nmt.edu)
  10. * Copyright (C) 1996 Paul Mackerras
  11. * Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  12. *
  13. * Derived from "arch/i386/mm/init.c"
  14. * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
  15. *
  16. * Dave Engebretsen <engebret@us.ibm.com>
  17. * Rework for PPC64 port.
  18. *
  19. * This program is free software; you can redistribute it and/or
  20. * modify it under the terms of the GNU General Public License
  21. * as published by the Free Software Foundation; either version
  22. * 2 of the License, or (at your option) any later version.
  23. */
  24. #include <linux/kernel.h>
  25. #include <linux/mm.h>
  26. #include <linux/init.h>
  27. #include <linux/percpu.h>
  28. #include <linux/hardirq.h>
  29. #include <asm/pgalloc.h>
  30. #include <asm/tlbflush.h>
  31. #include <asm/tlb.h>
  32. #include <asm/bug.h>
  33. DEFINE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
  34. /* This is declared as we are using the more or less generic
  35. * include/asm-powerpc/tlb.h file -- tgall
  36. */
  37. DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
  38. DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
  39. unsigned long pte_freelist_forced_free;
  40. struct pte_freelist_batch
  41. {
  42. struct rcu_head rcu;
  43. unsigned int index;
  44. pgtable_free_t tables[0];
  45. };
  46. DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
  47. unsigned long pte_freelist_forced_free;
  48. #define PTE_FREELIST_SIZE \
  49. ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
  50. / sizeof(pgtable_free_t))
  51. #ifdef CONFIG_SMP
  52. static void pte_free_smp_sync(void *arg)
  53. {
  54. /* Do nothing, just ensure we sync with all CPUs */
  55. }
  56. #endif
  57. /* This is only called when we are critically out of memory
  58. * (and fail to get a page in pte_free_tlb).
  59. */
  60. static void pgtable_free_now(pgtable_free_t pgf)
  61. {
  62. pte_freelist_forced_free++;
  63. smp_call_function(pte_free_smp_sync, NULL, 0, 1);
  64. pgtable_free(pgf);
  65. }
  66. static void pte_free_rcu_callback(struct rcu_head *head)
  67. {
  68. struct pte_freelist_batch *batch =
  69. container_of(head, struct pte_freelist_batch, rcu);
  70. unsigned int i;
  71. for (i = 0; i < batch->index; i++)
  72. pgtable_free(batch->tables[i]);
  73. free_page((unsigned long)batch);
  74. }
  75. static void pte_free_submit(struct pte_freelist_batch *batch)
  76. {
  77. INIT_RCU_HEAD(&batch->rcu);
  78. call_rcu(&batch->rcu, pte_free_rcu_callback);
  79. }
  80. void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf)
  81. {
  82. /* This is safe since tlb_gather_mmu has disabled preemption */
  83. cpumask_t local_cpumask = cpumask_of_cpu(smp_processor_id());
  84. struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
  85. if (atomic_read(&tlb->mm->mm_users) < 2 ||
  86. cpus_equal(tlb->mm->cpu_vm_mask, local_cpumask)) {
  87. pgtable_free(pgf);
  88. return;
  89. }
  90. if (*batchp == NULL) {
  91. *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
  92. if (*batchp == NULL) {
  93. pgtable_free_now(pgf);
  94. return;
  95. }
  96. (*batchp)->index = 0;
  97. }
  98. (*batchp)->tables[(*batchp)->index++] = pgf;
  99. if ((*batchp)->index == PTE_FREELIST_SIZE) {
  100. pte_free_submit(*batchp);
  101. *batchp = NULL;
  102. }
  103. }
  104. /*
  105. * Update the MMU hash table to correspond with a change to
  106. * a Linux PTE. If wrprot is true, it is permissible to
  107. * change the existing HPTE to read-only rather than removing it
  108. * (if we remove it we should clear the _PTE_HPTEFLAGS bits).
  109. */
  110. void hpte_update(struct mm_struct *mm, unsigned long addr,
  111. pte_t *ptep, unsigned long pte, int huge)
  112. {
  113. struct ppc64_tlb_batch *batch = &__get_cpu_var(ppc64_tlb_batch);
  114. unsigned long vsid;
  115. unsigned int psize;
  116. int i;
  117. i = batch->index;
  118. /* We mask the address for the base page size. Huge pages will
  119. * have applied their own masking already
  120. */
  121. addr &= PAGE_MASK;
  122. /* Get page size (maybe move back to caller) */
  123. if (huge) {
  124. #ifdef CONFIG_HUGETLB_PAGE
  125. psize = mmu_huge_psize;
  126. #else
  127. BUG();
  128. psize = pte_pagesize_index(pte); /* shutup gcc */
  129. #endif
  130. } else
  131. psize = pte_pagesize_index(pte);
  132. /*
  133. * This can happen when we are in the middle of a TLB batch and
  134. * we encounter memory pressure (eg copy_page_range when it tries
  135. * to allocate a new pte). If we have to reclaim memory and end
  136. * up scanning and resetting referenced bits then our batch context
  137. * will change mid stream.
  138. *
  139. * We also need to ensure only one page size is present in a given
  140. * batch
  141. */
  142. if (i != 0 && (mm != batch->mm || batch->psize != psize)) {
  143. flush_tlb_pending();
  144. i = 0;
  145. }
  146. if (i == 0) {
  147. batch->mm = mm;
  148. batch->psize = psize;
  149. }
  150. if (!is_kernel_addr(addr)) {
  151. vsid = get_vsid(mm->context.id, addr);
  152. WARN_ON(vsid == 0);
  153. } else
  154. vsid = get_kernel_vsid(addr);
  155. batch->vaddr[i] = (vsid << 28 ) | (addr & 0x0fffffff);
  156. batch->pte[i] = __real_pte(__pte(pte), ptep);
  157. batch->index = ++i;
  158. if (i >= PPC64_TLB_BATCH_NR)
  159. flush_tlb_pending();
  160. }
  161. void __flush_tlb_pending(struct ppc64_tlb_batch *batch)
  162. {
  163. int i;
  164. int cpu;
  165. cpumask_t tmp;
  166. int local = 0;
  167. BUG_ON(in_interrupt());
  168. cpu = get_cpu();
  169. i = batch->index;
  170. tmp = cpumask_of_cpu(cpu);
  171. if (cpus_equal(batch->mm->cpu_vm_mask, tmp))
  172. local = 1;
  173. if (i == 1)
  174. flush_hash_page(batch->vaddr[0], batch->pte[0],
  175. batch->psize, local);
  176. else
  177. flush_hash_range(i, local);
  178. batch->index = 0;
  179. put_cpu();
  180. }
  181. void pte_free_finish(void)
  182. {
  183. /* This is safe since tlb_gather_mmu has disabled preemption */
  184. struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
  185. if (*batchp == NULL)
  186. return;
  187. pte_free_submit(*batchp);
  188. *batchp = NULL;
  189. }