iommu.c 16 KB

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  1. /*
  2. * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  3. *
  4. * Rewrite, cleanup, new allocation schemes, virtual merging:
  5. * Copyright (C) 2004 Olof Johansson, IBM Corporation
  6. * and Ben. Herrenschmidt, IBM Corporation
  7. *
  8. * Dynamic DMA mapping support, bus-independent parts.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  23. */
  24. #include <linux/init.h>
  25. #include <linux/types.h>
  26. #include <linux/slab.h>
  27. #include <linux/mm.h>
  28. #include <linux/spinlock.h>
  29. #include <linux/string.h>
  30. #include <linux/dma-mapping.h>
  31. #include <linux/init.h>
  32. #include <linux/bitops.h>
  33. #include <asm/io.h>
  34. #include <asm/prom.h>
  35. #include <asm/iommu.h>
  36. #include <asm/pci-bridge.h>
  37. #include <asm/machdep.h>
  38. #include <asm/kdump.h>
  39. #define DBG(...)
  40. #ifdef CONFIG_IOMMU_VMERGE
  41. static int novmerge = 0;
  42. #else
  43. static int novmerge = 1;
  44. #endif
  45. static int __init setup_iommu(char *str)
  46. {
  47. if (!strcmp(str, "novmerge"))
  48. novmerge = 1;
  49. else if (!strcmp(str, "vmerge"))
  50. novmerge = 0;
  51. return 1;
  52. }
  53. __setup("iommu=", setup_iommu);
  54. static unsigned long iommu_range_alloc(struct iommu_table *tbl,
  55. unsigned long npages,
  56. unsigned long *handle,
  57. unsigned long mask,
  58. unsigned int align_order)
  59. {
  60. unsigned long n, end, i, start;
  61. unsigned long limit;
  62. int largealloc = npages > 15;
  63. int pass = 0;
  64. unsigned long align_mask;
  65. align_mask = 0xffffffffffffffffl >> (64 - align_order);
  66. /* This allocator was derived from x86_64's bit string search */
  67. /* Sanity check */
  68. if (unlikely(npages == 0)) {
  69. if (printk_ratelimit())
  70. WARN_ON(1);
  71. return DMA_ERROR_CODE;
  72. }
  73. if (handle && *handle)
  74. start = *handle;
  75. else
  76. start = largealloc ? tbl->it_largehint : tbl->it_hint;
  77. /* Use only half of the table for small allocs (15 pages or less) */
  78. limit = largealloc ? tbl->it_size : tbl->it_halfpoint;
  79. if (largealloc && start < tbl->it_halfpoint)
  80. start = tbl->it_halfpoint;
  81. /* The case below can happen if we have a small segment appended
  82. * to a large, or when the previous alloc was at the very end of
  83. * the available space. If so, go back to the initial start.
  84. */
  85. if (start >= limit)
  86. start = largealloc ? tbl->it_largehint : tbl->it_hint;
  87. again:
  88. if (limit + tbl->it_offset > mask) {
  89. limit = mask - tbl->it_offset + 1;
  90. /* If we're constrained on address range, first try
  91. * at the masked hint to avoid O(n) search complexity,
  92. * but on second pass, start at 0.
  93. */
  94. if ((start & mask) >= limit || pass > 0)
  95. start = 0;
  96. else
  97. start &= mask;
  98. }
  99. n = find_next_zero_bit(tbl->it_map, limit, start);
  100. /* Align allocation */
  101. n = (n + align_mask) & ~align_mask;
  102. end = n + npages;
  103. if (unlikely(end >= limit)) {
  104. if (likely(pass < 2)) {
  105. /* First failure, just rescan the half of the table.
  106. * Second failure, rescan the other half of the table.
  107. */
  108. start = (largealloc ^ pass) ? tbl->it_halfpoint : 0;
  109. limit = pass ? tbl->it_size : limit;
  110. pass++;
  111. goto again;
  112. } else {
  113. /* Third failure, give up */
  114. return DMA_ERROR_CODE;
  115. }
  116. }
  117. for (i = n; i < end; i++)
  118. if (test_bit(i, tbl->it_map)) {
  119. start = i+1;
  120. goto again;
  121. }
  122. for (i = n; i < end; i++)
  123. __set_bit(i, tbl->it_map);
  124. /* Bump the hint to a new block for small allocs. */
  125. if (largealloc) {
  126. /* Don't bump to new block to avoid fragmentation */
  127. tbl->it_largehint = end;
  128. } else {
  129. /* Overflow will be taken care of at the next allocation */
  130. tbl->it_hint = (end + tbl->it_blocksize - 1) &
  131. ~(tbl->it_blocksize - 1);
  132. }
  133. /* Update handle for SG allocations */
  134. if (handle)
  135. *handle = end;
  136. return n;
  137. }
  138. static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *page,
  139. unsigned int npages, enum dma_data_direction direction,
  140. unsigned long mask, unsigned int align_order)
  141. {
  142. unsigned long entry, flags;
  143. dma_addr_t ret = DMA_ERROR_CODE;
  144. spin_lock_irqsave(&(tbl->it_lock), flags);
  145. entry = iommu_range_alloc(tbl, npages, NULL, mask, align_order);
  146. if (unlikely(entry == DMA_ERROR_CODE)) {
  147. spin_unlock_irqrestore(&(tbl->it_lock), flags);
  148. return DMA_ERROR_CODE;
  149. }
  150. entry += tbl->it_offset; /* Offset into real TCE table */
  151. ret = entry << PAGE_SHIFT; /* Set the return dma address */
  152. /* Put the TCEs in the HW table */
  153. ppc_md.tce_build(tbl, entry, npages, (unsigned long)page & PAGE_MASK,
  154. direction);
  155. /* Flush/invalidate TLB caches if necessary */
  156. if (ppc_md.tce_flush)
  157. ppc_md.tce_flush(tbl);
  158. spin_unlock_irqrestore(&(tbl->it_lock), flags);
  159. /* Make sure updates are seen by hardware */
  160. mb();
  161. return ret;
  162. }
  163. static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
  164. unsigned int npages)
  165. {
  166. unsigned long entry, free_entry;
  167. unsigned long i;
  168. entry = dma_addr >> PAGE_SHIFT;
  169. free_entry = entry - tbl->it_offset;
  170. if (((free_entry + npages) > tbl->it_size) ||
  171. (entry < tbl->it_offset)) {
  172. if (printk_ratelimit()) {
  173. printk(KERN_INFO "iommu_free: invalid entry\n");
  174. printk(KERN_INFO "\tentry = 0x%lx\n", entry);
  175. printk(KERN_INFO "\tdma_addr = 0x%lx\n", (u64)dma_addr);
  176. printk(KERN_INFO "\tTable = 0x%lx\n", (u64)tbl);
  177. printk(KERN_INFO "\tbus# = 0x%lx\n", (u64)tbl->it_busno);
  178. printk(KERN_INFO "\tsize = 0x%lx\n", (u64)tbl->it_size);
  179. printk(KERN_INFO "\tstartOff = 0x%lx\n", (u64)tbl->it_offset);
  180. printk(KERN_INFO "\tindex = 0x%lx\n", (u64)tbl->it_index);
  181. WARN_ON(1);
  182. }
  183. return;
  184. }
  185. ppc_md.tce_free(tbl, entry, npages);
  186. for (i = 0; i < npages; i++)
  187. __clear_bit(free_entry+i, tbl->it_map);
  188. }
  189. static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
  190. unsigned int npages)
  191. {
  192. unsigned long flags;
  193. spin_lock_irqsave(&(tbl->it_lock), flags);
  194. __iommu_free(tbl, dma_addr, npages);
  195. /* Make sure TLB cache is flushed if the HW needs it. We do
  196. * not do an mb() here on purpose, it is not needed on any of
  197. * the current platforms.
  198. */
  199. if (ppc_md.tce_flush)
  200. ppc_md.tce_flush(tbl);
  201. spin_unlock_irqrestore(&(tbl->it_lock), flags);
  202. }
  203. int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
  204. struct scatterlist *sglist, int nelems,
  205. unsigned long mask, enum dma_data_direction direction)
  206. {
  207. dma_addr_t dma_next = 0, dma_addr;
  208. unsigned long flags;
  209. struct scatterlist *s, *outs, *segstart;
  210. int outcount, incount;
  211. unsigned long handle;
  212. BUG_ON(direction == DMA_NONE);
  213. if ((nelems == 0) || !tbl)
  214. return 0;
  215. outs = s = segstart = &sglist[0];
  216. outcount = 1;
  217. incount = nelems;
  218. handle = 0;
  219. /* Init first segment length for backout at failure */
  220. outs->dma_length = 0;
  221. DBG("mapping %d elements:\n", nelems);
  222. spin_lock_irqsave(&(tbl->it_lock), flags);
  223. for (s = outs; nelems; nelems--, s++) {
  224. unsigned long vaddr, npages, entry, slen;
  225. slen = s->length;
  226. /* Sanity check */
  227. if (slen == 0) {
  228. dma_next = 0;
  229. continue;
  230. }
  231. /* Allocate iommu entries for that segment */
  232. vaddr = (unsigned long)page_address(s->page) + s->offset;
  233. npages = PAGE_ALIGN(vaddr + slen) - (vaddr & PAGE_MASK);
  234. npages >>= PAGE_SHIFT;
  235. entry = iommu_range_alloc(tbl, npages, &handle, mask >> PAGE_SHIFT, 0);
  236. DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
  237. /* Handle failure */
  238. if (unlikely(entry == DMA_ERROR_CODE)) {
  239. if (printk_ratelimit())
  240. printk(KERN_INFO "iommu_alloc failed, tbl %p vaddr %lx"
  241. " npages %lx\n", tbl, vaddr, npages);
  242. goto failure;
  243. }
  244. /* Convert entry to a dma_addr_t */
  245. entry += tbl->it_offset;
  246. dma_addr = entry << PAGE_SHIFT;
  247. dma_addr |= s->offset;
  248. DBG(" - %lx pages, entry: %lx, dma_addr: %lx\n",
  249. npages, entry, dma_addr);
  250. /* Insert into HW table */
  251. ppc_md.tce_build(tbl, entry, npages, vaddr & PAGE_MASK, direction);
  252. /* If we are in an open segment, try merging */
  253. if (segstart != s) {
  254. DBG(" - trying merge...\n");
  255. /* We cannot merge if:
  256. * - allocated dma_addr isn't contiguous to previous allocation
  257. */
  258. if (novmerge || (dma_addr != dma_next)) {
  259. /* Can't merge: create a new segment */
  260. segstart = s;
  261. outcount++; outs++;
  262. DBG(" can't merge, new segment.\n");
  263. } else {
  264. outs->dma_length += s->length;
  265. DBG(" merged, new len: %lx\n", outs->dma_length);
  266. }
  267. }
  268. if (segstart == s) {
  269. /* This is a new segment, fill entries */
  270. DBG(" - filling new segment.\n");
  271. outs->dma_address = dma_addr;
  272. outs->dma_length = slen;
  273. }
  274. /* Calculate next page pointer for contiguous check */
  275. dma_next = dma_addr + slen;
  276. DBG(" - dma next is: %lx\n", dma_next);
  277. }
  278. /* Flush/invalidate TLB caches if necessary */
  279. if (ppc_md.tce_flush)
  280. ppc_md.tce_flush(tbl);
  281. spin_unlock_irqrestore(&(tbl->it_lock), flags);
  282. DBG("mapped %d elements:\n", outcount);
  283. /* For the sake of iommu_unmap_sg, we clear out the length in the
  284. * next entry of the sglist if we didn't fill the list completely
  285. */
  286. if (outcount < incount) {
  287. outs++;
  288. outs->dma_address = DMA_ERROR_CODE;
  289. outs->dma_length = 0;
  290. }
  291. /* Make sure updates are seen by hardware */
  292. mb();
  293. return outcount;
  294. failure:
  295. for (s = &sglist[0]; s <= outs; s++) {
  296. if (s->dma_length != 0) {
  297. unsigned long vaddr, npages;
  298. vaddr = s->dma_address & PAGE_MASK;
  299. npages = (PAGE_ALIGN(s->dma_address + s->dma_length) - vaddr)
  300. >> PAGE_SHIFT;
  301. __iommu_free(tbl, vaddr, npages);
  302. s->dma_address = DMA_ERROR_CODE;
  303. s->dma_length = 0;
  304. }
  305. }
  306. spin_unlock_irqrestore(&(tbl->it_lock), flags);
  307. return 0;
  308. }
  309. void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
  310. int nelems, enum dma_data_direction direction)
  311. {
  312. unsigned long flags;
  313. BUG_ON(direction == DMA_NONE);
  314. if (!tbl)
  315. return;
  316. spin_lock_irqsave(&(tbl->it_lock), flags);
  317. while (nelems--) {
  318. unsigned int npages;
  319. dma_addr_t dma_handle = sglist->dma_address;
  320. if (sglist->dma_length == 0)
  321. break;
  322. npages = (PAGE_ALIGN(dma_handle + sglist->dma_length)
  323. - (dma_handle & PAGE_MASK)) >> PAGE_SHIFT;
  324. __iommu_free(tbl, dma_handle, npages);
  325. sglist++;
  326. }
  327. /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
  328. * do not do an mb() here, the affected platforms do not need it
  329. * when freeing.
  330. */
  331. if (ppc_md.tce_flush)
  332. ppc_md.tce_flush(tbl);
  333. spin_unlock_irqrestore(&(tbl->it_lock), flags);
  334. }
  335. /*
  336. * Build a iommu_table structure. This contains a bit map which
  337. * is used to manage allocation of the tce space.
  338. */
  339. struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
  340. {
  341. unsigned long sz;
  342. static int welcomed = 0;
  343. struct page *page;
  344. /* Set aside 1/4 of the table for large allocations. */
  345. tbl->it_halfpoint = tbl->it_size * 3 / 4;
  346. /* number of bytes needed for the bitmap */
  347. sz = (tbl->it_size + 7) >> 3;
  348. page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz));
  349. if (!page)
  350. panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
  351. tbl->it_map = page_address(page);
  352. memset(tbl->it_map, 0, sz);
  353. tbl->it_hint = 0;
  354. tbl->it_largehint = tbl->it_halfpoint;
  355. spin_lock_init(&tbl->it_lock);
  356. #ifdef CONFIG_CRASH_DUMP
  357. if (ppc_md.tce_get) {
  358. unsigned long index, tceval;
  359. unsigned long tcecount = 0;
  360. /*
  361. * Reserve the existing mappings left by the first kernel.
  362. */
  363. for (index = 0; index < tbl->it_size; index++) {
  364. tceval = ppc_md.tce_get(tbl, index + tbl->it_offset);
  365. /*
  366. * Freed TCE entry contains 0x7fffffffffffffff on JS20
  367. */
  368. if (tceval && (tceval != 0x7fffffffffffffffUL)) {
  369. __set_bit(index, tbl->it_map);
  370. tcecount++;
  371. }
  372. }
  373. if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
  374. printk(KERN_WARNING "TCE table is full; ");
  375. printk(KERN_WARNING "freeing %d entries for the kdump boot\n",
  376. KDUMP_MIN_TCE_ENTRIES);
  377. for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
  378. index < tbl->it_size; index++)
  379. __clear_bit(index, tbl->it_map);
  380. }
  381. }
  382. #else
  383. /* Clear the hardware table in case firmware left allocations in it */
  384. ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size);
  385. #endif
  386. if (!welcomed) {
  387. printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
  388. novmerge ? "disabled" : "enabled");
  389. welcomed = 1;
  390. }
  391. return tbl;
  392. }
  393. void iommu_free_table(struct device_node *dn)
  394. {
  395. struct pci_dn *pdn = dn->data;
  396. struct iommu_table *tbl = pdn->iommu_table;
  397. unsigned long bitmap_sz, i;
  398. unsigned int order;
  399. if (!tbl || !tbl->it_map) {
  400. printk(KERN_ERR "%s: expected TCE map for %s\n", __FUNCTION__,
  401. dn->full_name);
  402. return;
  403. }
  404. /* verify that table contains no entries */
  405. /* it_size is in entries, and we're examining 64 at a time */
  406. for (i = 0; i < (tbl->it_size/64); i++) {
  407. if (tbl->it_map[i] != 0) {
  408. printk(KERN_WARNING "%s: Unexpected TCEs for %s\n",
  409. __FUNCTION__, dn->full_name);
  410. break;
  411. }
  412. }
  413. /* calculate bitmap size in bytes */
  414. bitmap_sz = (tbl->it_size + 7) / 8;
  415. /* free bitmap */
  416. order = get_order(bitmap_sz);
  417. free_pages((unsigned long) tbl->it_map, order);
  418. /* free table */
  419. kfree(tbl);
  420. }
  421. /* Creates TCEs for a user provided buffer. The user buffer must be
  422. * contiguous real kernel storage (not vmalloc). The address of the buffer
  423. * passed here is the kernel (virtual) address of the buffer. The buffer
  424. * need not be page aligned, the dma_addr_t returned will point to the same
  425. * byte within the page as vaddr.
  426. */
  427. dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
  428. size_t size, unsigned long mask,
  429. enum dma_data_direction direction)
  430. {
  431. dma_addr_t dma_handle = DMA_ERROR_CODE;
  432. unsigned long uaddr;
  433. unsigned int npages;
  434. BUG_ON(direction == DMA_NONE);
  435. uaddr = (unsigned long)vaddr;
  436. npages = PAGE_ALIGN(uaddr + size) - (uaddr & PAGE_MASK);
  437. npages >>= PAGE_SHIFT;
  438. if (tbl) {
  439. dma_handle = iommu_alloc(tbl, vaddr, npages, direction,
  440. mask >> PAGE_SHIFT, 0);
  441. if (dma_handle == DMA_ERROR_CODE) {
  442. if (printk_ratelimit()) {
  443. printk(KERN_INFO "iommu_alloc failed, "
  444. "tbl %p vaddr %p npages %d\n",
  445. tbl, vaddr, npages);
  446. }
  447. } else
  448. dma_handle |= (uaddr & ~PAGE_MASK);
  449. }
  450. return dma_handle;
  451. }
  452. void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
  453. size_t size, enum dma_data_direction direction)
  454. {
  455. BUG_ON(direction == DMA_NONE);
  456. if (tbl)
  457. iommu_free(tbl, dma_handle, (PAGE_ALIGN(dma_handle + size) -
  458. (dma_handle & PAGE_MASK)) >> PAGE_SHIFT);
  459. }
  460. /* Allocates a contiguous real buffer and creates mappings over it.
  461. * Returns the virtual address of the buffer and sets dma_handle
  462. * to the dma address (mapping) of the first page.
  463. */
  464. void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
  465. dma_addr_t *dma_handle, unsigned long mask, gfp_t flag, int node)
  466. {
  467. void *ret = NULL;
  468. dma_addr_t mapping;
  469. unsigned int npages, order;
  470. struct page *page;
  471. size = PAGE_ALIGN(size);
  472. npages = size >> PAGE_SHIFT;
  473. order = get_order(size);
  474. /*
  475. * Client asked for way too much space. This is checked later
  476. * anyway. It is easier to debug here for the drivers than in
  477. * the tce tables.
  478. */
  479. if (order >= IOMAP_MAX_ORDER) {
  480. printk("iommu_alloc_consistent size too large: 0x%lx\n", size);
  481. return NULL;
  482. }
  483. if (!tbl)
  484. return NULL;
  485. /* Alloc enough pages (and possibly more) */
  486. page = alloc_pages_node(node, flag, order);
  487. if (!page)
  488. return NULL;
  489. ret = page_address(page);
  490. memset(ret, 0, size);
  491. /* Set up tces to cover the allocated range */
  492. mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL,
  493. mask >> PAGE_SHIFT, order);
  494. if (mapping == DMA_ERROR_CODE) {
  495. free_pages((unsigned long)ret, order);
  496. return NULL;
  497. }
  498. *dma_handle = mapping;
  499. return ret;
  500. }
  501. void iommu_free_coherent(struct iommu_table *tbl, size_t size,
  502. void *vaddr, dma_addr_t dma_handle)
  503. {
  504. unsigned int npages;
  505. if (tbl) {
  506. size = PAGE_ALIGN(size);
  507. npages = size >> PAGE_SHIFT;
  508. iommu_free(tbl, dma_handle, npages);
  509. free_pages((unsigned long)vaddr, get_order(size));
  510. }
  511. }