irq.c 2.9 KB

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  1. /*
  2. * Copyright (C) 2002 Momentum Computer, Inc.
  3. * Author: Matthew Dharm, mdharm@momenco.com
  4. *
  5. * Based on work by:
  6. * Copyright (C) 2000 RidgeRun, Inc.
  7. * Author: RidgeRun, Inc.
  8. * glonnon@ridgerun.com, skranz@ridgerun.com, stevej@ridgerun.com
  9. *
  10. * Copyright 2001 MontaVista Software Inc.
  11. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  12. *
  13. * Copyright (C) 2000, 01, 06 Ralf Baechle (ralf@linux-mips.org)
  14. *
  15. * This program is free software; you can redistribute it and/or modify it
  16. * under the terms of the GNU General Public License as published by the
  17. * Free Software Foundation; either version 2 of the License, or (at your
  18. * option) any later version.
  19. *
  20. * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23. * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. * You should have received a copy of the GNU General Public License along
  32. * with this program; if not, write to the Free Software Foundation, Inc.,
  33. * 675 Mass Ave, Cambridge, MA 02139, USA.
  34. */
  35. #include <linux/init.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/signal.h>
  38. #include <linux/types.h>
  39. #include <asm/irq_cpu.h>
  40. #include <asm/mipsregs.h>
  41. #include <asm/time.h>
  42. asmlinkage void plat_irq_dispatch(void)
  43. {
  44. unsigned int pending = read_c0_cause() & read_c0_status();
  45. if (pending & STATUSF_IP0)
  46. do_IRQ(0);
  47. else if (pending & STATUSF_IP1)
  48. do_IRQ(1);
  49. else if (pending & STATUSF_IP2)
  50. do_IRQ(2);
  51. else if (pending & STATUSF_IP3)
  52. do_IRQ(3);
  53. else if (pending & STATUSF_IP4)
  54. do_IRQ(4);
  55. else if (pending & STATUSF_IP5)
  56. do_IRQ(5);
  57. else if (pending & STATUSF_IP6)
  58. do_IRQ(6);
  59. else if (pending & STATUSF_IP7)
  60. ll_timer_interrupt(7);
  61. else {
  62. /*
  63. * Now look at the extended interrupts
  64. */
  65. pending = (read_c0_cause() & (read_c0_intcontrol() << 8)) >> 16;
  66. if (pending & STATUSF_IP8)
  67. ll_mv64340_irq();
  68. }
  69. }
  70. static struct irqaction cascade_mv64340 = {
  71. no_action, IRQF_DISABLED, CPU_MASK_NONE, "MV64340-Cascade", NULL, NULL
  72. };
  73. void __init arch_init_irq(void)
  74. {
  75. /*
  76. * Clear all of the interrupts while we change the able around a bit.
  77. * int-handler is not on bootstrap
  78. */
  79. clear_c0_status(ST0_IM);
  80. mips_cpu_irq_init(0);
  81. rm7k_cpu_irq_init(8);
  82. /* set up the cascading interrupts */
  83. setup_irq(8, &cascade_mv64340);
  84. mv64340_irq_init(16);
  85. set_c0_status(ST0_IM);
  86. }