pit.c 2.6 KB

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  1. /***************************************************************************/
  2. /*
  3. * pit.c -- Freescale ColdFire PIT timer. Currently this type of
  4. * hardware timer only exists in the Freescale ColdFire
  5. * 5270/5271, 5282 and other CPUs.
  6. *
  7. * Copyright (C) 1999-2006, Greg Ungerer (gerg@snapgear.com)
  8. * Copyright (C) 2001-2004, SnapGear Inc. (www.snapgear.com)
  9. *
  10. */
  11. /***************************************************************************/
  12. #include <linux/kernel.h>
  13. #include <linux/sched.h>
  14. #include <linux/param.h>
  15. #include <linux/init.h>
  16. #include <linux/interrupt.h>
  17. #include <asm/io.h>
  18. #include <asm/irq.h>
  19. #include <asm/coldfire.h>
  20. #include <asm/mcfpit.h>
  21. #include <asm/mcfsim.h>
  22. /***************************************************************************/
  23. /*
  24. * By default use timer1 as the system clock timer.
  25. */
  26. #define TA(a) (MCF_IPSBAR + MCFPIT_BASE1 + (a))
  27. /***************************************************************************/
  28. void coldfire_pit_tick(void)
  29. {
  30. unsigned short pcsr;
  31. /* Reset the ColdFire timer */
  32. pcsr = __raw_readw(TA(MCFPIT_PCSR));
  33. __raw_writew(pcsr | MCFPIT_PCSR_PIF, TA(MCFPIT_PCSR));
  34. }
  35. /***************************************************************************/
  36. void coldfire_pit_init(irqreturn_t (*handler)(int, void *, struct pt_regs *))
  37. {
  38. volatile unsigned char *icrp;
  39. volatile unsigned long *imrp;
  40. request_irq(MCFINT_VECBASE + MCFINT_PIT1, handler, IRQF_DISABLED,
  41. "ColdFire Timer", NULL);
  42. icrp = (volatile unsigned char *) (MCF_IPSBAR + MCFICM_INTC0 +
  43. MCFINTC_ICR0 + MCFINT_PIT1);
  44. *icrp = ICR_INTRCONF;
  45. imrp = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
  46. *imrp &= ~MCFPIT_IMR_IBIT;
  47. /* Set up PIT timer 1 as poll clock */
  48. __raw_writew(MCFPIT_PCSR_DISABLE, TA(MCFPIT_PCSR));
  49. __raw_writew(((MCF_CLK / 2) / 64) / HZ, TA(MCFPIT_PMR));
  50. __raw_writew(MCFPIT_PCSR_EN | MCFPIT_PCSR_PIE | MCFPIT_PCSR_OVW |
  51. MCFPIT_PCSR_RLD | MCFPIT_PCSR_CLK64, TA(MCFPIT_PCSR));
  52. }
  53. /***************************************************************************/
  54. unsigned long coldfire_pit_offset(void)
  55. {
  56. volatile unsigned long *ipr;
  57. unsigned long pmr, pcntr, offset;
  58. ipr = (volatile unsigned long *) (MCF_IPSBAR + MCFICM_INTC0 + MCFPIT_IMR);
  59. pmr = __raw_readw(TA(MCFPIT_PMR));
  60. pcntr = __raw_readw(TA(MCFPIT_PCNTR));
  61. /*
  62. * If we are still in the first half of the upcount and a
  63. * timer interupt is pending, then add on a ticks worth of time.
  64. */
  65. offset = ((pmr - pcntr) * (1000000 / HZ)) / pmr;
  66. if ((offset < (1000000 / HZ / 2)) && (*ipr & MCFPIT_IMR_IBIT))
  67. offset += 1000000 / HZ;
  68. return offset;
  69. }
  70. /***************************************************************************/