memory.c 3.2 KB

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  1. /*
  2. * linux/arch/m68knommu/mm/memory.c
  3. *
  4. * Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
  5. * Copyright (C) 1999-2002, Greg Ungerer (gerg@snapgear.com)
  6. *
  7. * Based on:
  8. *
  9. * linux/arch/m68k/mm/memory.c
  10. *
  11. * Copyright (C) 1995 Hamish Macdonald
  12. */
  13. #include <linux/mm.h>
  14. #include <linux/kernel.h>
  15. #include <linux/string.h>
  16. #include <linux/types.h>
  17. #include <linux/slab.h>
  18. #include <asm/setup.h>
  19. #include <asm/segment.h>
  20. #include <asm/page.h>
  21. #include <asm/pgtable.h>
  22. #include <asm/system.h>
  23. #include <asm/traps.h>
  24. #include <asm/io.h>
  25. /*
  26. * cache_clear() semantics: Clear any cache entries for the area in question,
  27. * without writing back dirty entries first. This is useful if the data will
  28. * be overwritten anyway, e.g. by DMA to memory. The range is defined by a
  29. * _physical_ address.
  30. */
  31. void cache_clear (unsigned long paddr, int len)
  32. {
  33. }
  34. /*
  35. * Define cache invalidate functions. The ColdFire 5407 is really
  36. * the only processor that needs to do some work here. Anything
  37. * that has separate data and instruction caches will be a problem.
  38. */
  39. #ifdef CONFIG_M5407
  40. static __inline__ void cache_invalidate_lines(unsigned long paddr, int len)
  41. {
  42. unsigned long sset, eset;
  43. sset = (paddr & 0x00000ff0);
  44. eset = ((paddr + len) & 0x0000ff0) + 0x10;
  45. __asm__ __volatile__ (
  46. "nop\n\t"
  47. "clrl %%d0\n\t"
  48. "1:\n\t"
  49. "movel %0,%%a0\n\t"
  50. "addl %%d0,%%a0\n\t"
  51. "2:\n\t"
  52. ".word 0xf4e8\n\t"
  53. "addl #0x10,%%a0\n\t"
  54. "cmpl %1,%%a0\n\t"
  55. "blt 2b\n\t"
  56. "addql #1,%%d0\n\t"
  57. "cmpil #4,%%d0\n\t"
  58. "bne 1b"
  59. : : "a" (sset), "a" (eset) : "d0", "a0" );
  60. }
  61. #else
  62. #define cache_invalidate_lines(a,b)
  63. #endif
  64. /*
  65. * cache_push() semantics: Write back any dirty cache data in the given area,
  66. * and invalidate the range in the instruction cache. It needs not (but may)
  67. * invalidate those entries also in the data cache. The range is defined by a
  68. * _physical_ address.
  69. */
  70. void cache_push (unsigned long paddr, int len)
  71. {
  72. cache_invalidate_lines(paddr, len);
  73. }
  74. /*
  75. * cache_push_v() semantics: Write back any dirty cache data in the given
  76. * area, and invalidate those entries at least in the instruction cache. This
  77. * is intended to be used after data has been written that can be executed as
  78. * code later. The range is defined by a _user_mode_ _virtual_ address (or,
  79. * more exactly, the space is defined by the %sfc/%dfc register.)
  80. */
  81. void cache_push_v (unsigned long vaddr, int len)
  82. {
  83. cache_invalidate_lines(vaddr, len);
  84. }
  85. /* Map some physical address range into the kernel address space. The
  86. * code is copied and adapted from map_chunk().
  87. */
  88. unsigned long kernel_map(unsigned long paddr, unsigned long size,
  89. int nocacheflag, unsigned long *memavailp )
  90. {
  91. return paddr;
  92. }
  93. int is_in_rom(unsigned long addr)
  94. {
  95. extern unsigned long _ramstart, _ramend;
  96. /*
  97. * What we are really trying to do is determine if addr is
  98. * in an allocated kernel memory region. If not then assume
  99. * we cannot free it or otherwise de-allocate it. Ideally
  100. * we could restrict this to really being in a ROM or flash,
  101. * but that would need to be done on a board by board basis,
  102. * not globally.
  103. */
  104. if ((addr < _ramstart) || (addr >= _ramend))
  105. return(1);
  106. /* Default case, not in ROM */
  107. return(0);
  108. }