devs.c 12 KB

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  1. /* linux/arch/arm/mach-s3c2410/devs.c
  2. *
  3. * Copyright (c) 2004 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * Base S3C24XX platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. *
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/platform_device.h>
  20. #include <asm/mach/arch.h>
  21. #include <asm/mach/map.h>
  22. #include <asm/mach/irq.h>
  23. #include <asm/arch/fb.h>
  24. #include <asm/hardware.h>
  25. #include <asm/io.h>
  26. #include <asm/irq.h>
  27. #include <asm/arch/regs-serial.h>
  28. #include "devs.h"
  29. #include "cpu.h"
  30. /* Serial port registrations */
  31. static struct resource s3c2410_uart0_resource[] = {
  32. [0] = {
  33. .start = S3C2410_PA_UART0,
  34. .end = S3C2410_PA_UART0 + 0x3fff,
  35. .flags = IORESOURCE_MEM,
  36. },
  37. [1] = {
  38. .start = IRQ_S3CUART_RX0,
  39. .end = IRQ_S3CUART_ERR0,
  40. .flags = IORESOURCE_IRQ,
  41. }
  42. };
  43. static struct resource s3c2410_uart1_resource[] = {
  44. [0] = {
  45. .start = S3C2410_PA_UART1,
  46. .end = S3C2410_PA_UART1 + 0x3fff,
  47. .flags = IORESOURCE_MEM,
  48. },
  49. [1] = {
  50. .start = IRQ_S3CUART_RX1,
  51. .end = IRQ_S3CUART_ERR1,
  52. .flags = IORESOURCE_IRQ,
  53. }
  54. };
  55. static struct resource s3c2410_uart2_resource[] = {
  56. [0] = {
  57. .start = S3C2410_PA_UART2,
  58. .end = S3C2410_PA_UART2 + 0x3fff,
  59. .flags = IORESOURCE_MEM,
  60. },
  61. [1] = {
  62. .start = IRQ_S3CUART_RX2,
  63. .end = IRQ_S3CUART_ERR2,
  64. .flags = IORESOURCE_IRQ,
  65. }
  66. };
  67. struct s3c24xx_uart_resources s3c2410_uart_resources[] __initdata = {
  68. [0] = {
  69. .resources = s3c2410_uart0_resource,
  70. .nr_resources = ARRAY_SIZE(s3c2410_uart0_resource),
  71. },
  72. [1] = {
  73. .resources = s3c2410_uart1_resource,
  74. .nr_resources = ARRAY_SIZE(s3c2410_uart1_resource),
  75. },
  76. [2] = {
  77. .resources = s3c2410_uart2_resource,
  78. .nr_resources = ARRAY_SIZE(s3c2410_uart2_resource),
  79. },
  80. };
  81. /* yart devices */
  82. static struct platform_device s3c24xx_uart_device0 = {
  83. .id = 0,
  84. };
  85. static struct platform_device s3c24xx_uart_device1 = {
  86. .id = 1,
  87. };
  88. static struct platform_device s3c24xx_uart_device2 = {
  89. .id = 2,
  90. };
  91. struct platform_device *s3c24xx_uart_src[3] = {
  92. &s3c24xx_uart_device0,
  93. &s3c24xx_uart_device1,
  94. &s3c24xx_uart_device2,
  95. };
  96. struct platform_device *s3c24xx_uart_devs[3] = {
  97. };
  98. /* USB Host Controller */
  99. static struct resource s3c_usb_resource[] = {
  100. [0] = {
  101. .start = S3C24XX_PA_USBHOST,
  102. .end = S3C24XX_PA_USBHOST + S3C24XX_SZ_USBHOST - 1,
  103. .flags = IORESOURCE_MEM,
  104. },
  105. [1] = {
  106. .start = IRQ_USBH,
  107. .end = IRQ_USBH,
  108. .flags = IORESOURCE_IRQ,
  109. }
  110. };
  111. static u64 s3c_device_usb_dmamask = 0xffffffffUL;
  112. struct platform_device s3c_device_usb = {
  113. .name = "s3c2410-ohci",
  114. .id = -1,
  115. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  116. .resource = s3c_usb_resource,
  117. .dev = {
  118. .dma_mask = &s3c_device_usb_dmamask,
  119. .coherent_dma_mask = 0xffffffffUL
  120. }
  121. };
  122. EXPORT_SYMBOL(s3c_device_usb);
  123. /* LCD Controller */
  124. static struct resource s3c_lcd_resource[] = {
  125. [0] = {
  126. .start = S3C24XX_PA_LCD,
  127. .end = S3C24XX_PA_LCD + S3C24XX_SZ_LCD - 1,
  128. .flags = IORESOURCE_MEM,
  129. },
  130. [1] = {
  131. .start = IRQ_LCD,
  132. .end = IRQ_LCD,
  133. .flags = IORESOURCE_IRQ,
  134. }
  135. };
  136. static u64 s3c_device_lcd_dmamask = 0xffffffffUL;
  137. struct platform_device s3c_device_lcd = {
  138. .name = "s3c2410-lcd",
  139. .id = -1,
  140. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  141. .resource = s3c_lcd_resource,
  142. .dev = {
  143. .dma_mask = &s3c_device_lcd_dmamask,
  144. .coherent_dma_mask = 0xffffffffUL
  145. }
  146. };
  147. EXPORT_SYMBOL(s3c_device_lcd);
  148. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  149. {
  150. struct s3c2410fb_mach_info *npd;
  151. npd = kmalloc(sizeof(*npd), GFP_KERNEL);
  152. if (npd) {
  153. memcpy(npd, pd, sizeof(*npd));
  154. s3c_device_lcd.dev.platform_data = npd;
  155. } else {
  156. printk(KERN_ERR "no memory for LCD platform data\n");
  157. }
  158. }
  159. /* NAND Controller */
  160. static struct resource s3c_nand_resource[] = {
  161. [0] = {
  162. .start = S3C2410_PA_NAND,
  163. .end = S3C2410_PA_NAND + S3C24XX_SZ_NAND - 1,
  164. .flags = IORESOURCE_MEM,
  165. }
  166. };
  167. struct platform_device s3c_device_nand = {
  168. .name = "s3c2410-nand",
  169. .id = -1,
  170. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  171. .resource = s3c_nand_resource,
  172. };
  173. EXPORT_SYMBOL(s3c_device_nand);
  174. /* USB Device (Gadget)*/
  175. static struct resource s3c_usbgadget_resource[] = {
  176. [0] = {
  177. .start = S3C24XX_PA_USBDEV,
  178. .end = S3C24XX_PA_USBDEV + S3C24XX_SZ_USBDEV - 1,
  179. .flags = IORESOURCE_MEM,
  180. },
  181. [1] = {
  182. .start = IRQ_USBD,
  183. .end = IRQ_USBD,
  184. .flags = IORESOURCE_IRQ,
  185. }
  186. };
  187. struct platform_device s3c_device_usbgadget = {
  188. .name = "s3c2410-usbgadget",
  189. .id = -1,
  190. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  191. .resource = s3c_usbgadget_resource,
  192. };
  193. EXPORT_SYMBOL(s3c_device_usbgadget);
  194. /* Watchdog */
  195. static struct resource s3c_wdt_resource[] = {
  196. [0] = {
  197. .start = S3C24XX_PA_WATCHDOG,
  198. .end = S3C24XX_PA_WATCHDOG + S3C24XX_SZ_WATCHDOG - 1,
  199. .flags = IORESOURCE_MEM,
  200. },
  201. [1] = {
  202. .start = IRQ_WDT,
  203. .end = IRQ_WDT,
  204. .flags = IORESOURCE_IRQ,
  205. }
  206. };
  207. struct platform_device s3c_device_wdt = {
  208. .name = "s3c2410-wdt",
  209. .id = -1,
  210. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  211. .resource = s3c_wdt_resource,
  212. };
  213. EXPORT_SYMBOL(s3c_device_wdt);
  214. /* I2C */
  215. static struct resource s3c_i2c_resource[] = {
  216. [0] = {
  217. .start = S3C24XX_PA_IIC,
  218. .end = S3C24XX_PA_IIC + S3C24XX_SZ_IIC - 1,
  219. .flags = IORESOURCE_MEM,
  220. },
  221. [1] = {
  222. .start = IRQ_IIC,
  223. .end = IRQ_IIC,
  224. .flags = IORESOURCE_IRQ,
  225. }
  226. };
  227. struct platform_device s3c_device_i2c = {
  228. .name = "s3c2410-i2c",
  229. .id = -1,
  230. .num_resources = ARRAY_SIZE(s3c_i2c_resource),
  231. .resource = s3c_i2c_resource,
  232. };
  233. EXPORT_SYMBOL(s3c_device_i2c);
  234. /* IIS */
  235. static struct resource s3c_iis_resource[] = {
  236. [0] = {
  237. .start = S3C24XX_PA_IIS,
  238. .end = S3C24XX_PA_IIS + S3C24XX_SZ_IIS -1,
  239. .flags = IORESOURCE_MEM,
  240. }
  241. };
  242. static u64 s3c_device_iis_dmamask = 0xffffffffUL;
  243. struct platform_device s3c_device_iis = {
  244. .name = "s3c2410-iis",
  245. .id = -1,
  246. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  247. .resource = s3c_iis_resource,
  248. .dev = {
  249. .dma_mask = &s3c_device_iis_dmamask,
  250. .coherent_dma_mask = 0xffffffffUL
  251. }
  252. };
  253. EXPORT_SYMBOL(s3c_device_iis);
  254. /* RTC */
  255. static struct resource s3c_rtc_resource[] = {
  256. [0] = {
  257. .start = S3C24XX_PA_RTC,
  258. .end = S3C24XX_PA_RTC + 0xff,
  259. .flags = IORESOURCE_MEM,
  260. },
  261. [1] = {
  262. .start = IRQ_RTC,
  263. .end = IRQ_RTC,
  264. .flags = IORESOURCE_IRQ,
  265. },
  266. [2] = {
  267. .start = IRQ_TICK,
  268. .end = IRQ_TICK,
  269. .flags = IORESOURCE_IRQ
  270. }
  271. };
  272. struct platform_device s3c_device_rtc = {
  273. .name = "s3c2410-rtc",
  274. .id = -1,
  275. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  276. .resource = s3c_rtc_resource,
  277. };
  278. EXPORT_SYMBOL(s3c_device_rtc);
  279. /* ADC */
  280. static struct resource s3c_adc_resource[] = {
  281. [0] = {
  282. .start = S3C24XX_PA_ADC,
  283. .end = S3C24XX_PA_ADC + S3C24XX_SZ_ADC - 1,
  284. .flags = IORESOURCE_MEM,
  285. },
  286. [1] = {
  287. .start = IRQ_TC,
  288. .end = IRQ_TC,
  289. .flags = IORESOURCE_IRQ,
  290. },
  291. [2] = {
  292. .start = IRQ_ADC,
  293. .end = IRQ_ADC,
  294. .flags = IORESOURCE_IRQ,
  295. }
  296. };
  297. struct platform_device s3c_device_adc = {
  298. .name = "s3c2410-adc",
  299. .id = -1,
  300. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  301. .resource = s3c_adc_resource,
  302. };
  303. /* SDI */
  304. static struct resource s3c_sdi_resource[] = {
  305. [0] = {
  306. .start = S3C2410_PA_SDI,
  307. .end = S3C2410_PA_SDI + S3C24XX_SZ_SDI - 1,
  308. .flags = IORESOURCE_MEM,
  309. },
  310. [1] = {
  311. .start = IRQ_SDI,
  312. .end = IRQ_SDI,
  313. .flags = IORESOURCE_IRQ,
  314. }
  315. };
  316. struct platform_device s3c_device_sdi = {
  317. .name = "s3c2410-sdi",
  318. .id = -1,
  319. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  320. .resource = s3c_sdi_resource,
  321. };
  322. EXPORT_SYMBOL(s3c_device_sdi);
  323. /* SPI (0) */
  324. static struct resource s3c_spi0_resource[] = {
  325. [0] = {
  326. .start = S3C24XX_PA_SPI,
  327. .end = S3C24XX_PA_SPI + 0x1f,
  328. .flags = IORESOURCE_MEM,
  329. },
  330. [1] = {
  331. .start = IRQ_SPI0,
  332. .end = IRQ_SPI0,
  333. .flags = IORESOURCE_IRQ,
  334. }
  335. };
  336. static u64 s3c_device_spi0_dmamask = 0xffffffffUL;
  337. struct platform_device s3c_device_spi0 = {
  338. .name = "s3c2410-spi",
  339. .id = 0,
  340. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  341. .resource = s3c_spi0_resource,
  342. .dev = {
  343. .dma_mask = &s3c_device_spi0_dmamask,
  344. .coherent_dma_mask = 0xffffffffUL
  345. }
  346. };
  347. EXPORT_SYMBOL(s3c_device_spi0);
  348. /* SPI (1) */
  349. static struct resource s3c_spi1_resource[] = {
  350. [0] = {
  351. .start = S3C24XX_PA_SPI + 0x20,
  352. .end = S3C24XX_PA_SPI + 0x20 + 0x1f,
  353. .flags = IORESOURCE_MEM,
  354. },
  355. [1] = {
  356. .start = IRQ_SPI1,
  357. .end = IRQ_SPI1,
  358. .flags = IORESOURCE_IRQ,
  359. }
  360. };
  361. static u64 s3c_device_spi1_dmamask = 0xffffffffUL;
  362. struct platform_device s3c_device_spi1 = {
  363. .name = "s3c2410-spi",
  364. .id = 1,
  365. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  366. .resource = s3c_spi1_resource,
  367. .dev = {
  368. .dma_mask = &s3c_device_spi1_dmamask,
  369. .coherent_dma_mask = 0xffffffffUL
  370. }
  371. };
  372. EXPORT_SYMBOL(s3c_device_spi1);
  373. /* pwm timer blocks */
  374. static struct resource s3c_timer0_resource[] = {
  375. [0] = {
  376. .start = S3C24XX_PA_TIMER + 0x0C,
  377. .end = S3C24XX_PA_TIMER + 0x0C + 0xB,
  378. .flags = IORESOURCE_MEM,
  379. },
  380. [1] = {
  381. .start = IRQ_TIMER0,
  382. .end = IRQ_TIMER0,
  383. .flags = IORESOURCE_IRQ,
  384. }
  385. };
  386. struct platform_device s3c_device_timer0 = {
  387. .name = "s3c2410-timer",
  388. .id = 0,
  389. .num_resources = ARRAY_SIZE(s3c_timer0_resource),
  390. .resource = s3c_timer0_resource,
  391. };
  392. EXPORT_SYMBOL(s3c_device_timer0);
  393. /* timer 1 */
  394. static struct resource s3c_timer1_resource[] = {
  395. [0] = {
  396. .start = S3C24XX_PA_TIMER + 0x18,
  397. .end = S3C24XX_PA_TIMER + 0x23,
  398. .flags = IORESOURCE_MEM,
  399. },
  400. [1] = {
  401. .start = IRQ_TIMER1,
  402. .end = IRQ_TIMER1,
  403. .flags = IORESOURCE_IRQ,
  404. }
  405. };
  406. struct platform_device s3c_device_timer1 = {
  407. .name = "s3c2410-timer",
  408. .id = 1,
  409. .num_resources = ARRAY_SIZE(s3c_timer1_resource),
  410. .resource = s3c_timer1_resource,
  411. };
  412. EXPORT_SYMBOL(s3c_device_timer1);
  413. /* timer 2 */
  414. static struct resource s3c_timer2_resource[] = {
  415. [0] = {
  416. .start = S3C24XX_PA_TIMER + 0x24,
  417. .end = S3C24XX_PA_TIMER + 0x2F,
  418. .flags = IORESOURCE_MEM,
  419. },
  420. [1] = {
  421. .start = IRQ_TIMER2,
  422. .end = IRQ_TIMER2,
  423. .flags = IORESOURCE_IRQ,
  424. }
  425. };
  426. struct platform_device s3c_device_timer2 = {
  427. .name = "s3c2410-timer",
  428. .id = 2,
  429. .num_resources = ARRAY_SIZE(s3c_timer2_resource),
  430. .resource = s3c_timer2_resource,
  431. };
  432. EXPORT_SYMBOL(s3c_device_timer2);
  433. /* timer 3 */
  434. static struct resource s3c_timer3_resource[] = {
  435. [0] = {
  436. .start = S3C24XX_PA_TIMER + 0x30,
  437. .end = S3C24XX_PA_TIMER + 0x3B,
  438. .flags = IORESOURCE_MEM,
  439. },
  440. [1] = {
  441. .start = IRQ_TIMER3,
  442. .end = IRQ_TIMER3,
  443. .flags = IORESOURCE_IRQ,
  444. }
  445. };
  446. struct platform_device s3c_device_timer3 = {
  447. .name = "s3c2410-timer",
  448. .id = 3,
  449. .num_resources = ARRAY_SIZE(s3c_timer3_resource),
  450. .resource = s3c_timer3_resource,
  451. };
  452. EXPORT_SYMBOL(s3c_device_timer3);
  453. #ifdef CONFIG_CPU_S3C2440
  454. /* Camif Controller */
  455. static struct resource s3c_camif_resource[] = {
  456. [0] = {
  457. .start = S3C2440_PA_CAMIF,
  458. .end = S3C2440_PA_CAMIF + S3C2440_SZ_CAMIF - 1,
  459. .flags = IORESOURCE_MEM,
  460. },
  461. [1] = {
  462. .start = IRQ_CAM,
  463. .end = IRQ_CAM,
  464. .flags = IORESOURCE_IRQ,
  465. }
  466. };
  467. static u64 s3c_device_camif_dmamask = 0xffffffffUL;
  468. struct platform_device s3c_device_camif = {
  469. .name = "s3c2440-camif",
  470. .id = -1,
  471. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  472. .resource = s3c_camif_resource,
  473. .dev = {
  474. .dma_mask = &s3c_device_camif_dmamask,
  475. .coherent_dma_mask = 0xffffffffUL
  476. }
  477. };
  478. EXPORT_SYMBOL(s3c_device_camif);
  479. #endif // CONFIG_CPU_S32440