t4_hw.c 111 KB

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  1. /*
  2. * This file is part of the Chelsio T4 Ethernet driver for Linux.
  3. *
  4. * Copyright (c) 2003-2010 Chelsio Communications, Inc. All rights reserved.
  5. *
  6. * This software is available to you under a choice of one of two
  7. * licenses. You may choose to be licensed under the terms of the GNU
  8. * General Public License (GPL) Version 2, available from the file
  9. * COPYING in the main directory of this source tree, or the
  10. * OpenIB.org BSD license below:
  11. *
  12. * Redistribution and use in source and binary forms, with or
  13. * without modification, are permitted provided that the following
  14. * conditions are met:
  15. *
  16. * - Redistributions of source code must retain the above
  17. * copyright notice, this list of conditions and the following
  18. * disclaimer.
  19. *
  20. * - Redistributions in binary form must reproduce the above
  21. * copyright notice, this list of conditions and the following
  22. * disclaimer in the documentation and/or other materials
  23. * provided with the distribution.
  24. *
  25. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32. * SOFTWARE.
  33. */
  34. #include <linux/init.h>
  35. #include <linux/delay.h>
  36. #include "cxgb4.h"
  37. #include "t4_regs.h"
  38. #include "t4fw_api.h"
  39. /**
  40. * t4_wait_op_done_val - wait until an operation is completed
  41. * @adapter: the adapter performing the operation
  42. * @reg: the register to check for completion
  43. * @mask: a single-bit field within @reg that indicates completion
  44. * @polarity: the value of the field when the operation is completed
  45. * @attempts: number of check iterations
  46. * @delay: delay in usecs between iterations
  47. * @valp: where to store the value of the register at completion time
  48. *
  49. * Wait until an operation is completed by checking a bit in a register
  50. * up to @attempts times. If @valp is not NULL the value of the register
  51. * at the time it indicated completion is stored there. Returns 0 if the
  52. * operation completes and -EAGAIN otherwise.
  53. */
  54. static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  55. int polarity, int attempts, int delay, u32 *valp)
  56. {
  57. while (1) {
  58. u32 val = t4_read_reg(adapter, reg);
  59. if (!!(val & mask) == polarity) {
  60. if (valp)
  61. *valp = val;
  62. return 0;
  63. }
  64. if (--attempts == 0)
  65. return -EAGAIN;
  66. if (delay)
  67. udelay(delay);
  68. }
  69. }
  70. static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  71. int polarity, int attempts, int delay)
  72. {
  73. return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  74. delay, NULL);
  75. }
  76. /**
  77. * t4_set_reg_field - set a register field to a value
  78. * @adapter: the adapter to program
  79. * @addr: the register address
  80. * @mask: specifies the portion of the register to modify
  81. * @val: the new value for the register field
  82. *
  83. * Sets a register field specified by the supplied mask to the
  84. * given value.
  85. */
  86. void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  87. u32 val)
  88. {
  89. u32 v = t4_read_reg(adapter, addr) & ~mask;
  90. t4_write_reg(adapter, addr, v | val);
  91. (void) t4_read_reg(adapter, addr); /* flush */
  92. }
  93. /**
  94. * t4_read_indirect - read indirectly addressed registers
  95. * @adap: the adapter
  96. * @addr_reg: register holding the indirect address
  97. * @data_reg: register holding the value of the indirect register
  98. * @vals: where the read register values are stored
  99. * @nregs: how many indirect registers to read
  100. * @start_idx: index of first indirect register to read
  101. *
  102. * Reads registers that are accessed indirectly through an address/data
  103. * register pair.
  104. */
  105. void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
  106. unsigned int data_reg, u32 *vals,
  107. unsigned int nregs, unsigned int start_idx)
  108. {
  109. while (nregs--) {
  110. t4_write_reg(adap, addr_reg, start_idx);
  111. *vals++ = t4_read_reg(adap, data_reg);
  112. start_idx++;
  113. }
  114. }
  115. /**
  116. * t4_write_indirect - write indirectly addressed registers
  117. * @adap: the adapter
  118. * @addr_reg: register holding the indirect addresses
  119. * @data_reg: register holding the value for the indirect registers
  120. * @vals: values to write
  121. * @nregs: how many indirect registers to write
  122. * @start_idx: address of first indirect register to write
  123. *
  124. * Writes a sequential block of registers that are accessed indirectly
  125. * through an address/data register pair.
  126. */
  127. void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
  128. unsigned int data_reg, const u32 *vals,
  129. unsigned int nregs, unsigned int start_idx)
  130. {
  131. while (nregs--) {
  132. t4_write_reg(adap, addr_reg, start_idx++);
  133. t4_write_reg(adap, data_reg, *vals++);
  134. }
  135. }
  136. /*
  137. * Get the reply to a mailbox command and store it in @rpl in big-endian order.
  138. */
  139. static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
  140. u32 mbox_addr)
  141. {
  142. for ( ; nflit; nflit--, mbox_addr += 8)
  143. *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
  144. }
  145. /*
  146. * Handle a FW assertion reported in a mailbox.
  147. */
  148. static void fw_asrt(struct adapter *adap, u32 mbox_addr)
  149. {
  150. struct fw_debug_cmd asrt;
  151. get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
  152. dev_alert(adap->pdev_dev,
  153. "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
  154. asrt.u.assert.filename_0_7, ntohl(asrt.u.assert.line),
  155. ntohl(asrt.u.assert.x), ntohl(asrt.u.assert.y));
  156. }
  157. static void dump_mbox(struct adapter *adap, int mbox, u32 data_reg)
  158. {
  159. dev_err(adap->pdev_dev,
  160. "mbox %d: %llx %llx %llx %llx %llx %llx %llx %llx\n", mbox,
  161. (unsigned long long)t4_read_reg64(adap, data_reg),
  162. (unsigned long long)t4_read_reg64(adap, data_reg + 8),
  163. (unsigned long long)t4_read_reg64(adap, data_reg + 16),
  164. (unsigned long long)t4_read_reg64(adap, data_reg + 24),
  165. (unsigned long long)t4_read_reg64(adap, data_reg + 32),
  166. (unsigned long long)t4_read_reg64(adap, data_reg + 40),
  167. (unsigned long long)t4_read_reg64(adap, data_reg + 48),
  168. (unsigned long long)t4_read_reg64(adap, data_reg + 56));
  169. }
  170. /**
  171. * t4_wr_mbox_meat - send a command to FW through the given mailbox
  172. * @adap: the adapter
  173. * @mbox: index of the mailbox to use
  174. * @cmd: the command to write
  175. * @size: command length in bytes
  176. * @rpl: where to optionally store the reply
  177. * @sleep_ok: if true we may sleep while awaiting command completion
  178. *
  179. * Sends the given command to FW through the selected mailbox and waits
  180. * for the FW to execute the command. If @rpl is not %NULL it is used to
  181. * store the FW's reply to the command. The command and its optional
  182. * reply are of the same length. FW can take up to %FW_CMD_MAX_TIMEOUT ms
  183. * to respond. @sleep_ok determines whether we may sleep while awaiting
  184. * the response. If sleeping is allowed we use progressive backoff
  185. * otherwise we spin.
  186. *
  187. * The return value is 0 on success or a negative errno on failure. A
  188. * failure can happen either because we are not able to execute the
  189. * command or FW executes it but signals an error. In the latter case
  190. * the return value is the error code indicated by FW (negated).
  191. */
  192. int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
  193. void *rpl, bool sleep_ok)
  194. {
  195. static const int delay[] = {
  196. 1, 1, 3, 5, 10, 10, 20, 50, 100, 200
  197. };
  198. u32 v;
  199. u64 res;
  200. int i, ms, delay_idx;
  201. const __be64 *p = cmd;
  202. u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA);
  203. u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL);
  204. if ((size & 15) || size > MBOX_LEN)
  205. return -EINVAL;
  206. /*
  207. * If the device is off-line, as in EEH, commands will time out.
  208. * Fail them early so we don't waste time waiting.
  209. */
  210. if (adap->pdev->error_state != pci_channel_io_normal)
  211. return -EIO;
  212. v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
  213. for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
  214. v = MBOWNER_GET(t4_read_reg(adap, ctl_reg));
  215. if (v != MBOX_OWNER_DRV)
  216. return v ? -EBUSY : -ETIMEDOUT;
  217. for (i = 0; i < size; i += 8)
  218. t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
  219. t4_write_reg(adap, ctl_reg, MBMSGVALID | MBOWNER(MBOX_OWNER_FW));
  220. t4_read_reg(adap, ctl_reg); /* flush write */
  221. delay_idx = 0;
  222. ms = delay[0];
  223. for (i = 0; i < FW_CMD_MAX_TIMEOUT; i += ms) {
  224. if (sleep_ok) {
  225. ms = delay[delay_idx]; /* last element may repeat */
  226. if (delay_idx < ARRAY_SIZE(delay) - 1)
  227. delay_idx++;
  228. msleep(ms);
  229. } else
  230. mdelay(ms);
  231. v = t4_read_reg(adap, ctl_reg);
  232. if (MBOWNER_GET(v) == MBOX_OWNER_DRV) {
  233. if (!(v & MBMSGVALID)) {
  234. t4_write_reg(adap, ctl_reg, 0);
  235. continue;
  236. }
  237. res = t4_read_reg64(adap, data_reg);
  238. if (FW_CMD_OP_GET(res >> 32) == FW_DEBUG_CMD) {
  239. fw_asrt(adap, data_reg);
  240. res = FW_CMD_RETVAL(EIO);
  241. } else if (rpl)
  242. get_mbox_rpl(adap, rpl, size / 8, data_reg);
  243. if (FW_CMD_RETVAL_GET((int)res))
  244. dump_mbox(adap, mbox, data_reg);
  245. t4_write_reg(adap, ctl_reg, 0);
  246. return -FW_CMD_RETVAL_GET((int)res);
  247. }
  248. }
  249. dump_mbox(adap, mbox, data_reg);
  250. dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
  251. *(const u8 *)cmd, mbox);
  252. return -ETIMEDOUT;
  253. }
  254. /**
  255. * t4_mc_read - read from MC through backdoor accesses
  256. * @adap: the adapter
  257. * @addr: address of first byte requested
  258. * @data: 64 bytes of data containing the requested address
  259. * @ecc: where to store the corresponding 64-bit ECC word
  260. *
  261. * Read 64 bytes of data from MC starting at a 64-byte-aligned address
  262. * that covers the requested address @addr. If @parity is not %NULL it
  263. * is assigned the 64-bit ECC word for the read data.
  264. */
  265. int t4_mc_read(struct adapter *adap, u32 addr, __be32 *data, u64 *ecc)
  266. {
  267. int i;
  268. if (t4_read_reg(adap, MC_BIST_CMD) & START_BIST)
  269. return -EBUSY;
  270. t4_write_reg(adap, MC_BIST_CMD_ADDR, addr & ~0x3fU);
  271. t4_write_reg(adap, MC_BIST_CMD_LEN, 64);
  272. t4_write_reg(adap, MC_BIST_DATA_PATTERN, 0xc);
  273. t4_write_reg(adap, MC_BIST_CMD, BIST_OPCODE(1) | START_BIST |
  274. BIST_CMD_GAP(1));
  275. i = t4_wait_op_done(adap, MC_BIST_CMD, START_BIST, 0, 10, 1);
  276. if (i)
  277. return i;
  278. #define MC_DATA(i) MC_BIST_STATUS_REG(MC_BIST_STATUS_RDATA, i)
  279. for (i = 15; i >= 0; i--)
  280. *data++ = htonl(t4_read_reg(adap, MC_DATA(i)));
  281. if (ecc)
  282. *ecc = t4_read_reg64(adap, MC_DATA(16));
  283. #undef MC_DATA
  284. return 0;
  285. }
  286. /**
  287. * t4_edc_read - read from EDC through backdoor accesses
  288. * @adap: the adapter
  289. * @idx: which EDC to access
  290. * @addr: address of first byte requested
  291. * @data: 64 bytes of data containing the requested address
  292. * @ecc: where to store the corresponding 64-bit ECC word
  293. *
  294. * Read 64 bytes of data from EDC starting at a 64-byte-aligned address
  295. * that covers the requested address @addr. If @parity is not %NULL it
  296. * is assigned the 64-bit ECC word for the read data.
  297. */
  298. int t4_edc_read(struct adapter *adap, int idx, u32 addr, __be32 *data, u64 *ecc)
  299. {
  300. int i;
  301. idx *= EDC_STRIDE;
  302. if (t4_read_reg(adap, EDC_BIST_CMD + idx) & START_BIST)
  303. return -EBUSY;
  304. t4_write_reg(adap, EDC_BIST_CMD_ADDR + idx, addr & ~0x3fU);
  305. t4_write_reg(adap, EDC_BIST_CMD_LEN + idx, 64);
  306. t4_write_reg(adap, EDC_BIST_DATA_PATTERN + idx, 0xc);
  307. t4_write_reg(adap, EDC_BIST_CMD + idx,
  308. BIST_OPCODE(1) | BIST_CMD_GAP(1) | START_BIST);
  309. i = t4_wait_op_done(adap, EDC_BIST_CMD + idx, START_BIST, 0, 10, 1);
  310. if (i)
  311. return i;
  312. #define EDC_DATA(i) (EDC_BIST_STATUS_REG(EDC_BIST_STATUS_RDATA, i) + idx)
  313. for (i = 15; i >= 0; i--)
  314. *data++ = htonl(t4_read_reg(adap, EDC_DATA(i)));
  315. if (ecc)
  316. *ecc = t4_read_reg64(adap, EDC_DATA(16));
  317. #undef EDC_DATA
  318. return 0;
  319. }
  320. /*
  321. * t4_mem_win_rw - read/write memory through PCIE memory window
  322. * @adap: the adapter
  323. * @addr: address of first byte requested
  324. * @data: MEMWIN0_APERTURE bytes of data containing the requested address
  325. * @dir: direction of transfer 1 => read, 0 => write
  326. *
  327. * Read/write MEMWIN0_APERTURE bytes of data from MC starting at a
  328. * MEMWIN0_APERTURE-byte-aligned address that covers the requested
  329. * address @addr.
  330. */
  331. static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
  332. {
  333. int i;
  334. /*
  335. * Setup offset into PCIE memory window. Address must be a
  336. * MEMWIN0_APERTURE-byte-aligned address. (Read back MA register to
  337. * ensure that changes propagate before we attempt to use the new
  338. * values.)
  339. */
  340. t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET,
  341. addr & ~(MEMWIN0_APERTURE - 1));
  342. t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
  343. /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */
  344. for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) {
  345. if (dir)
  346. *data++ = (__force __be32) t4_read_reg(adap,
  347. (MEMWIN0_BASE + i));
  348. else
  349. t4_write_reg(adap, (MEMWIN0_BASE + i),
  350. (__force u32) *data++);
  351. }
  352. return 0;
  353. }
  354. /**
  355. * t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
  356. * @adap: the adapter
  357. * @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
  358. * @addr: address within indicated memory type
  359. * @len: amount of memory to transfer
  360. * @buf: host memory buffer
  361. * @dir: direction of transfer 1 => read, 0 => write
  362. *
  363. * Reads/writes an [almost] arbitrary memory region in the firmware: the
  364. * firmware memory address, length and host buffer must be aligned on
  365. * 32-bit boudaries. The memory is transferred as a raw byte sequence
  366. * from/to the firmware's memory. If this memory contains data
  367. * structures which contain multi-byte integers, it's the callers
  368. * responsibility to perform appropriate byte order conversions.
  369. */
  370. static int t4_memory_rw(struct adapter *adap, int mtype, u32 addr, u32 len,
  371. __be32 *buf, int dir)
  372. {
  373. u32 pos, start, end, offset, memoffset;
  374. int ret = 0;
  375. __be32 *data;
  376. /*
  377. * Argument sanity checks ...
  378. */
  379. if ((addr & 0x3) || (len & 0x3))
  380. return -EINVAL;
  381. data = vmalloc(MEMWIN0_APERTURE);
  382. if (!data)
  383. return -ENOMEM;
  384. /*
  385. * Offset into the region of memory which is being accessed
  386. * MEM_EDC0 = 0
  387. * MEM_EDC1 = 1
  388. * MEM_MC = 2
  389. */
  390. memoffset = (mtype * (5 * 1024 * 1024));
  391. /* Determine the PCIE_MEM_ACCESS_OFFSET */
  392. addr = addr + memoffset;
  393. /*
  394. * The underlaying EDC/MC read routines read MEMWIN0_APERTURE bytes
  395. * at a time so we need to round down the start and round up the end.
  396. * We'll start copying out of the first line at (addr - start) a word
  397. * at a time.
  398. */
  399. start = addr & ~(MEMWIN0_APERTURE-1);
  400. end = (addr + len + MEMWIN0_APERTURE-1) & ~(MEMWIN0_APERTURE-1);
  401. offset = (addr - start)/sizeof(__be32);
  402. for (pos = start; pos < end; pos += MEMWIN0_APERTURE, offset = 0) {
  403. /*
  404. * If we're writing, copy the data from the caller's memory
  405. * buffer
  406. */
  407. if (!dir) {
  408. /*
  409. * If we're doing a partial write, then we need to do
  410. * a read-modify-write ...
  411. */
  412. if (offset || len < MEMWIN0_APERTURE) {
  413. ret = t4_mem_win_rw(adap, pos, data, 1);
  414. if (ret)
  415. break;
  416. }
  417. while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
  418. len > 0) {
  419. data[offset++] = *buf++;
  420. len -= sizeof(__be32);
  421. }
  422. }
  423. /*
  424. * Transfer a block of memory and bail if there's an error.
  425. */
  426. ret = t4_mem_win_rw(adap, pos, data, dir);
  427. if (ret)
  428. break;
  429. /*
  430. * If we're reading, copy the data into the caller's memory
  431. * buffer.
  432. */
  433. if (dir)
  434. while (offset < (MEMWIN0_APERTURE/sizeof(__be32)) &&
  435. len > 0) {
  436. *buf++ = data[offset++];
  437. len -= sizeof(__be32);
  438. }
  439. }
  440. vfree(data);
  441. return ret;
  442. }
  443. int t4_memory_write(struct adapter *adap, int mtype, u32 addr, u32 len,
  444. __be32 *buf)
  445. {
  446. return t4_memory_rw(adap, mtype, addr, len, buf, 0);
  447. }
  448. #define EEPROM_STAT_ADDR 0x7bfc
  449. #define VPD_LEN 512
  450. #define VPD_BASE 0x400
  451. #define VPD_BASE_OLD 0
  452. /**
  453. * t4_seeprom_wp - enable/disable EEPROM write protection
  454. * @adapter: the adapter
  455. * @enable: whether to enable or disable write protection
  456. *
  457. * Enables or disables write protection on the serial EEPROM.
  458. */
  459. int t4_seeprom_wp(struct adapter *adapter, bool enable)
  460. {
  461. unsigned int v = enable ? 0xc : 0;
  462. int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
  463. return ret < 0 ? ret : 0;
  464. }
  465. /**
  466. * get_vpd_params - read VPD parameters from VPD EEPROM
  467. * @adapter: adapter to read
  468. * @p: where to store the parameters
  469. *
  470. * Reads card parameters stored in VPD EEPROM.
  471. */
  472. int get_vpd_params(struct adapter *adapter, struct vpd_params *p)
  473. {
  474. u32 cclk_param, cclk_val;
  475. int i, ret, addr;
  476. int ec, sn;
  477. u8 *vpd, csum;
  478. unsigned int vpdr_len, kw_offset, id_len;
  479. vpd = vmalloc(VPD_LEN);
  480. if (!vpd)
  481. return -ENOMEM;
  482. ret = pci_read_vpd(adapter->pdev, VPD_BASE, sizeof(u32), vpd);
  483. if (ret < 0)
  484. goto out;
  485. addr = *vpd == 0x82 ? VPD_BASE : VPD_BASE_OLD;
  486. ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
  487. if (ret < 0)
  488. goto out;
  489. if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
  490. dev_err(adapter->pdev_dev, "missing VPD ID string\n");
  491. ret = -EINVAL;
  492. goto out;
  493. }
  494. id_len = pci_vpd_lrdt_size(vpd);
  495. if (id_len > ID_LEN)
  496. id_len = ID_LEN;
  497. i = pci_vpd_find_tag(vpd, 0, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
  498. if (i < 0) {
  499. dev_err(adapter->pdev_dev, "missing VPD-R section\n");
  500. ret = -EINVAL;
  501. goto out;
  502. }
  503. vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
  504. kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
  505. if (vpdr_len + kw_offset > VPD_LEN) {
  506. dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
  507. ret = -EINVAL;
  508. goto out;
  509. }
  510. #define FIND_VPD_KW(var, name) do { \
  511. var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
  512. if (var < 0) { \
  513. dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
  514. ret = -EINVAL; \
  515. goto out; \
  516. } \
  517. var += PCI_VPD_INFO_FLD_HDR_SIZE; \
  518. } while (0)
  519. FIND_VPD_KW(i, "RV");
  520. for (csum = 0; i >= 0; i--)
  521. csum += vpd[i];
  522. if (csum) {
  523. dev_err(adapter->pdev_dev,
  524. "corrupted VPD EEPROM, actual csum %u\n", csum);
  525. ret = -EINVAL;
  526. goto out;
  527. }
  528. FIND_VPD_KW(ec, "EC");
  529. FIND_VPD_KW(sn, "SN");
  530. #undef FIND_VPD_KW
  531. memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
  532. strim(p->id);
  533. memcpy(p->ec, vpd + ec, EC_LEN);
  534. strim(p->ec);
  535. i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
  536. memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
  537. strim(p->sn);
  538. /*
  539. * Ask firmware for the Core Clock since it knows how to translate the
  540. * Reference Clock ('V2') VPD field into a Core Clock value ...
  541. */
  542. cclk_param = (FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
  543. FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_CCLK));
  544. ret = t4_query_params(adapter, adapter->mbox, 0, 0,
  545. 1, &cclk_param, &cclk_val);
  546. out:
  547. vfree(vpd);
  548. if (ret)
  549. return ret;
  550. p->cclk = cclk_val;
  551. return 0;
  552. }
  553. /* serial flash and firmware constants */
  554. enum {
  555. SF_ATTEMPTS = 10, /* max retries for SF operations */
  556. /* flash command opcodes */
  557. SF_PROG_PAGE = 2, /* program page */
  558. SF_WR_DISABLE = 4, /* disable writes */
  559. SF_RD_STATUS = 5, /* read status register */
  560. SF_WR_ENABLE = 6, /* enable writes */
  561. SF_RD_DATA_FAST = 0xb, /* read flash */
  562. SF_RD_ID = 0x9f, /* read ID */
  563. SF_ERASE_SECTOR = 0xd8, /* erase sector */
  564. FW_MAX_SIZE = 512 * 1024,
  565. };
  566. /**
  567. * sf1_read - read data from the serial flash
  568. * @adapter: the adapter
  569. * @byte_cnt: number of bytes to read
  570. * @cont: whether another operation will be chained
  571. * @lock: whether to lock SF for PL access only
  572. * @valp: where to store the read data
  573. *
  574. * Reads up to 4 bytes of data from the serial flash. The location of
  575. * the read needs to be specified prior to calling this by issuing the
  576. * appropriate commands to the serial flash.
  577. */
  578. static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
  579. int lock, u32 *valp)
  580. {
  581. int ret;
  582. if (!byte_cnt || byte_cnt > 4)
  583. return -EINVAL;
  584. if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
  585. return -EBUSY;
  586. cont = cont ? SF_CONT : 0;
  587. lock = lock ? SF_LOCK : 0;
  588. t4_write_reg(adapter, SF_OP, lock | cont | BYTECNT(byte_cnt - 1));
  589. ret = t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
  590. if (!ret)
  591. *valp = t4_read_reg(adapter, SF_DATA);
  592. return ret;
  593. }
  594. /**
  595. * sf1_write - write data to the serial flash
  596. * @adapter: the adapter
  597. * @byte_cnt: number of bytes to write
  598. * @cont: whether another operation will be chained
  599. * @lock: whether to lock SF for PL access only
  600. * @val: value to write
  601. *
  602. * Writes up to 4 bytes of data to the serial flash. The location of
  603. * the write needs to be specified prior to calling this by issuing the
  604. * appropriate commands to the serial flash.
  605. */
  606. static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
  607. int lock, u32 val)
  608. {
  609. if (!byte_cnt || byte_cnt > 4)
  610. return -EINVAL;
  611. if (t4_read_reg(adapter, SF_OP) & SF_BUSY)
  612. return -EBUSY;
  613. cont = cont ? SF_CONT : 0;
  614. lock = lock ? SF_LOCK : 0;
  615. t4_write_reg(adapter, SF_DATA, val);
  616. t4_write_reg(adapter, SF_OP, lock |
  617. cont | BYTECNT(byte_cnt - 1) | OP_WR);
  618. return t4_wait_op_done(adapter, SF_OP, SF_BUSY, 0, SF_ATTEMPTS, 5);
  619. }
  620. /**
  621. * flash_wait_op - wait for a flash operation to complete
  622. * @adapter: the adapter
  623. * @attempts: max number of polls of the status register
  624. * @delay: delay between polls in ms
  625. *
  626. * Wait for a flash operation to complete by polling the status register.
  627. */
  628. static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
  629. {
  630. int ret;
  631. u32 status;
  632. while (1) {
  633. if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
  634. (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
  635. return ret;
  636. if (!(status & 1))
  637. return 0;
  638. if (--attempts == 0)
  639. return -EAGAIN;
  640. if (delay)
  641. msleep(delay);
  642. }
  643. }
  644. /**
  645. * t4_read_flash - read words from serial flash
  646. * @adapter: the adapter
  647. * @addr: the start address for the read
  648. * @nwords: how many 32-bit words to read
  649. * @data: where to store the read data
  650. * @byte_oriented: whether to store data as bytes or as words
  651. *
  652. * Read the specified number of 32-bit words from the serial flash.
  653. * If @byte_oriented is set the read data is stored as a byte array
  654. * (i.e., big-endian), otherwise as 32-bit words in the platform's
  655. * natural endianess.
  656. */
  657. static int t4_read_flash(struct adapter *adapter, unsigned int addr,
  658. unsigned int nwords, u32 *data, int byte_oriented)
  659. {
  660. int ret;
  661. if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
  662. return -EINVAL;
  663. addr = swab32(addr) | SF_RD_DATA_FAST;
  664. if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
  665. (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
  666. return ret;
  667. for ( ; nwords; nwords--, data++) {
  668. ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
  669. if (nwords == 1)
  670. t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
  671. if (ret)
  672. return ret;
  673. if (byte_oriented)
  674. *data = (__force __u32) (htonl(*data));
  675. }
  676. return 0;
  677. }
  678. /**
  679. * t4_write_flash - write up to a page of data to the serial flash
  680. * @adapter: the adapter
  681. * @addr: the start address to write
  682. * @n: length of data to write in bytes
  683. * @data: the data to write
  684. *
  685. * Writes up to a page of data (256 bytes) to the serial flash starting
  686. * at the given address. All the data must be written to the same page.
  687. */
  688. static int t4_write_flash(struct adapter *adapter, unsigned int addr,
  689. unsigned int n, const u8 *data)
  690. {
  691. int ret;
  692. u32 buf[64];
  693. unsigned int i, c, left, val, offset = addr & 0xff;
  694. if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
  695. return -EINVAL;
  696. val = swab32(addr) | SF_PROG_PAGE;
  697. if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
  698. (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
  699. goto unlock;
  700. for (left = n; left; left -= c) {
  701. c = min(left, 4U);
  702. for (val = 0, i = 0; i < c; ++i)
  703. val = (val << 8) + *data++;
  704. ret = sf1_write(adapter, c, c != left, 1, val);
  705. if (ret)
  706. goto unlock;
  707. }
  708. ret = flash_wait_op(adapter, 8, 1);
  709. if (ret)
  710. goto unlock;
  711. t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
  712. /* Read the page to verify the write succeeded */
  713. ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf, 1);
  714. if (ret)
  715. return ret;
  716. if (memcmp(data - n, (u8 *)buf + offset, n)) {
  717. dev_err(adapter->pdev_dev,
  718. "failed to correctly write the flash page at %#x\n",
  719. addr);
  720. return -EIO;
  721. }
  722. return 0;
  723. unlock:
  724. t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
  725. return ret;
  726. }
  727. /**
  728. * get_fw_version - read the firmware version
  729. * @adapter: the adapter
  730. * @vers: where to place the version
  731. *
  732. * Reads the FW version from flash.
  733. */
  734. static int get_fw_version(struct adapter *adapter, u32 *vers)
  735. {
  736. return t4_read_flash(adapter, adapter->params.sf_fw_start +
  737. offsetof(struct fw_hdr, fw_ver), 1, vers, 0);
  738. }
  739. /**
  740. * get_tp_version - read the TP microcode version
  741. * @adapter: the adapter
  742. * @vers: where to place the version
  743. *
  744. * Reads the TP microcode version from flash.
  745. */
  746. static int get_tp_version(struct adapter *adapter, u32 *vers)
  747. {
  748. return t4_read_flash(adapter, adapter->params.sf_fw_start +
  749. offsetof(struct fw_hdr, tp_microcode_ver),
  750. 1, vers, 0);
  751. }
  752. /**
  753. * t4_check_fw_version - check if the FW is compatible with this driver
  754. * @adapter: the adapter
  755. *
  756. * Checks if an adapter's FW is compatible with the driver. Returns 0
  757. * if there's exact match, a negative error if the version could not be
  758. * read or there's a major version mismatch, and a positive value if the
  759. * expected major version is found but there's a minor version mismatch.
  760. */
  761. int t4_check_fw_version(struct adapter *adapter)
  762. {
  763. u32 api_vers[2];
  764. int ret, major, minor, micro;
  765. ret = get_fw_version(adapter, &adapter->params.fw_vers);
  766. if (!ret)
  767. ret = get_tp_version(adapter, &adapter->params.tp_vers);
  768. if (!ret)
  769. ret = t4_read_flash(adapter, adapter->params.sf_fw_start +
  770. offsetof(struct fw_hdr, intfver_nic),
  771. 2, api_vers, 1);
  772. if (ret)
  773. return ret;
  774. major = FW_HDR_FW_VER_MAJOR_GET(adapter->params.fw_vers);
  775. minor = FW_HDR_FW_VER_MINOR_GET(adapter->params.fw_vers);
  776. micro = FW_HDR_FW_VER_MICRO_GET(adapter->params.fw_vers);
  777. memcpy(adapter->params.api_vers, api_vers,
  778. sizeof(adapter->params.api_vers));
  779. if (major != FW_VERSION_MAJOR) { /* major mismatch - fail */
  780. dev_err(adapter->pdev_dev,
  781. "card FW has major version %u, driver wants %u\n",
  782. major, FW_VERSION_MAJOR);
  783. return -EINVAL;
  784. }
  785. if (minor == FW_VERSION_MINOR && micro == FW_VERSION_MICRO)
  786. return 0; /* perfect match */
  787. /* Minor/micro version mismatch. Report it but often it's OK. */
  788. return 1;
  789. }
  790. /**
  791. * t4_flash_erase_sectors - erase a range of flash sectors
  792. * @adapter: the adapter
  793. * @start: the first sector to erase
  794. * @end: the last sector to erase
  795. *
  796. * Erases the sectors in the given inclusive range.
  797. */
  798. static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
  799. {
  800. int ret = 0;
  801. while (start <= end) {
  802. if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
  803. (ret = sf1_write(adapter, 4, 0, 1,
  804. SF_ERASE_SECTOR | (start << 8))) != 0 ||
  805. (ret = flash_wait_op(adapter, 14, 500)) != 0) {
  806. dev_err(adapter->pdev_dev,
  807. "erase of flash sector %d failed, error %d\n",
  808. start, ret);
  809. break;
  810. }
  811. start++;
  812. }
  813. t4_write_reg(adapter, SF_OP, 0); /* unlock SF */
  814. return ret;
  815. }
  816. /**
  817. * t4_flash_cfg_addr - return the address of the flash configuration file
  818. * @adapter: the adapter
  819. *
  820. * Return the address within the flash where the Firmware Configuration
  821. * File is stored.
  822. */
  823. unsigned int t4_flash_cfg_addr(struct adapter *adapter)
  824. {
  825. if (adapter->params.sf_size == 0x100000)
  826. return FLASH_FPGA_CFG_START;
  827. else
  828. return FLASH_CFG_START;
  829. }
  830. /**
  831. * t4_load_cfg - download config file
  832. * @adap: the adapter
  833. * @cfg_data: the cfg text file to write
  834. * @size: text file size
  835. *
  836. * Write the supplied config text file to the card's serial flash.
  837. */
  838. int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size)
  839. {
  840. int ret, i, n;
  841. unsigned int addr;
  842. unsigned int flash_cfg_start_sec;
  843. unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
  844. addr = t4_flash_cfg_addr(adap);
  845. flash_cfg_start_sec = addr / SF_SEC_SIZE;
  846. if (size > FLASH_CFG_MAX_SIZE) {
  847. dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n",
  848. FLASH_CFG_MAX_SIZE);
  849. return -EFBIG;
  850. }
  851. i = DIV_ROUND_UP(FLASH_CFG_MAX_SIZE, /* # of sectors spanned */
  852. sf_sec_size);
  853. ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec,
  854. flash_cfg_start_sec + i - 1);
  855. /*
  856. * If size == 0 then we're simply erasing the FLASH sectors associated
  857. * with the on-adapter Firmware Configuration File.
  858. */
  859. if (ret || size == 0)
  860. goto out;
  861. /* this will write to the flash up to SF_PAGE_SIZE at a time */
  862. for (i = 0; i < size; i += SF_PAGE_SIZE) {
  863. if ((size - i) < SF_PAGE_SIZE)
  864. n = size - i;
  865. else
  866. n = SF_PAGE_SIZE;
  867. ret = t4_write_flash(adap, addr, n, cfg_data);
  868. if (ret)
  869. goto out;
  870. addr += SF_PAGE_SIZE;
  871. cfg_data += SF_PAGE_SIZE;
  872. }
  873. out:
  874. if (ret)
  875. dev_err(adap->pdev_dev, "config file %s failed %d\n",
  876. (size == 0 ? "clear" : "download"), ret);
  877. return ret;
  878. }
  879. /**
  880. * t4_load_fw - download firmware
  881. * @adap: the adapter
  882. * @fw_data: the firmware image to write
  883. * @size: image size
  884. *
  885. * Write the supplied firmware image to the card's serial flash.
  886. */
  887. int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
  888. {
  889. u32 csum;
  890. int ret, addr;
  891. unsigned int i;
  892. u8 first_page[SF_PAGE_SIZE];
  893. const __be32 *p = (const __be32 *)fw_data;
  894. const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
  895. unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
  896. unsigned int fw_img_start = adap->params.sf_fw_start;
  897. unsigned int fw_start_sec = fw_img_start / sf_sec_size;
  898. if (!size) {
  899. dev_err(adap->pdev_dev, "FW image has no data\n");
  900. return -EINVAL;
  901. }
  902. if (size & 511) {
  903. dev_err(adap->pdev_dev,
  904. "FW image size not multiple of 512 bytes\n");
  905. return -EINVAL;
  906. }
  907. if (ntohs(hdr->len512) * 512 != size) {
  908. dev_err(adap->pdev_dev,
  909. "FW image size differs from size in FW header\n");
  910. return -EINVAL;
  911. }
  912. if (size > FW_MAX_SIZE) {
  913. dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
  914. FW_MAX_SIZE);
  915. return -EFBIG;
  916. }
  917. for (csum = 0, i = 0; i < size / sizeof(csum); i++)
  918. csum += ntohl(p[i]);
  919. if (csum != 0xffffffff) {
  920. dev_err(adap->pdev_dev,
  921. "corrupted firmware image, checksum %#x\n", csum);
  922. return -EINVAL;
  923. }
  924. i = DIV_ROUND_UP(size, sf_sec_size); /* # of sectors spanned */
  925. ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
  926. if (ret)
  927. goto out;
  928. /*
  929. * We write the correct version at the end so the driver can see a bad
  930. * version if the FW write fails. Start by writing a copy of the
  931. * first page with a bad version.
  932. */
  933. memcpy(first_page, fw_data, SF_PAGE_SIZE);
  934. ((struct fw_hdr *)first_page)->fw_ver = htonl(0xffffffff);
  935. ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page);
  936. if (ret)
  937. goto out;
  938. addr = fw_img_start;
  939. for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
  940. addr += SF_PAGE_SIZE;
  941. fw_data += SF_PAGE_SIZE;
  942. ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data);
  943. if (ret)
  944. goto out;
  945. }
  946. ret = t4_write_flash(adap,
  947. fw_img_start + offsetof(struct fw_hdr, fw_ver),
  948. sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver);
  949. out:
  950. if (ret)
  951. dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
  952. ret);
  953. return ret;
  954. }
  955. #define ADVERT_MASK (FW_PORT_CAP_SPEED_100M | FW_PORT_CAP_SPEED_1G |\
  956. FW_PORT_CAP_SPEED_10G | FW_PORT_CAP_ANEG)
  957. /**
  958. * t4_link_start - apply link configuration to MAC/PHY
  959. * @phy: the PHY to setup
  960. * @mac: the MAC to setup
  961. * @lc: the requested link configuration
  962. *
  963. * Set up a port's MAC and PHY according to a desired link configuration.
  964. * - If the PHY can auto-negotiate first decide what to advertise, then
  965. * enable/disable auto-negotiation as desired, and reset.
  966. * - If the PHY does not auto-negotiate just reset it.
  967. * - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
  968. * otherwise do it later based on the outcome of auto-negotiation.
  969. */
  970. int t4_link_start(struct adapter *adap, unsigned int mbox, unsigned int port,
  971. struct link_config *lc)
  972. {
  973. struct fw_port_cmd c;
  974. unsigned int fc = 0, mdi = FW_PORT_MDI(FW_PORT_MDI_AUTO);
  975. lc->link_ok = 0;
  976. if (lc->requested_fc & PAUSE_RX)
  977. fc |= FW_PORT_CAP_FC_RX;
  978. if (lc->requested_fc & PAUSE_TX)
  979. fc |= FW_PORT_CAP_FC_TX;
  980. memset(&c, 0, sizeof(c));
  981. c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
  982. FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
  983. c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
  984. FW_LEN16(c));
  985. if (!(lc->supported & FW_PORT_CAP_ANEG)) {
  986. c.u.l1cfg.rcap = htonl((lc->supported & ADVERT_MASK) | fc);
  987. lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
  988. } else if (lc->autoneg == AUTONEG_DISABLE) {
  989. c.u.l1cfg.rcap = htonl(lc->requested_speed | fc | mdi);
  990. lc->fc = lc->requested_fc & (PAUSE_RX | PAUSE_TX);
  991. } else
  992. c.u.l1cfg.rcap = htonl(lc->advertising | fc | mdi);
  993. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  994. }
  995. /**
  996. * t4_restart_aneg - restart autonegotiation
  997. * @adap: the adapter
  998. * @mbox: mbox to use for the FW command
  999. * @port: the port id
  1000. *
  1001. * Restarts autonegotiation for the selected port.
  1002. */
  1003. int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
  1004. {
  1005. struct fw_port_cmd c;
  1006. memset(&c, 0, sizeof(c));
  1007. c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) | FW_CMD_REQUEST |
  1008. FW_CMD_EXEC | FW_PORT_CMD_PORTID(port));
  1009. c.action_to_len16 = htonl(FW_PORT_CMD_ACTION(FW_PORT_ACTION_L1_CFG) |
  1010. FW_LEN16(c));
  1011. c.u.l1cfg.rcap = htonl(FW_PORT_CAP_ANEG);
  1012. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  1013. }
  1014. typedef void (*int_handler_t)(struct adapter *adap);
  1015. struct intr_info {
  1016. unsigned int mask; /* bits to check in interrupt status */
  1017. const char *msg; /* message to print or NULL */
  1018. short stat_idx; /* stat counter to increment or -1 */
  1019. unsigned short fatal; /* whether the condition reported is fatal */
  1020. int_handler_t int_handler; /* platform-specific int handler */
  1021. };
  1022. /**
  1023. * t4_handle_intr_status - table driven interrupt handler
  1024. * @adapter: the adapter that generated the interrupt
  1025. * @reg: the interrupt status register to process
  1026. * @acts: table of interrupt actions
  1027. *
  1028. * A table driven interrupt handler that applies a set of masks to an
  1029. * interrupt status word and performs the corresponding actions if the
  1030. * interrupts described by the mask have occurred. The actions include
  1031. * optionally emitting a warning or alert message. The table is terminated
  1032. * by an entry specifying mask 0. Returns the number of fatal interrupt
  1033. * conditions.
  1034. */
  1035. static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
  1036. const struct intr_info *acts)
  1037. {
  1038. int fatal = 0;
  1039. unsigned int mask = 0;
  1040. unsigned int status = t4_read_reg(adapter, reg);
  1041. for ( ; acts->mask; ++acts) {
  1042. if (!(status & acts->mask))
  1043. continue;
  1044. if (acts->fatal) {
  1045. fatal++;
  1046. dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
  1047. status & acts->mask);
  1048. } else if (acts->msg && printk_ratelimit())
  1049. dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
  1050. status & acts->mask);
  1051. if (acts->int_handler)
  1052. acts->int_handler(adapter);
  1053. mask |= acts->mask;
  1054. }
  1055. status &= mask;
  1056. if (status) /* clear processed interrupts */
  1057. t4_write_reg(adapter, reg, status);
  1058. return fatal;
  1059. }
  1060. /*
  1061. * Interrupt handler for the PCIE module.
  1062. */
  1063. static void pcie_intr_handler(struct adapter *adapter)
  1064. {
  1065. static const struct intr_info sysbus_intr_info[] = {
  1066. { RNPP, "RXNP array parity error", -1, 1 },
  1067. { RPCP, "RXPC array parity error", -1, 1 },
  1068. { RCIP, "RXCIF array parity error", -1, 1 },
  1069. { RCCP, "Rx completions control array parity error", -1, 1 },
  1070. { RFTP, "RXFT array parity error", -1, 1 },
  1071. { 0 }
  1072. };
  1073. static const struct intr_info pcie_port_intr_info[] = {
  1074. { TPCP, "TXPC array parity error", -1, 1 },
  1075. { TNPP, "TXNP array parity error", -1, 1 },
  1076. { TFTP, "TXFT array parity error", -1, 1 },
  1077. { TCAP, "TXCA array parity error", -1, 1 },
  1078. { TCIP, "TXCIF array parity error", -1, 1 },
  1079. { RCAP, "RXCA array parity error", -1, 1 },
  1080. { OTDD, "outbound request TLP discarded", -1, 1 },
  1081. { RDPE, "Rx data parity error", -1, 1 },
  1082. { TDUE, "Tx uncorrectable data error", -1, 1 },
  1083. { 0 }
  1084. };
  1085. static const struct intr_info pcie_intr_info[] = {
  1086. { MSIADDRLPERR, "MSI AddrL parity error", -1, 1 },
  1087. { MSIADDRHPERR, "MSI AddrH parity error", -1, 1 },
  1088. { MSIDATAPERR, "MSI data parity error", -1, 1 },
  1089. { MSIXADDRLPERR, "MSI-X AddrL parity error", -1, 1 },
  1090. { MSIXADDRHPERR, "MSI-X AddrH parity error", -1, 1 },
  1091. { MSIXDATAPERR, "MSI-X data parity error", -1, 1 },
  1092. { MSIXDIPERR, "MSI-X DI parity error", -1, 1 },
  1093. { PIOCPLPERR, "PCI PIO completion FIFO parity error", -1, 1 },
  1094. { PIOREQPERR, "PCI PIO request FIFO parity error", -1, 1 },
  1095. { TARTAGPERR, "PCI PCI target tag FIFO parity error", -1, 1 },
  1096. { CCNTPERR, "PCI CMD channel count parity error", -1, 1 },
  1097. { CREQPERR, "PCI CMD channel request parity error", -1, 1 },
  1098. { CRSPPERR, "PCI CMD channel response parity error", -1, 1 },
  1099. { DCNTPERR, "PCI DMA channel count parity error", -1, 1 },
  1100. { DREQPERR, "PCI DMA channel request parity error", -1, 1 },
  1101. { DRSPPERR, "PCI DMA channel response parity error", -1, 1 },
  1102. { HCNTPERR, "PCI HMA channel count parity error", -1, 1 },
  1103. { HREQPERR, "PCI HMA channel request parity error", -1, 1 },
  1104. { HRSPPERR, "PCI HMA channel response parity error", -1, 1 },
  1105. { CFGSNPPERR, "PCI config snoop FIFO parity error", -1, 1 },
  1106. { FIDPERR, "PCI FID parity error", -1, 1 },
  1107. { INTXCLRPERR, "PCI INTx clear parity error", -1, 1 },
  1108. { MATAGPERR, "PCI MA tag parity error", -1, 1 },
  1109. { PIOTAGPERR, "PCI PIO tag parity error", -1, 1 },
  1110. { RXCPLPERR, "PCI Rx completion parity error", -1, 1 },
  1111. { RXWRPERR, "PCI Rx write parity error", -1, 1 },
  1112. { RPLPERR, "PCI replay buffer parity error", -1, 1 },
  1113. { PCIESINT, "PCI core secondary fault", -1, 1 },
  1114. { PCIEPINT, "PCI core primary fault", -1, 1 },
  1115. { UNXSPLCPLERR, "PCI unexpected split completion error", -1, 0 },
  1116. { 0 }
  1117. };
  1118. int fat;
  1119. fat = t4_handle_intr_status(adapter,
  1120. PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS,
  1121. sysbus_intr_info) +
  1122. t4_handle_intr_status(adapter,
  1123. PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS,
  1124. pcie_port_intr_info) +
  1125. t4_handle_intr_status(adapter, PCIE_INT_CAUSE, pcie_intr_info);
  1126. if (fat)
  1127. t4_fatal_err(adapter);
  1128. }
  1129. /*
  1130. * TP interrupt handler.
  1131. */
  1132. static void tp_intr_handler(struct adapter *adapter)
  1133. {
  1134. static const struct intr_info tp_intr_info[] = {
  1135. { 0x3fffffff, "TP parity error", -1, 1 },
  1136. { FLMTXFLSTEMPTY, "TP out of Tx pages", -1, 1 },
  1137. { 0 }
  1138. };
  1139. if (t4_handle_intr_status(adapter, TP_INT_CAUSE, tp_intr_info))
  1140. t4_fatal_err(adapter);
  1141. }
  1142. /*
  1143. * SGE interrupt handler.
  1144. */
  1145. static void sge_intr_handler(struct adapter *adapter)
  1146. {
  1147. u64 v;
  1148. static const struct intr_info sge_intr_info[] = {
  1149. { ERR_CPL_EXCEED_IQE_SIZE,
  1150. "SGE received CPL exceeding IQE size", -1, 1 },
  1151. { ERR_INVALID_CIDX_INC,
  1152. "SGE GTS CIDX increment too large", -1, 0 },
  1153. { ERR_CPL_OPCODE_0, "SGE received 0-length CPL", -1, 0 },
  1154. { DBFIFO_LP_INT, NULL, -1, 0, t4_db_full },
  1155. { DBFIFO_HP_INT, NULL, -1, 0, t4_db_full },
  1156. { ERR_DROPPED_DB, NULL, -1, 0, t4_db_dropped },
  1157. { ERR_DATA_CPL_ON_HIGH_QID1 | ERR_DATA_CPL_ON_HIGH_QID0,
  1158. "SGE IQID > 1023 received CPL for FL", -1, 0 },
  1159. { ERR_BAD_DB_PIDX3, "SGE DBP 3 pidx increment too large", -1,
  1160. 0 },
  1161. { ERR_BAD_DB_PIDX2, "SGE DBP 2 pidx increment too large", -1,
  1162. 0 },
  1163. { ERR_BAD_DB_PIDX1, "SGE DBP 1 pidx increment too large", -1,
  1164. 0 },
  1165. { ERR_BAD_DB_PIDX0, "SGE DBP 0 pidx increment too large", -1,
  1166. 0 },
  1167. { ERR_ING_CTXT_PRIO,
  1168. "SGE too many priority ingress contexts", -1, 0 },
  1169. { ERR_EGR_CTXT_PRIO,
  1170. "SGE too many priority egress contexts", -1, 0 },
  1171. { INGRESS_SIZE_ERR, "SGE illegal ingress QID", -1, 0 },
  1172. { EGRESS_SIZE_ERR, "SGE illegal egress QID", -1, 0 },
  1173. { 0 }
  1174. };
  1175. v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1) |
  1176. ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2) << 32);
  1177. if (v) {
  1178. dev_alert(adapter->pdev_dev, "SGE parity error (%#llx)\n",
  1179. (unsigned long long)v);
  1180. t4_write_reg(adapter, SGE_INT_CAUSE1, v);
  1181. t4_write_reg(adapter, SGE_INT_CAUSE2, v >> 32);
  1182. }
  1183. if (t4_handle_intr_status(adapter, SGE_INT_CAUSE3, sge_intr_info) ||
  1184. v != 0)
  1185. t4_fatal_err(adapter);
  1186. }
  1187. /*
  1188. * CIM interrupt handler.
  1189. */
  1190. static void cim_intr_handler(struct adapter *adapter)
  1191. {
  1192. static const struct intr_info cim_intr_info[] = {
  1193. { PREFDROPINT, "CIM control register prefetch drop", -1, 1 },
  1194. { OBQPARERR, "CIM OBQ parity error", -1, 1 },
  1195. { IBQPARERR, "CIM IBQ parity error", -1, 1 },
  1196. { MBUPPARERR, "CIM mailbox uP parity error", -1, 1 },
  1197. { MBHOSTPARERR, "CIM mailbox host parity error", -1, 1 },
  1198. { TIEQINPARERRINT, "CIM TIEQ outgoing parity error", -1, 1 },
  1199. { TIEQOUTPARERRINT, "CIM TIEQ incoming parity error", -1, 1 },
  1200. { 0 }
  1201. };
  1202. static const struct intr_info cim_upintr_info[] = {
  1203. { RSVDSPACEINT, "CIM reserved space access", -1, 1 },
  1204. { ILLTRANSINT, "CIM illegal transaction", -1, 1 },
  1205. { ILLWRINT, "CIM illegal write", -1, 1 },
  1206. { ILLRDINT, "CIM illegal read", -1, 1 },
  1207. { ILLRDBEINT, "CIM illegal read BE", -1, 1 },
  1208. { ILLWRBEINT, "CIM illegal write BE", -1, 1 },
  1209. { SGLRDBOOTINT, "CIM single read from boot space", -1, 1 },
  1210. { SGLWRBOOTINT, "CIM single write to boot space", -1, 1 },
  1211. { BLKWRBOOTINT, "CIM block write to boot space", -1, 1 },
  1212. { SGLRDFLASHINT, "CIM single read from flash space", -1, 1 },
  1213. { SGLWRFLASHINT, "CIM single write to flash space", -1, 1 },
  1214. { BLKWRFLASHINT, "CIM block write to flash space", -1, 1 },
  1215. { SGLRDEEPROMINT, "CIM single EEPROM read", -1, 1 },
  1216. { SGLWREEPROMINT, "CIM single EEPROM write", -1, 1 },
  1217. { BLKRDEEPROMINT, "CIM block EEPROM read", -1, 1 },
  1218. { BLKWREEPROMINT, "CIM block EEPROM write", -1, 1 },
  1219. { SGLRDCTLINT , "CIM single read from CTL space", -1, 1 },
  1220. { SGLWRCTLINT , "CIM single write to CTL space", -1, 1 },
  1221. { BLKRDCTLINT , "CIM block read from CTL space", -1, 1 },
  1222. { BLKWRCTLINT , "CIM block write to CTL space", -1, 1 },
  1223. { SGLRDPLINT , "CIM single read from PL space", -1, 1 },
  1224. { SGLWRPLINT , "CIM single write to PL space", -1, 1 },
  1225. { BLKRDPLINT , "CIM block read from PL space", -1, 1 },
  1226. { BLKWRPLINT , "CIM block write to PL space", -1, 1 },
  1227. { REQOVRLOOKUPINT , "CIM request FIFO overwrite", -1, 1 },
  1228. { RSPOVRLOOKUPINT , "CIM response FIFO overwrite", -1, 1 },
  1229. { TIMEOUTINT , "CIM PIF timeout", -1, 1 },
  1230. { TIMEOUTMAINT , "CIM PIF MA timeout", -1, 1 },
  1231. { 0 }
  1232. };
  1233. int fat;
  1234. fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE,
  1235. cim_intr_info) +
  1236. t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE,
  1237. cim_upintr_info);
  1238. if (fat)
  1239. t4_fatal_err(adapter);
  1240. }
  1241. /*
  1242. * ULP RX interrupt handler.
  1243. */
  1244. static void ulprx_intr_handler(struct adapter *adapter)
  1245. {
  1246. static const struct intr_info ulprx_intr_info[] = {
  1247. { 0x1800000, "ULPRX context error", -1, 1 },
  1248. { 0x7fffff, "ULPRX parity error", -1, 1 },
  1249. { 0 }
  1250. };
  1251. if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE, ulprx_intr_info))
  1252. t4_fatal_err(adapter);
  1253. }
  1254. /*
  1255. * ULP TX interrupt handler.
  1256. */
  1257. static void ulptx_intr_handler(struct adapter *adapter)
  1258. {
  1259. static const struct intr_info ulptx_intr_info[] = {
  1260. { PBL_BOUND_ERR_CH3, "ULPTX channel 3 PBL out of bounds", -1,
  1261. 0 },
  1262. { PBL_BOUND_ERR_CH2, "ULPTX channel 2 PBL out of bounds", -1,
  1263. 0 },
  1264. { PBL_BOUND_ERR_CH1, "ULPTX channel 1 PBL out of bounds", -1,
  1265. 0 },
  1266. { PBL_BOUND_ERR_CH0, "ULPTX channel 0 PBL out of bounds", -1,
  1267. 0 },
  1268. { 0xfffffff, "ULPTX parity error", -1, 1 },
  1269. { 0 }
  1270. };
  1271. if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE, ulptx_intr_info))
  1272. t4_fatal_err(adapter);
  1273. }
  1274. /*
  1275. * PM TX interrupt handler.
  1276. */
  1277. static void pmtx_intr_handler(struct adapter *adapter)
  1278. {
  1279. static const struct intr_info pmtx_intr_info[] = {
  1280. { PCMD_LEN_OVFL0, "PMTX channel 0 pcmd too large", -1, 1 },
  1281. { PCMD_LEN_OVFL1, "PMTX channel 1 pcmd too large", -1, 1 },
  1282. { PCMD_LEN_OVFL2, "PMTX channel 2 pcmd too large", -1, 1 },
  1283. { ZERO_C_CMD_ERROR, "PMTX 0-length pcmd", -1, 1 },
  1284. { PMTX_FRAMING_ERROR, "PMTX framing error", -1, 1 },
  1285. { OESPI_PAR_ERROR, "PMTX oespi parity error", -1, 1 },
  1286. { DB_OPTIONS_PAR_ERROR, "PMTX db_options parity error", -1, 1 },
  1287. { ICSPI_PAR_ERROR, "PMTX icspi parity error", -1, 1 },
  1288. { C_PCMD_PAR_ERROR, "PMTX c_pcmd parity error", -1, 1},
  1289. { 0 }
  1290. };
  1291. if (t4_handle_intr_status(adapter, PM_TX_INT_CAUSE, pmtx_intr_info))
  1292. t4_fatal_err(adapter);
  1293. }
  1294. /*
  1295. * PM RX interrupt handler.
  1296. */
  1297. static void pmrx_intr_handler(struct adapter *adapter)
  1298. {
  1299. static const struct intr_info pmrx_intr_info[] = {
  1300. { ZERO_E_CMD_ERROR, "PMRX 0-length pcmd", -1, 1 },
  1301. { PMRX_FRAMING_ERROR, "PMRX framing error", -1, 1 },
  1302. { OCSPI_PAR_ERROR, "PMRX ocspi parity error", -1, 1 },
  1303. { DB_OPTIONS_PAR_ERROR, "PMRX db_options parity error", -1, 1 },
  1304. { IESPI_PAR_ERROR, "PMRX iespi parity error", -1, 1 },
  1305. { E_PCMD_PAR_ERROR, "PMRX e_pcmd parity error", -1, 1},
  1306. { 0 }
  1307. };
  1308. if (t4_handle_intr_status(adapter, PM_RX_INT_CAUSE, pmrx_intr_info))
  1309. t4_fatal_err(adapter);
  1310. }
  1311. /*
  1312. * CPL switch interrupt handler.
  1313. */
  1314. static void cplsw_intr_handler(struct adapter *adapter)
  1315. {
  1316. static const struct intr_info cplsw_intr_info[] = {
  1317. { CIM_OP_MAP_PERR, "CPLSW CIM op_map parity error", -1, 1 },
  1318. { CIM_OVFL_ERROR, "CPLSW CIM overflow", -1, 1 },
  1319. { TP_FRAMING_ERROR, "CPLSW TP framing error", -1, 1 },
  1320. { SGE_FRAMING_ERROR, "CPLSW SGE framing error", -1, 1 },
  1321. { CIM_FRAMING_ERROR, "CPLSW CIM framing error", -1, 1 },
  1322. { ZERO_SWITCH_ERROR, "CPLSW no-switch error", -1, 1 },
  1323. { 0 }
  1324. };
  1325. if (t4_handle_intr_status(adapter, CPL_INTR_CAUSE, cplsw_intr_info))
  1326. t4_fatal_err(adapter);
  1327. }
  1328. /*
  1329. * LE interrupt handler.
  1330. */
  1331. static void le_intr_handler(struct adapter *adap)
  1332. {
  1333. static const struct intr_info le_intr_info[] = {
  1334. { LIPMISS, "LE LIP miss", -1, 0 },
  1335. { LIP0, "LE 0 LIP error", -1, 0 },
  1336. { PARITYERR, "LE parity error", -1, 1 },
  1337. { UNKNOWNCMD, "LE unknown command", -1, 1 },
  1338. { REQQPARERR, "LE request queue parity error", -1, 1 },
  1339. { 0 }
  1340. };
  1341. if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE, le_intr_info))
  1342. t4_fatal_err(adap);
  1343. }
  1344. /*
  1345. * MPS interrupt handler.
  1346. */
  1347. static void mps_intr_handler(struct adapter *adapter)
  1348. {
  1349. static const struct intr_info mps_rx_intr_info[] = {
  1350. { 0xffffff, "MPS Rx parity error", -1, 1 },
  1351. { 0 }
  1352. };
  1353. static const struct intr_info mps_tx_intr_info[] = {
  1354. { TPFIFO, "MPS Tx TP FIFO parity error", -1, 1 },
  1355. { NCSIFIFO, "MPS Tx NC-SI FIFO parity error", -1, 1 },
  1356. { TXDATAFIFO, "MPS Tx data FIFO parity error", -1, 1 },
  1357. { TXDESCFIFO, "MPS Tx desc FIFO parity error", -1, 1 },
  1358. { BUBBLE, "MPS Tx underflow", -1, 1 },
  1359. { SECNTERR, "MPS Tx SOP/EOP error", -1, 1 },
  1360. { FRMERR, "MPS Tx framing error", -1, 1 },
  1361. { 0 }
  1362. };
  1363. static const struct intr_info mps_trc_intr_info[] = {
  1364. { FILTMEM, "MPS TRC filter parity error", -1, 1 },
  1365. { PKTFIFO, "MPS TRC packet FIFO parity error", -1, 1 },
  1366. { MISCPERR, "MPS TRC misc parity error", -1, 1 },
  1367. { 0 }
  1368. };
  1369. static const struct intr_info mps_stat_sram_intr_info[] = {
  1370. { 0x1fffff, "MPS statistics SRAM parity error", -1, 1 },
  1371. { 0 }
  1372. };
  1373. static const struct intr_info mps_stat_tx_intr_info[] = {
  1374. { 0xfffff, "MPS statistics Tx FIFO parity error", -1, 1 },
  1375. { 0 }
  1376. };
  1377. static const struct intr_info mps_stat_rx_intr_info[] = {
  1378. { 0xffffff, "MPS statistics Rx FIFO parity error", -1, 1 },
  1379. { 0 }
  1380. };
  1381. static const struct intr_info mps_cls_intr_info[] = {
  1382. { MATCHSRAM, "MPS match SRAM parity error", -1, 1 },
  1383. { MATCHTCAM, "MPS match TCAM parity error", -1, 1 },
  1384. { HASHSRAM, "MPS hash SRAM parity error", -1, 1 },
  1385. { 0 }
  1386. };
  1387. int fat;
  1388. fat = t4_handle_intr_status(adapter, MPS_RX_PERR_INT_CAUSE,
  1389. mps_rx_intr_info) +
  1390. t4_handle_intr_status(adapter, MPS_TX_INT_CAUSE,
  1391. mps_tx_intr_info) +
  1392. t4_handle_intr_status(adapter, MPS_TRC_INT_CAUSE,
  1393. mps_trc_intr_info) +
  1394. t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_SRAM,
  1395. mps_stat_sram_intr_info) +
  1396. t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_TX_FIFO,
  1397. mps_stat_tx_intr_info) +
  1398. t4_handle_intr_status(adapter, MPS_STAT_PERR_INT_CAUSE_RX_FIFO,
  1399. mps_stat_rx_intr_info) +
  1400. t4_handle_intr_status(adapter, MPS_CLS_INT_CAUSE,
  1401. mps_cls_intr_info);
  1402. t4_write_reg(adapter, MPS_INT_CAUSE, CLSINT | TRCINT |
  1403. RXINT | TXINT | STATINT);
  1404. t4_read_reg(adapter, MPS_INT_CAUSE); /* flush */
  1405. if (fat)
  1406. t4_fatal_err(adapter);
  1407. }
  1408. #define MEM_INT_MASK (PERR_INT_CAUSE | ECC_CE_INT_CAUSE | ECC_UE_INT_CAUSE)
  1409. /*
  1410. * EDC/MC interrupt handler.
  1411. */
  1412. static void mem_intr_handler(struct adapter *adapter, int idx)
  1413. {
  1414. static const char name[3][5] = { "EDC0", "EDC1", "MC" };
  1415. unsigned int addr, cnt_addr, v;
  1416. if (idx <= MEM_EDC1) {
  1417. addr = EDC_REG(EDC_INT_CAUSE, idx);
  1418. cnt_addr = EDC_REG(EDC_ECC_STATUS, idx);
  1419. } else {
  1420. addr = MC_INT_CAUSE;
  1421. cnt_addr = MC_ECC_STATUS;
  1422. }
  1423. v = t4_read_reg(adapter, addr) & MEM_INT_MASK;
  1424. if (v & PERR_INT_CAUSE)
  1425. dev_alert(adapter->pdev_dev, "%s FIFO parity error\n",
  1426. name[idx]);
  1427. if (v & ECC_CE_INT_CAUSE) {
  1428. u32 cnt = ECC_CECNT_GET(t4_read_reg(adapter, cnt_addr));
  1429. t4_write_reg(adapter, cnt_addr, ECC_CECNT_MASK);
  1430. if (printk_ratelimit())
  1431. dev_warn(adapter->pdev_dev,
  1432. "%u %s correctable ECC data error%s\n",
  1433. cnt, name[idx], cnt > 1 ? "s" : "");
  1434. }
  1435. if (v & ECC_UE_INT_CAUSE)
  1436. dev_alert(adapter->pdev_dev,
  1437. "%s uncorrectable ECC data error\n", name[idx]);
  1438. t4_write_reg(adapter, addr, v);
  1439. if (v & (PERR_INT_CAUSE | ECC_UE_INT_CAUSE))
  1440. t4_fatal_err(adapter);
  1441. }
  1442. /*
  1443. * MA interrupt handler.
  1444. */
  1445. static void ma_intr_handler(struct adapter *adap)
  1446. {
  1447. u32 v, status = t4_read_reg(adap, MA_INT_CAUSE);
  1448. if (status & MEM_PERR_INT_CAUSE)
  1449. dev_alert(adap->pdev_dev,
  1450. "MA parity error, parity status %#x\n",
  1451. t4_read_reg(adap, MA_PARITY_ERROR_STATUS));
  1452. if (status & MEM_WRAP_INT_CAUSE) {
  1453. v = t4_read_reg(adap, MA_INT_WRAP_STATUS);
  1454. dev_alert(adap->pdev_dev, "MA address wrap-around error by "
  1455. "client %u to address %#x\n",
  1456. MEM_WRAP_CLIENT_NUM_GET(v),
  1457. MEM_WRAP_ADDRESS_GET(v) << 4);
  1458. }
  1459. t4_write_reg(adap, MA_INT_CAUSE, status);
  1460. t4_fatal_err(adap);
  1461. }
  1462. /*
  1463. * SMB interrupt handler.
  1464. */
  1465. static void smb_intr_handler(struct adapter *adap)
  1466. {
  1467. static const struct intr_info smb_intr_info[] = {
  1468. { MSTTXFIFOPARINT, "SMB master Tx FIFO parity error", -1, 1 },
  1469. { MSTRXFIFOPARINT, "SMB master Rx FIFO parity error", -1, 1 },
  1470. { SLVFIFOPARINT, "SMB slave FIFO parity error", -1, 1 },
  1471. { 0 }
  1472. };
  1473. if (t4_handle_intr_status(adap, SMB_INT_CAUSE, smb_intr_info))
  1474. t4_fatal_err(adap);
  1475. }
  1476. /*
  1477. * NC-SI interrupt handler.
  1478. */
  1479. static void ncsi_intr_handler(struct adapter *adap)
  1480. {
  1481. static const struct intr_info ncsi_intr_info[] = {
  1482. { CIM_DM_PRTY_ERR, "NC-SI CIM parity error", -1, 1 },
  1483. { MPS_DM_PRTY_ERR, "NC-SI MPS parity error", -1, 1 },
  1484. { TXFIFO_PRTY_ERR, "NC-SI Tx FIFO parity error", -1, 1 },
  1485. { RXFIFO_PRTY_ERR, "NC-SI Rx FIFO parity error", -1, 1 },
  1486. { 0 }
  1487. };
  1488. if (t4_handle_intr_status(adap, NCSI_INT_CAUSE, ncsi_intr_info))
  1489. t4_fatal_err(adap);
  1490. }
  1491. /*
  1492. * XGMAC interrupt handler.
  1493. */
  1494. static void xgmac_intr_handler(struct adapter *adap, int port)
  1495. {
  1496. u32 v = t4_read_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE));
  1497. v &= TXFIFO_PRTY_ERR | RXFIFO_PRTY_ERR;
  1498. if (!v)
  1499. return;
  1500. if (v & TXFIFO_PRTY_ERR)
  1501. dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n",
  1502. port);
  1503. if (v & RXFIFO_PRTY_ERR)
  1504. dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n",
  1505. port);
  1506. t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v);
  1507. t4_fatal_err(adap);
  1508. }
  1509. /*
  1510. * PL interrupt handler.
  1511. */
  1512. static void pl_intr_handler(struct adapter *adap)
  1513. {
  1514. static const struct intr_info pl_intr_info[] = {
  1515. { FATALPERR, "T4 fatal parity error", -1, 1 },
  1516. { PERRVFID, "PL VFID_MAP parity error", -1, 1 },
  1517. { 0 }
  1518. };
  1519. if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE, pl_intr_info))
  1520. t4_fatal_err(adap);
  1521. }
  1522. #define PF_INTR_MASK (PFSW)
  1523. #define GLBL_INTR_MASK (CIM | MPS | PL | PCIE | MC | EDC0 | \
  1524. EDC1 | LE | TP | MA | PM_TX | PM_RX | ULP_RX | \
  1525. CPL_SWITCH | SGE | ULP_TX)
  1526. /**
  1527. * t4_slow_intr_handler - control path interrupt handler
  1528. * @adapter: the adapter
  1529. *
  1530. * T4 interrupt handler for non-data global interrupt events, e.g., errors.
  1531. * The designation 'slow' is because it involves register reads, while
  1532. * data interrupts typically don't involve any MMIOs.
  1533. */
  1534. int t4_slow_intr_handler(struct adapter *adapter)
  1535. {
  1536. u32 cause = t4_read_reg(adapter, PL_INT_CAUSE);
  1537. if (!(cause & GLBL_INTR_MASK))
  1538. return 0;
  1539. if (cause & CIM)
  1540. cim_intr_handler(adapter);
  1541. if (cause & MPS)
  1542. mps_intr_handler(adapter);
  1543. if (cause & NCSI)
  1544. ncsi_intr_handler(adapter);
  1545. if (cause & PL)
  1546. pl_intr_handler(adapter);
  1547. if (cause & SMB)
  1548. smb_intr_handler(adapter);
  1549. if (cause & XGMAC0)
  1550. xgmac_intr_handler(adapter, 0);
  1551. if (cause & XGMAC1)
  1552. xgmac_intr_handler(adapter, 1);
  1553. if (cause & XGMAC_KR0)
  1554. xgmac_intr_handler(adapter, 2);
  1555. if (cause & XGMAC_KR1)
  1556. xgmac_intr_handler(adapter, 3);
  1557. if (cause & PCIE)
  1558. pcie_intr_handler(adapter);
  1559. if (cause & MC)
  1560. mem_intr_handler(adapter, MEM_MC);
  1561. if (cause & EDC0)
  1562. mem_intr_handler(adapter, MEM_EDC0);
  1563. if (cause & EDC1)
  1564. mem_intr_handler(adapter, MEM_EDC1);
  1565. if (cause & LE)
  1566. le_intr_handler(adapter);
  1567. if (cause & TP)
  1568. tp_intr_handler(adapter);
  1569. if (cause & MA)
  1570. ma_intr_handler(adapter);
  1571. if (cause & PM_TX)
  1572. pmtx_intr_handler(adapter);
  1573. if (cause & PM_RX)
  1574. pmrx_intr_handler(adapter);
  1575. if (cause & ULP_RX)
  1576. ulprx_intr_handler(adapter);
  1577. if (cause & CPL_SWITCH)
  1578. cplsw_intr_handler(adapter);
  1579. if (cause & SGE)
  1580. sge_intr_handler(adapter);
  1581. if (cause & ULP_TX)
  1582. ulptx_intr_handler(adapter);
  1583. /* Clear the interrupts just processed for which we are the master. */
  1584. t4_write_reg(adapter, PL_INT_CAUSE, cause & GLBL_INTR_MASK);
  1585. (void) t4_read_reg(adapter, PL_INT_CAUSE); /* flush */
  1586. return 1;
  1587. }
  1588. /**
  1589. * t4_intr_enable - enable interrupts
  1590. * @adapter: the adapter whose interrupts should be enabled
  1591. *
  1592. * Enable PF-specific interrupts for the calling function and the top-level
  1593. * interrupt concentrator for global interrupts. Interrupts are already
  1594. * enabled at each module, here we just enable the roots of the interrupt
  1595. * hierarchies.
  1596. *
  1597. * Note: this function should be called only when the driver manages
  1598. * non PF-specific interrupts from the various HW modules. Only one PCI
  1599. * function at a time should be doing this.
  1600. */
  1601. void t4_intr_enable(struct adapter *adapter)
  1602. {
  1603. u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
  1604. t4_write_reg(adapter, SGE_INT_ENABLE3, ERR_CPL_EXCEED_IQE_SIZE |
  1605. ERR_INVALID_CIDX_INC | ERR_CPL_OPCODE_0 |
  1606. ERR_DROPPED_DB | ERR_DATA_CPL_ON_HIGH_QID1 |
  1607. ERR_DATA_CPL_ON_HIGH_QID0 | ERR_BAD_DB_PIDX3 |
  1608. ERR_BAD_DB_PIDX2 | ERR_BAD_DB_PIDX1 |
  1609. ERR_BAD_DB_PIDX0 | ERR_ING_CTXT_PRIO |
  1610. ERR_EGR_CTXT_PRIO | INGRESS_SIZE_ERR |
  1611. DBFIFO_HP_INT | DBFIFO_LP_INT |
  1612. EGRESS_SIZE_ERR);
  1613. t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), PF_INTR_MASK);
  1614. t4_set_reg_field(adapter, PL_INT_MAP0, 0, 1 << pf);
  1615. }
  1616. /**
  1617. * t4_intr_disable - disable interrupts
  1618. * @adapter: the adapter whose interrupts should be disabled
  1619. *
  1620. * Disable interrupts. We only disable the top-level interrupt
  1621. * concentrators. The caller must be a PCI function managing global
  1622. * interrupts.
  1623. */
  1624. void t4_intr_disable(struct adapter *adapter)
  1625. {
  1626. u32 pf = SOURCEPF_GET(t4_read_reg(adapter, PL_WHOAMI));
  1627. t4_write_reg(adapter, MYPF_REG(PL_PF_INT_ENABLE), 0);
  1628. t4_set_reg_field(adapter, PL_INT_MAP0, 1 << pf, 0);
  1629. }
  1630. /**
  1631. * hash_mac_addr - return the hash value of a MAC address
  1632. * @addr: the 48-bit Ethernet MAC address
  1633. *
  1634. * Hashes a MAC address according to the hash function used by HW inexact
  1635. * (hash) address matching.
  1636. */
  1637. static int hash_mac_addr(const u8 *addr)
  1638. {
  1639. u32 a = ((u32)addr[0] << 16) | ((u32)addr[1] << 8) | addr[2];
  1640. u32 b = ((u32)addr[3] << 16) | ((u32)addr[4] << 8) | addr[5];
  1641. a ^= b;
  1642. a ^= (a >> 12);
  1643. a ^= (a >> 6);
  1644. return a & 0x3f;
  1645. }
  1646. /**
  1647. * t4_config_rss_range - configure a portion of the RSS mapping table
  1648. * @adapter: the adapter
  1649. * @mbox: mbox to use for the FW command
  1650. * @viid: virtual interface whose RSS subtable is to be written
  1651. * @start: start entry in the table to write
  1652. * @n: how many table entries to write
  1653. * @rspq: values for the response queue lookup table
  1654. * @nrspq: number of values in @rspq
  1655. *
  1656. * Programs the selected part of the VI's RSS mapping table with the
  1657. * provided values. If @nrspq < @n the supplied values are used repeatedly
  1658. * until the full table range is populated.
  1659. *
  1660. * The caller must ensure the values in @rspq are in the range allowed for
  1661. * @viid.
  1662. */
  1663. int t4_config_rss_range(struct adapter *adapter, int mbox, unsigned int viid,
  1664. int start, int n, const u16 *rspq, unsigned int nrspq)
  1665. {
  1666. int ret;
  1667. const u16 *rsp = rspq;
  1668. const u16 *rsp_end = rspq + nrspq;
  1669. struct fw_rss_ind_tbl_cmd cmd;
  1670. memset(&cmd, 0, sizeof(cmd));
  1671. cmd.op_to_viid = htonl(FW_CMD_OP(FW_RSS_IND_TBL_CMD) |
  1672. FW_CMD_REQUEST | FW_CMD_WRITE |
  1673. FW_RSS_IND_TBL_CMD_VIID(viid));
  1674. cmd.retval_len16 = htonl(FW_LEN16(cmd));
  1675. /* each fw_rss_ind_tbl_cmd takes up to 32 entries */
  1676. while (n > 0) {
  1677. int nq = min(n, 32);
  1678. __be32 *qp = &cmd.iq0_to_iq2;
  1679. cmd.niqid = htons(nq);
  1680. cmd.startidx = htons(start);
  1681. start += nq;
  1682. n -= nq;
  1683. while (nq > 0) {
  1684. unsigned int v;
  1685. v = FW_RSS_IND_TBL_CMD_IQ0(*rsp);
  1686. if (++rsp >= rsp_end)
  1687. rsp = rspq;
  1688. v |= FW_RSS_IND_TBL_CMD_IQ1(*rsp);
  1689. if (++rsp >= rsp_end)
  1690. rsp = rspq;
  1691. v |= FW_RSS_IND_TBL_CMD_IQ2(*rsp);
  1692. if (++rsp >= rsp_end)
  1693. rsp = rspq;
  1694. *qp++ = htonl(v);
  1695. nq -= 3;
  1696. }
  1697. ret = t4_wr_mbox(adapter, mbox, &cmd, sizeof(cmd), NULL);
  1698. if (ret)
  1699. return ret;
  1700. }
  1701. return 0;
  1702. }
  1703. /**
  1704. * t4_config_glbl_rss - configure the global RSS mode
  1705. * @adapter: the adapter
  1706. * @mbox: mbox to use for the FW command
  1707. * @mode: global RSS mode
  1708. * @flags: mode-specific flags
  1709. *
  1710. * Sets the global RSS mode.
  1711. */
  1712. int t4_config_glbl_rss(struct adapter *adapter, int mbox, unsigned int mode,
  1713. unsigned int flags)
  1714. {
  1715. struct fw_rss_glb_config_cmd c;
  1716. memset(&c, 0, sizeof(c));
  1717. c.op_to_write = htonl(FW_CMD_OP(FW_RSS_GLB_CONFIG_CMD) |
  1718. FW_CMD_REQUEST | FW_CMD_WRITE);
  1719. c.retval_len16 = htonl(FW_LEN16(c));
  1720. if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL) {
  1721. c.u.manual.mode_pkd = htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
  1722. } else if (mode == FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
  1723. c.u.basicvirtual.mode_pkd =
  1724. htonl(FW_RSS_GLB_CONFIG_CMD_MODE(mode));
  1725. c.u.basicvirtual.synmapen_to_hashtoeplitz = htonl(flags);
  1726. } else
  1727. return -EINVAL;
  1728. return t4_wr_mbox(adapter, mbox, &c, sizeof(c), NULL);
  1729. }
  1730. /**
  1731. * t4_tp_get_tcp_stats - read TP's TCP MIB counters
  1732. * @adap: the adapter
  1733. * @v4: holds the TCP/IP counter values
  1734. * @v6: holds the TCP/IPv6 counter values
  1735. *
  1736. * Returns the values of TP's TCP/IP and TCP/IPv6 MIB counters.
  1737. * Either @v4 or @v6 may be %NULL to skip the corresponding stats.
  1738. */
  1739. void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4,
  1740. struct tp_tcp_stats *v6)
  1741. {
  1742. u32 val[TP_MIB_TCP_RXT_SEG_LO - TP_MIB_TCP_OUT_RST + 1];
  1743. #define STAT_IDX(x) ((TP_MIB_TCP_##x) - TP_MIB_TCP_OUT_RST)
  1744. #define STAT(x) val[STAT_IDX(x)]
  1745. #define STAT64(x) (((u64)STAT(x##_HI) << 32) | STAT(x##_LO))
  1746. if (v4) {
  1747. t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
  1748. ARRAY_SIZE(val), TP_MIB_TCP_OUT_RST);
  1749. v4->tcpOutRsts = STAT(OUT_RST);
  1750. v4->tcpInSegs = STAT64(IN_SEG);
  1751. v4->tcpOutSegs = STAT64(OUT_SEG);
  1752. v4->tcpRetransSegs = STAT64(RXT_SEG);
  1753. }
  1754. if (v6) {
  1755. t4_read_indirect(adap, TP_MIB_INDEX, TP_MIB_DATA, val,
  1756. ARRAY_SIZE(val), TP_MIB_TCP_V6OUT_RST);
  1757. v6->tcpOutRsts = STAT(OUT_RST);
  1758. v6->tcpInSegs = STAT64(IN_SEG);
  1759. v6->tcpOutSegs = STAT64(OUT_SEG);
  1760. v6->tcpRetransSegs = STAT64(RXT_SEG);
  1761. }
  1762. #undef STAT64
  1763. #undef STAT
  1764. #undef STAT_IDX
  1765. }
  1766. /**
  1767. * t4_read_mtu_tbl - returns the values in the HW path MTU table
  1768. * @adap: the adapter
  1769. * @mtus: where to store the MTU values
  1770. * @mtu_log: where to store the MTU base-2 log (may be %NULL)
  1771. *
  1772. * Reads the HW path MTU table.
  1773. */
  1774. void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log)
  1775. {
  1776. u32 v;
  1777. int i;
  1778. for (i = 0; i < NMTUS; ++i) {
  1779. t4_write_reg(adap, TP_MTU_TABLE,
  1780. MTUINDEX(0xff) | MTUVALUE(i));
  1781. v = t4_read_reg(adap, TP_MTU_TABLE);
  1782. mtus[i] = MTUVALUE_GET(v);
  1783. if (mtu_log)
  1784. mtu_log[i] = MTUWIDTH_GET(v);
  1785. }
  1786. }
  1787. /**
  1788. * t4_tp_wr_bits_indirect - set/clear bits in an indirect TP register
  1789. * @adap: the adapter
  1790. * @addr: the indirect TP register address
  1791. * @mask: specifies the field within the register to modify
  1792. * @val: new value for the field
  1793. *
  1794. * Sets a field of an indirect TP register to the given value.
  1795. */
  1796. void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr,
  1797. unsigned int mask, unsigned int val)
  1798. {
  1799. t4_write_reg(adap, TP_PIO_ADDR, addr);
  1800. val |= t4_read_reg(adap, TP_PIO_DATA) & ~mask;
  1801. t4_write_reg(adap, TP_PIO_DATA, val);
  1802. }
  1803. /**
  1804. * init_cong_ctrl - initialize congestion control parameters
  1805. * @a: the alpha values for congestion control
  1806. * @b: the beta values for congestion control
  1807. *
  1808. * Initialize the congestion control parameters.
  1809. */
  1810. static void init_cong_ctrl(unsigned short *a, unsigned short *b)
  1811. {
  1812. a[0] = a[1] = a[2] = a[3] = a[4] = a[5] = a[6] = a[7] = a[8] = 1;
  1813. a[9] = 2;
  1814. a[10] = 3;
  1815. a[11] = 4;
  1816. a[12] = 5;
  1817. a[13] = 6;
  1818. a[14] = 7;
  1819. a[15] = 8;
  1820. a[16] = 9;
  1821. a[17] = 10;
  1822. a[18] = 14;
  1823. a[19] = 17;
  1824. a[20] = 21;
  1825. a[21] = 25;
  1826. a[22] = 30;
  1827. a[23] = 35;
  1828. a[24] = 45;
  1829. a[25] = 60;
  1830. a[26] = 80;
  1831. a[27] = 100;
  1832. a[28] = 200;
  1833. a[29] = 300;
  1834. a[30] = 400;
  1835. a[31] = 500;
  1836. b[0] = b[1] = b[2] = b[3] = b[4] = b[5] = b[6] = b[7] = b[8] = 0;
  1837. b[9] = b[10] = 1;
  1838. b[11] = b[12] = 2;
  1839. b[13] = b[14] = b[15] = b[16] = 3;
  1840. b[17] = b[18] = b[19] = b[20] = b[21] = 4;
  1841. b[22] = b[23] = b[24] = b[25] = b[26] = b[27] = 5;
  1842. b[28] = b[29] = 6;
  1843. b[30] = b[31] = 7;
  1844. }
  1845. /* The minimum additive increment value for the congestion control table */
  1846. #define CC_MIN_INCR 2U
  1847. /**
  1848. * t4_load_mtus - write the MTU and congestion control HW tables
  1849. * @adap: the adapter
  1850. * @mtus: the values for the MTU table
  1851. * @alpha: the values for the congestion control alpha parameter
  1852. * @beta: the values for the congestion control beta parameter
  1853. *
  1854. * Write the HW MTU table with the supplied MTUs and the high-speed
  1855. * congestion control table with the supplied alpha, beta, and MTUs.
  1856. * We write the two tables together because the additive increments
  1857. * depend on the MTUs.
  1858. */
  1859. void t4_load_mtus(struct adapter *adap, const unsigned short *mtus,
  1860. const unsigned short *alpha, const unsigned short *beta)
  1861. {
  1862. static const unsigned int avg_pkts[NCCTRL_WIN] = {
  1863. 2, 6, 10, 14, 20, 28, 40, 56, 80, 112, 160, 224, 320, 448, 640,
  1864. 896, 1281, 1792, 2560, 3584, 5120, 7168, 10240, 14336, 20480,
  1865. 28672, 40960, 57344, 81920, 114688, 163840, 229376
  1866. };
  1867. unsigned int i, w;
  1868. for (i = 0; i < NMTUS; ++i) {
  1869. unsigned int mtu = mtus[i];
  1870. unsigned int log2 = fls(mtu);
  1871. if (!(mtu & ((1 << log2) >> 2))) /* round */
  1872. log2--;
  1873. t4_write_reg(adap, TP_MTU_TABLE, MTUINDEX(i) |
  1874. MTUWIDTH(log2) | MTUVALUE(mtu));
  1875. for (w = 0; w < NCCTRL_WIN; ++w) {
  1876. unsigned int inc;
  1877. inc = max(((mtu - 40) * alpha[w]) / avg_pkts[w],
  1878. CC_MIN_INCR);
  1879. t4_write_reg(adap, TP_CCTRL_TABLE, (i << 21) |
  1880. (w << 16) | (beta[w] << 13) | inc);
  1881. }
  1882. }
  1883. }
  1884. /**
  1885. * get_mps_bg_map - return the buffer groups associated with a port
  1886. * @adap: the adapter
  1887. * @idx: the port index
  1888. *
  1889. * Returns a bitmap indicating which MPS buffer groups are associated
  1890. * with the given port. Bit i is set if buffer group i is used by the
  1891. * port.
  1892. */
  1893. static unsigned int get_mps_bg_map(struct adapter *adap, int idx)
  1894. {
  1895. u32 n = NUMPORTS_GET(t4_read_reg(adap, MPS_CMN_CTL));
  1896. if (n == 0)
  1897. return idx == 0 ? 0xf : 0;
  1898. if (n == 1)
  1899. return idx < 2 ? (3 << (2 * idx)) : 0;
  1900. return 1 << idx;
  1901. }
  1902. /**
  1903. * t4_get_port_stats - collect port statistics
  1904. * @adap: the adapter
  1905. * @idx: the port index
  1906. * @p: the stats structure to fill
  1907. *
  1908. * Collect statistics related to the given port from HW.
  1909. */
  1910. void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p)
  1911. {
  1912. u32 bgmap = get_mps_bg_map(adap, idx);
  1913. #define GET_STAT(name) \
  1914. t4_read_reg64(adap, PORT_REG(idx, MPS_PORT_STAT_##name##_L))
  1915. #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L)
  1916. p->tx_octets = GET_STAT(TX_PORT_BYTES);
  1917. p->tx_frames = GET_STAT(TX_PORT_FRAMES);
  1918. p->tx_bcast_frames = GET_STAT(TX_PORT_BCAST);
  1919. p->tx_mcast_frames = GET_STAT(TX_PORT_MCAST);
  1920. p->tx_ucast_frames = GET_STAT(TX_PORT_UCAST);
  1921. p->tx_error_frames = GET_STAT(TX_PORT_ERROR);
  1922. p->tx_frames_64 = GET_STAT(TX_PORT_64B);
  1923. p->tx_frames_65_127 = GET_STAT(TX_PORT_65B_127B);
  1924. p->tx_frames_128_255 = GET_STAT(TX_PORT_128B_255B);
  1925. p->tx_frames_256_511 = GET_STAT(TX_PORT_256B_511B);
  1926. p->tx_frames_512_1023 = GET_STAT(TX_PORT_512B_1023B);
  1927. p->tx_frames_1024_1518 = GET_STAT(TX_PORT_1024B_1518B);
  1928. p->tx_frames_1519_max = GET_STAT(TX_PORT_1519B_MAX);
  1929. p->tx_drop = GET_STAT(TX_PORT_DROP);
  1930. p->tx_pause = GET_STAT(TX_PORT_PAUSE);
  1931. p->tx_ppp0 = GET_STAT(TX_PORT_PPP0);
  1932. p->tx_ppp1 = GET_STAT(TX_PORT_PPP1);
  1933. p->tx_ppp2 = GET_STAT(TX_PORT_PPP2);
  1934. p->tx_ppp3 = GET_STAT(TX_PORT_PPP3);
  1935. p->tx_ppp4 = GET_STAT(TX_PORT_PPP4);
  1936. p->tx_ppp5 = GET_STAT(TX_PORT_PPP5);
  1937. p->tx_ppp6 = GET_STAT(TX_PORT_PPP6);
  1938. p->tx_ppp7 = GET_STAT(TX_PORT_PPP7);
  1939. p->rx_octets = GET_STAT(RX_PORT_BYTES);
  1940. p->rx_frames = GET_STAT(RX_PORT_FRAMES);
  1941. p->rx_bcast_frames = GET_STAT(RX_PORT_BCAST);
  1942. p->rx_mcast_frames = GET_STAT(RX_PORT_MCAST);
  1943. p->rx_ucast_frames = GET_STAT(RX_PORT_UCAST);
  1944. p->rx_too_long = GET_STAT(RX_PORT_MTU_ERROR);
  1945. p->rx_jabber = GET_STAT(RX_PORT_MTU_CRC_ERROR);
  1946. p->rx_fcs_err = GET_STAT(RX_PORT_CRC_ERROR);
  1947. p->rx_len_err = GET_STAT(RX_PORT_LEN_ERROR);
  1948. p->rx_symbol_err = GET_STAT(RX_PORT_SYM_ERROR);
  1949. p->rx_runt = GET_STAT(RX_PORT_LESS_64B);
  1950. p->rx_frames_64 = GET_STAT(RX_PORT_64B);
  1951. p->rx_frames_65_127 = GET_STAT(RX_PORT_65B_127B);
  1952. p->rx_frames_128_255 = GET_STAT(RX_PORT_128B_255B);
  1953. p->rx_frames_256_511 = GET_STAT(RX_PORT_256B_511B);
  1954. p->rx_frames_512_1023 = GET_STAT(RX_PORT_512B_1023B);
  1955. p->rx_frames_1024_1518 = GET_STAT(RX_PORT_1024B_1518B);
  1956. p->rx_frames_1519_max = GET_STAT(RX_PORT_1519B_MAX);
  1957. p->rx_pause = GET_STAT(RX_PORT_PAUSE);
  1958. p->rx_ppp0 = GET_STAT(RX_PORT_PPP0);
  1959. p->rx_ppp1 = GET_STAT(RX_PORT_PPP1);
  1960. p->rx_ppp2 = GET_STAT(RX_PORT_PPP2);
  1961. p->rx_ppp3 = GET_STAT(RX_PORT_PPP3);
  1962. p->rx_ppp4 = GET_STAT(RX_PORT_PPP4);
  1963. p->rx_ppp5 = GET_STAT(RX_PORT_PPP5);
  1964. p->rx_ppp6 = GET_STAT(RX_PORT_PPP6);
  1965. p->rx_ppp7 = GET_STAT(RX_PORT_PPP7);
  1966. p->rx_ovflow0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_DROP_FRAME) : 0;
  1967. p->rx_ovflow1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_DROP_FRAME) : 0;
  1968. p->rx_ovflow2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_DROP_FRAME) : 0;
  1969. p->rx_ovflow3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_DROP_FRAME) : 0;
  1970. p->rx_trunc0 = (bgmap & 1) ? GET_STAT_COM(RX_BG_0_MAC_TRUNC_FRAME) : 0;
  1971. p->rx_trunc1 = (bgmap & 2) ? GET_STAT_COM(RX_BG_1_MAC_TRUNC_FRAME) : 0;
  1972. p->rx_trunc2 = (bgmap & 4) ? GET_STAT_COM(RX_BG_2_MAC_TRUNC_FRAME) : 0;
  1973. p->rx_trunc3 = (bgmap & 8) ? GET_STAT_COM(RX_BG_3_MAC_TRUNC_FRAME) : 0;
  1974. #undef GET_STAT
  1975. #undef GET_STAT_COM
  1976. }
  1977. /**
  1978. * t4_wol_magic_enable - enable/disable magic packet WoL
  1979. * @adap: the adapter
  1980. * @port: the physical port index
  1981. * @addr: MAC address expected in magic packets, %NULL to disable
  1982. *
  1983. * Enables/disables magic packet wake-on-LAN for the selected port.
  1984. */
  1985. void t4_wol_magic_enable(struct adapter *adap, unsigned int port,
  1986. const u8 *addr)
  1987. {
  1988. if (addr) {
  1989. t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO),
  1990. (addr[2] << 24) | (addr[3] << 16) |
  1991. (addr[4] << 8) | addr[5]);
  1992. t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI),
  1993. (addr[0] << 8) | addr[1]);
  1994. }
  1995. t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), MAGICEN,
  1996. addr ? MAGICEN : 0);
  1997. }
  1998. /**
  1999. * t4_wol_pat_enable - enable/disable pattern-based WoL
  2000. * @adap: the adapter
  2001. * @port: the physical port index
  2002. * @map: bitmap of which HW pattern filters to set
  2003. * @mask0: byte mask for bytes 0-63 of a packet
  2004. * @mask1: byte mask for bytes 64-127 of a packet
  2005. * @crc: Ethernet CRC for selected bytes
  2006. * @enable: enable/disable switch
  2007. *
  2008. * Sets the pattern filters indicated in @map to mask out the bytes
  2009. * specified in @mask0/@mask1 in received packets and compare the CRC of
  2010. * the resulting packet against @crc. If @enable is %true pattern-based
  2011. * WoL is enabled, otherwise disabled.
  2012. */
  2013. int t4_wol_pat_enable(struct adapter *adap, unsigned int port, unsigned int map,
  2014. u64 mask0, u64 mask1, unsigned int crc, bool enable)
  2015. {
  2016. int i;
  2017. if (!enable) {
  2018. t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2),
  2019. PATEN, 0);
  2020. return 0;
  2021. }
  2022. if (map > 0xff)
  2023. return -EINVAL;
  2024. #define EPIO_REG(name) PORT_REG(port, XGMAC_PORT_EPIO_##name)
  2025. t4_write_reg(adap, EPIO_REG(DATA1), mask0 >> 32);
  2026. t4_write_reg(adap, EPIO_REG(DATA2), mask1);
  2027. t4_write_reg(adap, EPIO_REG(DATA3), mask1 >> 32);
  2028. for (i = 0; i < NWOL_PAT; i++, map >>= 1) {
  2029. if (!(map & 1))
  2030. continue;
  2031. /* write byte masks */
  2032. t4_write_reg(adap, EPIO_REG(DATA0), mask0);
  2033. t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i) | EPIOWR);
  2034. t4_read_reg(adap, EPIO_REG(OP)); /* flush */
  2035. if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
  2036. return -ETIMEDOUT;
  2037. /* write CRC */
  2038. t4_write_reg(adap, EPIO_REG(DATA0), crc);
  2039. t4_write_reg(adap, EPIO_REG(OP), ADDRESS(i + 32) | EPIOWR);
  2040. t4_read_reg(adap, EPIO_REG(OP)); /* flush */
  2041. if (t4_read_reg(adap, EPIO_REG(OP)) & SF_BUSY)
  2042. return -ETIMEDOUT;
  2043. }
  2044. #undef EPIO_REG
  2045. t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN);
  2046. return 0;
  2047. }
  2048. /* t4_mk_filtdelwr - create a delete filter WR
  2049. * @ftid: the filter ID
  2050. * @wr: the filter work request to populate
  2051. * @qid: ingress queue to receive the delete notification
  2052. *
  2053. * Creates a filter work request to delete the supplied filter. If @qid is
  2054. * negative the delete notification is suppressed.
  2055. */
  2056. void t4_mk_filtdelwr(unsigned int ftid, struct fw_filter_wr *wr, int qid)
  2057. {
  2058. memset(wr, 0, sizeof(*wr));
  2059. wr->op_pkd = htonl(FW_WR_OP(FW_FILTER_WR));
  2060. wr->len16_pkd = htonl(FW_WR_LEN16(sizeof(*wr) / 16));
  2061. wr->tid_to_iq = htonl(V_FW_FILTER_WR_TID(ftid) |
  2062. V_FW_FILTER_WR_NOREPLY(qid < 0));
  2063. wr->del_filter_to_l2tix = htonl(F_FW_FILTER_WR_DEL_FILTER);
  2064. if (qid >= 0)
  2065. wr->rx_chan_rx_rpl_iq = htons(V_FW_FILTER_WR_RX_RPL_IQ(qid));
  2066. }
  2067. #define INIT_CMD(var, cmd, rd_wr) do { \
  2068. (var).op_to_write = htonl(FW_CMD_OP(FW_##cmd##_CMD) | \
  2069. FW_CMD_REQUEST | FW_CMD_##rd_wr); \
  2070. (var).retval_len16 = htonl(FW_LEN16(var)); \
  2071. } while (0)
  2072. int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox,
  2073. u32 addr, u32 val)
  2074. {
  2075. struct fw_ldst_cmd c;
  2076. memset(&c, 0, sizeof(c));
  2077. c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
  2078. FW_CMD_WRITE |
  2079. FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_FIRMWARE));
  2080. c.cycles_to_len16 = htonl(FW_LEN16(c));
  2081. c.u.addrval.addr = htonl(addr);
  2082. c.u.addrval.val = htonl(val);
  2083. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2084. }
  2085. /**
  2086. * t4_mem_win_read_len - read memory through PCIE memory window
  2087. * @adap: the adapter
  2088. * @addr: address of first byte requested aligned on 32b.
  2089. * @data: len bytes to hold the data read
  2090. * @len: amount of data to read from window. Must be <=
  2091. * MEMWIN0_APERATURE after adjusting for 16B alignment
  2092. * requirements of the the memory window.
  2093. *
  2094. * Read len bytes of data from MC starting at @addr.
  2095. */
  2096. int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len)
  2097. {
  2098. int i;
  2099. int off;
  2100. /*
  2101. * Align on a 16B boundary.
  2102. */
  2103. off = addr & 15;
  2104. if ((addr & 3) || (len + off) > MEMWIN0_APERTURE)
  2105. return -EINVAL;
  2106. t4_write_reg(adap, PCIE_MEM_ACCESS_OFFSET, addr & ~15);
  2107. t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
  2108. for (i = 0; i < len; i += 4)
  2109. *data++ = (__force __be32) t4_read_reg(adap,
  2110. (MEMWIN0_BASE + off + i));
  2111. return 0;
  2112. }
  2113. /**
  2114. * t4_mdio_rd - read a PHY register through MDIO
  2115. * @adap: the adapter
  2116. * @mbox: mailbox to use for the FW command
  2117. * @phy_addr: the PHY address
  2118. * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
  2119. * @reg: the register to read
  2120. * @valp: where to store the value
  2121. *
  2122. * Issues a FW command through the given mailbox to read a PHY register.
  2123. */
  2124. int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
  2125. unsigned int mmd, unsigned int reg, u16 *valp)
  2126. {
  2127. int ret;
  2128. struct fw_ldst_cmd c;
  2129. memset(&c, 0, sizeof(c));
  2130. c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
  2131. FW_CMD_READ | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
  2132. c.cycles_to_len16 = htonl(FW_LEN16(c));
  2133. c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
  2134. FW_LDST_CMD_MMD(mmd));
  2135. c.u.mdio.raddr = htons(reg);
  2136. ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
  2137. if (ret == 0)
  2138. *valp = ntohs(c.u.mdio.rval);
  2139. return ret;
  2140. }
  2141. /**
  2142. * t4_mdio_wr - write a PHY register through MDIO
  2143. * @adap: the adapter
  2144. * @mbox: mailbox to use for the FW command
  2145. * @phy_addr: the PHY address
  2146. * @mmd: the PHY MMD to access (0 for clause 22 PHYs)
  2147. * @reg: the register to write
  2148. * @valp: value to write
  2149. *
  2150. * Issues a FW command through the given mailbox to write a PHY register.
  2151. */
  2152. int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr,
  2153. unsigned int mmd, unsigned int reg, u16 val)
  2154. {
  2155. struct fw_ldst_cmd c;
  2156. memset(&c, 0, sizeof(c));
  2157. c.op_to_addrspace = htonl(FW_CMD_OP(FW_LDST_CMD) | FW_CMD_REQUEST |
  2158. FW_CMD_WRITE | FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MDIO));
  2159. c.cycles_to_len16 = htonl(FW_LEN16(c));
  2160. c.u.mdio.paddr_mmd = htons(FW_LDST_CMD_PADDR(phy_addr) |
  2161. FW_LDST_CMD_MMD(mmd));
  2162. c.u.mdio.raddr = htons(reg);
  2163. c.u.mdio.rval = htons(val);
  2164. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2165. }
  2166. /**
  2167. * t4_fw_hello - establish communication with FW
  2168. * @adap: the adapter
  2169. * @mbox: mailbox to use for the FW command
  2170. * @evt_mbox: mailbox to receive async FW events
  2171. * @master: specifies the caller's willingness to be the device master
  2172. * @state: returns the current device state (if non-NULL)
  2173. *
  2174. * Issues a command to establish communication with FW. Returns either
  2175. * an error (negative integer) or the mailbox of the Master PF.
  2176. */
  2177. int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox,
  2178. enum dev_master master, enum dev_state *state)
  2179. {
  2180. int ret;
  2181. struct fw_hello_cmd c;
  2182. u32 v;
  2183. unsigned int master_mbox;
  2184. int retries = FW_CMD_HELLO_RETRIES;
  2185. retry:
  2186. memset(&c, 0, sizeof(c));
  2187. INIT_CMD(c, HELLO, WRITE);
  2188. c.err_to_clearinit = htonl(
  2189. FW_HELLO_CMD_MASTERDIS(master == MASTER_CANT) |
  2190. FW_HELLO_CMD_MASTERFORCE(master == MASTER_MUST) |
  2191. FW_HELLO_CMD_MBMASTER(master == MASTER_MUST ? mbox :
  2192. FW_HELLO_CMD_MBMASTER_MASK) |
  2193. FW_HELLO_CMD_MBASYNCNOT(evt_mbox) |
  2194. FW_HELLO_CMD_STAGE(fw_hello_cmd_stage_os) |
  2195. FW_HELLO_CMD_CLEARINIT);
  2196. /*
  2197. * Issue the HELLO command to the firmware. If it's not successful
  2198. * but indicates that we got a "busy" or "timeout" condition, retry
  2199. * the HELLO until we exhaust our retry limit.
  2200. */
  2201. ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
  2202. if (ret < 0) {
  2203. if ((ret == -EBUSY || ret == -ETIMEDOUT) && retries-- > 0)
  2204. goto retry;
  2205. return ret;
  2206. }
  2207. v = ntohl(c.err_to_clearinit);
  2208. master_mbox = FW_HELLO_CMD_MBMASTER_GET(v);
  2209. if (state) {
  2210. if (v & FW_HELLO_CMD_ERR)
  2211. *state = DEV_STATE_ERR;
  2212. else if (v & FW_HELLO_CMD_INIT)
  2213. *state = DEV_STATE_INIT;
  2214. else
  2215. *state = DEV_STATE_UNINIT;
  2216. }
  2217. /*
  2218. * If we're not the Master PF then we need to wait around for the
  2219. * Master PF Driver to finish setting up the adapter.
  2220. *
  2221. * Note that we also do this wait if we're a non-Master-capable PF and
  2222. * there is no current Master PF; a Master PF may show up momentarily
  2223. * and we wouldn't want to fail pointlessly. (This can happen when an
  2224. * OS loads lots of different drivers rapidly at the same time). In
  2225. * this case, the Master PF returned by the firmware will be
  2226. * FW_PCIE_FW_MASTER_MASK so the test below will work ...
  2227. */
  2228. if ((v & (FW_HELLO_CMD_ERR|FW_HELLO_CMD_INIT)) == 0 &&
  2229. master_mbox != mbox) {
  2230. int waiting = FW_CMD_HELLO_TIMEOUT;
  2231. /*
  2232. * Wait for the firmware to either indicate an error or
  2233. * initialized state. If we see either of these we bail out
  2234. * and report the issue to the caller. If we exhaust the
  2235. * "hello timeout" and we haven't exhausted our retries, try
  2236. * again. Otherwise bail with a timeout error.
  2237. */
  2238. for (;;) {
  2239. u32 pcie_fw;
  2240. msleep(50);
  2241. waiting -= 50;
  2242. /*
  2243. * If neither Error nor Initialialized are indicated
  2244. * by the firmware keep waiting till we exaust our
  2245. * timeout ... and then retry if we haven't exhausted
  2246. * our retries ...
  2247. */
  2248. pcie_fw = t4_read_reg(adap, MA_PCIE_FW);
  2249. if (!(pcie_fw & (FW_PCIE_FW_ERR|FW_PCIE_FW_INIT))) {
  2250. if (waiting <= 0) {
  2251. if (retries-- > 0)
  2252. goto retry;
  2253. return -ETIMEDOUT;
  2254. }
  2255. continue;
  2256. }
  2257. /*
  2258. * We either have an Error or Initialized condition
  2259. * report errors preferentially.
  2260. */
  2261. if (state) {
  2262. if (pcie_fw & FW_PCIE_FW_ERR)
  2263. *state = DEV_STATE_ERR;
  2264. else if (pcie_fw & FW_PCIE_FW_INIT)
  2265. *state = DEV_STATE_INIT;
  2266. }
  2267. /*
  2268. * If we arrived before a Master PF was selected and
  2269. * there's not a valid Master PF, grab its identity
  2270. * for our caller.
  2271. */
  2272. if (master_mbox == FW_PCIE_FW_MASTER_MASK &&
  2273. (pcie_fw & FW_PCIE_FW_MASTER_VLD))
  2274. master_mbox = FW_PCIE_FW_MASTER_GET(pcie_fw);
  2275. break;
  2276. }
  2277. }
  2278. return master_mbox;
  2279. }
  2280. /**
  2281. * t4_fw_bye - end communication with FW
  2282. * @adap: the adapter
  2283. * @mbox: mailbox to use for the FW command
  2284. *
  2285. * Issues a command to terminate communication with FW.
  2286. */
  2287. int t4_fw_bye(struct adapter *adap, unsigned int mbox)
  2288. {
  2289. struct fw_bye_cmd c;
  2290. memset(&c, 0, sizeof(c));
  2291. INIT_CMD(c, BYE, WRITE);
  2292. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2293. }
  2294. /**
  2295. * t4_init_cmd - ask FW to initialize the device
  2296. * @adap: the adapter
  2297. * @mbox: mailbox to use for the FW command
  2298. *
  2299. * Issues a command to FW to partially initialize the device. This
  2300. * performs initialization that generally doesn't depend on user input.
  2301. */
  2302. int t4_early_init(struct adapter *adap, unsigned int mbox)
  2303. {
  2304. struct fw_initialize_cmd c;
  2305. memset(&c, 0, sizeof(c));
  2306. INIT_CMD(c, INITIALIZE, WRITE);
  2307. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2308. }
  2309. /**
  2310. * t4_fw_reset - issue a reset to FW
  2311. * @adap: the adapter
  2312. * @mbox: mailbox to use for the FW command
  2313. * @reset: specifies the type of reset to perform
  2314. *
  2315. * Issues a reset command of the specified type to FW.
  2316. */
  2317. int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset)
  2318. {
  2319. struct fw_reset_cmd c;
  2320. memset(&c, 0, sizeof(c));
  2321. INIT_CMD(c, RESET, WRITE);
  2322. c.val = htonl(reset);
  2323. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2324. }
  2325. /**
  2326. * t4_fw_halt - issue a reset/halt to FW and put uP into RESET
  2327. * @adap: the adapter
  2328. * @mbox: mailbox to use for the FW RESET command (if desired)
  2329. * @force: force uP into RESET even if FW RESET command fails
  2330. *
  2331. * Issues a RESET command to firmware (if desired) with a HALT indication
  2332. * and then puts the microprocessor into RESET state. The RESET command
  2333. * will only be issued if a legitimate mailbox is provided (mbox <=
  2334. * FW_PCIE_FW_MASTER_MASK).
  2335. *
  2336. * This is generally used in order for the host to safely manipulate the
  2337. * adapter without fear of conflicting with whatever the firmware might
  2338. * be doing. The only way out of this state is to RESTART the firmware
  2339. * ...
  2340. */
  2341. int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force)
  2342. {
  2343. int ret = 0;
  2344. /*
  2345. * If a legitimate mailbox is provided, issue a RESET command
  2346. * with a HALT indication.
  2347. */
  2348. if (mbox <= FW_PCIE_FW_MASTER_MASK) {
  2349. struct fw_reset_cmd c;
  2350. memset(&c, 0, sizeof(c));
  2351. INIT_CMD(c, RESET, WRITE);
  2352. c.val = htonl(PIORST | PIORSTMODE);
  2353. c.halt_pkd = htonl(FW_RESET_CMD_HALT(1U));
  2354. ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2355. }
  2356. /*
  2357. * Normally we won't complete the operation if the firmware RESET
  2358. * command fails but if our caller insists we'll go ahead and put the
  2359. * uP into RESET. This can be useful if the firmware is hung or even
  2360. * missing ... We'll have to take the risk of putting the uP into
  2361. * RESET without the cooperation of firmware in that case.
  2362. *
  2363. * We also force the firmware's HALT flag to be on in case we bypassed
  2364. * the firmware RESET command above or we're dealing with old firmware
  2365. * which doesn't have the HALT capability. This will serve as a flag
  2366. * for the incoming firmware to know that it's coming out of a HALT
  2367. * rather than a RESET ... if it's new enough to understand that ...
  2368. */
  2369. if (ret == 0 || force) {
  2370. t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, UPCRST);
  2371. t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT,
  2372. FW_PCIE_FW_HALT);
  2373. }
  2374. /*
  2375. * And we always return the result of the firmware RESET command
  2376. * even when we force the uP into RESET ...
  2377. */
  2378. return ret;
  2379. }
  2380. /**
  2381. * t4_fw_restart - restart the firmware by taking the uP out of RESET
  2382. * @adap: the adapter
  2383. * @reset: if we want to do a RESET to restart things
  2384. *
  2385. * Restart firmware previously halted by t4_fw_halt(). On successful
  2386. * return the previous PF Master remains as the new PF Master and there
  2387. * is no need to issue a new HELLO command, etc.
  2388. *
  2389. * We do this in two ways:
  2390. *
  2391. * 1. If we're dealing with newer firmware we'll simply want to take
  2392. * the chip's microprocessor out of RESET. This will cause the
  2393. * firmware to start up from its start vector. And then we'll loop
  2394. * until the firmware indicates it's started again (PCIE_FW.HALT
  2395. * reset to 0) or we timeout.
  2396. *
  2397. * 2. If we're dealing with older firmware then we'll need to RESET
  2398. * the chip since older firmware won't recognize the PCIE_FW.HALT
  2399. * flag and automatically RESET itself on startup.
  2400. */
  2401. int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset)
  2402. {
  2403. if (reset) {
  2404. /*
  2405. * Since we're directing the RESET instead of the firmware
  2406. * doing it automatically, we need to clear the PCIE_FW.HALT
  2407. * bit.
  2408. */
  2409. t4_set_reg_field(adap, PCIE_FW, FW_PCIE_FW_HALT, 0);
  2410. /*
  2411. * If we've been given a valid mailbox, first try to get the
  2412. * firmware to do the RESET. If that works, great and we can
  2413. * return success. Otherwise, if we haven't been given a
  2414. * valid mailbox or the RESET command failed, fall back to
  2415. * hitting the chip with a hammer.
  2416. */
  2417. if (mbox <= FW_PCIE_FW_MASTER_MASK) {
  2418. t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
  2419. msleep(100);
  2420. if (t4_fw_reset(adap, mbox,
  2421. PIORST | PIORSTMODE) == 0)
  2422. return 0;
  2423. }
  2424. t4_write_reg(adap, PL_RST, PIORST | PIORSTMODE);
  2425. msleep(2000);
  2426. } else {
  2427. int ms;
  2428. t4_set_reg_field(adap, CIM_BOOT_CFG, UPCRST, 0);
  2429. for (ms = 0; ms < FW_CMD_MAX_TIMEOUT; ) {
  2430. if (!(t4_read_reg(adap, PCIE_FW) & FW_PCIE_FW_HALT))
  2431. return 0;
  2432. msleep(100);
  2433. ms += 100;
  2434. }
  2435. return -ETIMEDOUT;
  2436. }
  2437. return 0;
  2438. }
  2439. /**
  2440. * t4_fw_upgrade - perform all of the steps necessary to upgrade FW
  2441. * @adap: the adapter
  2442. * @mbox: mailbox to use for the FW RESET command (if desired)
  2443. * @fw_data: the firmware image to write
  2444. * @size: image size
  2445. * @force: force upgrade even if firmware doesn't cooperate
  2446. *
  2447. * Perform all of the steps necessary for upgrading an adapter's
  2448. * firmware image. Normally this requires the cooperation of the
  2449. * existing firmware in order to halt all existing activities
  2450. * but if an invalid mailbox token is passed in we skip that step
  2451. * (though we'll still put the adapter microprocessor into RESET in
  2452. * that case).
  2453. *
  2454. * On successful return the new firmware will have been loaded and
  2455. * the adapter will have been fully RESET losing all previous setup
  2456. * state. On unsuccessful return the adapter may be completely hosed ...
  2457. * positive errno indicates that the adapter is ~probably~ intact, a
  2458. * negative errno indicates that things are looking bad ...
  2459. */
  2460. int t4_fw_upgrade(struct adapter *adap, unsigned int mbox,
  2461. const u8 *fw_data, unsigned int size, int force)
  2462. {
  2463. const struct fw_hdr *fw_hdr = (const struct fw_hdr *)fw_data;
  2464. int reset, ret;
  2465. ret = t4_fw_halt(adap, mbox, force);
  2466. if (ret < 0 && !force)
  2467. return ret;
  2468. ret = t4_load_fw(adap, fw_data, size);
  2469. if (ret < 0)
  2470. return ret;
  2471. /*
  2472. * Older versions of the firmware don't understand the new
  2473. * PCIE_FW.HALT flag and so won't know to perform a RESET when they
  2474. * restart. So for newly loaded older firmware we'll have to do the
  2475. * RESET for it so it starts up on a clean slate. We can tell if
  2476. * the newly loaded firmware will handle this right by checking
  2477. * its header flags to see if it advertises the capability.
  2478. */
  2479. reset = ((ntohl(fw_hdr->flags) & FW_HDR_FLAGS_RESET_HALT) == 0);
  2480. return t4_fw_restart(adap, mbox, reset);
  2481. }
  2482. /**
  2483. * t4_fw_config_file - setup an adapter via a Configuration File
  2484. * @adap: the adapter
  2485. * @mbox: mailbox to use for the FW command
  2486. * @mtype: the memory type where the Configuration File is located
  2487. * @maddr: the memory address where the Configuration File is located
  2488. * @finiver: return value for CF [fini] version
  2489. * @finicsum: return value for CF [fini] checksum
  2490. * @cfcsum: return value for CF computed checksum
  2491. *
  2492. * Issue a command to get the firmware to process the Configuration
  2493. * File located at the specified mtype/maddress. If the Configuration
  2494. * File is processed successfully and return value pointers are
  2495. * provided, the Configuration File "[fini] section version and
  2496. * checksum values will be returned along with the computed checksum.
  2497. * It's up to the caller to decide how it wants to respond to the
  2498. * checksums not matching but it recommended that a prominant warning
  2499. * be emitted in order to help people rapidly identify changed or
  2500. * corrupted Configuration Files.
  2501. *
  2502. * Also note that it's possible to modify things like "niccaps",
  2503. * "toecaps",etc. between processing the Configuration File and telling
  2504. * the firmware to use the new configuration. Callers which want to
  2505. * do this will need to "hand-roll" their own CAPS_CONFIGS commands for
  2506. * Configuration Files if they want to do this.
  2507. */
  2508. int t4_fw_config_file(struct adapter *adap, unsigned int mbox,
  2509. unsigned int mtype, unsigned int maddr,
  2510. u32 *finiver, u32 *finicsum, u32 *cfcsum)
  2511. {
  2512. struct fw_caps_config_cmd caps_cmd;
  2513. int ret;
  2514. /*
  2515. * Tell the firmware to process the indicated Configuration File.
  2516. * If there are no errors and the caller has provided return value
  2517. * pointers for the [fini] section version, checksum and computed
  2518. * checksum, pass those back to the caller.
  2519. */
  2520. memset(&caps_cmd, 0, sizeof(caps_cmd));
  2521. caps_cmd.op_to_write =
  2522. htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
  2523. FW_CMD_REQUEST |
  2524. FW_CMD_READ);
  2525. caps_cmd.cfvalid_to_len16 =
  2526. htonl(FW_CAPS_CONFIG_CMD_CFVALID |
  2527. FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
  2528. FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) |
  2529. FW_LEN16(caps_cmd));
  2530. ret = t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), &caps_cmd);
  2531. if (ret < 0)
  2532. return ret;
  2533. if (finiver)
  2534. *finiver = ntohl(caps_cmd.finiver);
  2535. if (finicsum)
  2536. *finicsum = ntohl(caps_cmd.finicsum);
  2537. if (cfcsum)
  2538. *cfcsum = ntohl(caps_cmd.cfcsum);
  2539. /*
  2540. * And now tell the firmware to use the configuration we just loaded.
  2541. */
  2542. caps_cmd.op_to_write =
  2543. htonl(FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
  2544. FW_CMD_REQUEST |
  2545. FW_CMD_WRITE);
  2546. caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd));
  2547. return t4_wr_mbox(adap, mbox, &caps_cmd, sizeof(caps_cmd), NULL);
  2548. }
  2549. /**
  2550. * t4_fixup_host_params - fix up host-dependent parameters
  2551. * @adap: the adapter
  2552. * @page_size: the host's Base Page Size
  2553. * @cache_line_size: the host's Cache Line Size
  2554. *
  2555. * Various registers in T4 contain values which are dependent on the
  2556. * host's Base Page and Cache Line Sizes. This function will fix all of
  2557. * those registers with the appropriate values as passed in ...
  2558. */
  2559. int t4_fixup_host_params(struct adapter *adap, unsigned int page_size,
  2560. unsigned int cache_line_size)
  2561. {
  2562. unsigned int page_shift = fls(page_size) - 1;
  2563. unsigned int sge_hps = page_shift - 10;
  2564. unsigned int stat_len = cache_line_size > 64 ? 128 : 64;
  2565. unsigned int fl_align = cache_line_size < 32 ? 32 : cache_line_size;
  2566. unsigned int fl_align_log = fls(fl_align) - 1;
  2567. t4_write_reg(adap, SGE_HOST_PAGE_SIZE,
  2568. HOSTPAGESIZEPF0(sge_hps) |
  2569. HOSTPAGESIZEPF1(sge_hps) |
  2570. HOSTPAGESIZEPF2(sge_hps) |
  2571. HOSTPAGESIZEPF3(sge_hps) |
  2572. HOSTPAGESIZEPF4(sge_hps) |
  2573. HOSTPAGESIZEPF5(sge_hps) |
  2574. HOSTPAGESIZEPF6(sge_hps) |
  2575. HOSTPAGESIZEPF7(sge_hps));
  2576. t4_set_reg_field(adap, SGE_CONTROL,
  2577. INGPADBOUNDARY_MASK |
  2578. EGRSTATUSPAGESIZE_MASK,
  2579. INGPADBOUNDARY(fl_align_log - 5) |
  2580. EGRSTATUSPAGESIZE(stat_len != 64));
  2581. /*
  2582. * Adjust various SGE Free List Host Buffer Sizes.
  2583. *
  2584. * This is something of a crock since we're using fixed indices into
  2585. * the array which are also known by the sge.c code and the T4
  2586. * Firmware Configuration File. We need to come up with a much better
  2587. * approach to managing this array. For now, the first four entries
  2588. * are:
  2589. *
  2590. * 0: Host Page Size
  2591. * 1: 64KB
  2592. * 2: Buffer size corresponding to 1500 byte MTU (unpacked mode)
  2593. * 3: Buffer size corresponding to 9000 byte MTU (unpacked mode)
  2594. *
  2595. * For the single-MTU buffers in unpacked mode we need to include
  2596. * space for the SGE Control Packet Shift, 14 byte Ethernet header,
  2597. * possible 4 byte VLAN tag, all rounded up to the next Ingress Packet
  2598. * Padding boundry. All of these are accommodated in the Factory
  2599. * Default Firmware Configuration File but we need to adjust it for
  2600. * this host's cache line size.
  2601. */
  2602. t4_write_reg(adap, SGE_FL_BUFFER_SIZE0, page_size);
  2603. t4_write_reg(adap, SGE_FL_BUFFER_SIZE2,
  2604. (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2) + fl_align-1)
  2605. & ~(fl_align-1));
  2606. t4_write_reg(adap, SGE_FL_BUFFER_SIZE3,
  2607. (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3) + fl_align-1)
  2608. & ~(fl_align-1));
  2609. t4_write_reg(adap, ULP_RX_TDDP_PSZ, HPZ0(page_shift - 12));
  2610. return 0;
  2611. }
  2612. /**
  2613. * t4_fw_initialize - ask FW to initialize the device
  2614. * @adap: the adapter
  2615. * @mbox: mailbox to use for the FW command
  2616. *
  2617. * Issues a command to FW to partially initialize the device. This
  2618. * performs initialization that generally doesn't depend on user input.
  2619. */
  2620. int t4_fw_initialize(struct adapter *adap, unsigned int mbox)
  2621. {
  2622. struct fw_initialize_cmd c;
  2623. memset(&c, 0, sizeof(c));
  2624. INIT_CMD(c, INITIALIZE, WRITE);
  2625. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2626. }
  2627. /**
  2628. * t4_query_params - query FW or device parameters
  2629. * @adap: the adapter
  2630. * @mbox: mailbox to use for the FW command
  2631. * @pf: the PF
  2632. * @vf: the VF
  2633. * @nparams: the number of parameters
  2634. * @params: the parameter names
  2635. * @val: the parameter values
  2636. *
  2637. * Reads the value of FW or device parameters. Up to 7 parameters can be
  2638. * queried at once.
  2639. */
  2640. int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
  2641. unsigned int vf, unsigned int nparams, const u32 *params,
  2642. u32 *val)
  2643. {
  2644. int i, ret;
  2645. struct fw_params_cmd c;
  2646. __be32 *p = &c.param[0].mnem;
  2647. if (nparams > 7)
  2648. return -EINVAL;
  2649. memset(&c, 0, sizeof(c));
  2650. c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
  2651. FW_CMD_READ | FW_PARAMS_CMD_PFN(pf) |
  2652. FW_PARAMS_CMD_VFN(vf));
  2653. c.retval_len16 = htonl(FW_LEN16(c));
  2654. for (i = 0; i < nparams; i++, p += 2)
  2655. *p = htonl(*params++);
  2656. ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
  2657. if (ret == 0)
  2658. for (i = 0, p = &c.param[0].val; i < nparams; i++, p += 2)
  2659. *val++ = ntohl(*p);
  2660. return ret;
  2661. }
  2662. /**
  2663. * t4_set_params - sets FW or device parameters
  2664. * @adap: the adapter
  2665. * @mbox: mailbox to use for the FW command
  2666. * @pf: the PF
  2667. * @vf: the VF
  2668. * @nparams: the number of parameters
  2669. * @params: the parameter names
  2670. * @val: the parameter values
  2671. *
  2672. * Sets the value of FW or device parameters. Up to 7 parameters can be
  2673. * specified at once.
  2674. */
  2675. int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf,
  2676. unsigned int vf, unsigned int nparams, const u32 *params,
  2677. const u32 *val)
  2678. {
  2679. struct fw_params_cmd c;
  2680. __be32 *p = &c.param[0].mnem;
  2681. if (nparams > 7)
  2682. return -EINVAL;
  2683. memset(&c, 0, sizeof(c));
  2684. c.op_to_vfn = htonl(FW_CMD_OP(FW_PARAMS_CMD) | FW_CMD_REQUEST |
  2685. FW_CMD_WRITE | FW_PARAMS_CMD_PFN(pf) |
  2686. FW_PARAMS_CMD_VFN(vf));
  2687. c.retval_len16 = htonl(FW_LEN16(c));
  2688. while (nparams--) {
  2689. *p++ = htonl(*params++);
  2690. *p++ = htonl(*val++);
  2691. }
  2692. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2693. }
  2694. /**
  2695. * t4_cfg_pfvf - configure PF/VF resource limits
  2696. * @adap: the adapter
  2697. * @mbox: mailbox to use for the FW command
  2698. * @pf: the PF being configured
  2699. * @vf: the VF being configured
  2700. * @txq: the max number of egress queues
  2701. * @txq_eth_ctrl: the max number of egress Ethernet or control queues
  2702. * @rxqi: the max number of interrupt-capable ingress queues
  2703. * @rxq: the max number of interruptless ingress queues
  2704. * @tc: the PCI traffic class
  2705. * @vi: the max number of virtual interfaces
  2706. * @cmask: the channel access rights mask for the PF/VF
  2707. * @pmask: the port access rights mask for the PF/VF
  2708. * @nexact: the maximum number of exact MPS filters
  2709. * @rcaps: read capabilities
  2710. * @wxcaps: write/execute capabilities
  2711. *
  2712. * Configures resource limits and capabilities for a physical or virtual
  2713. * function.
  2714. */
  2715. int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf,
  2716. unsigned int vf, unsigned int txq, unsigned int txq_eth_ctrl,
  2717. unsigned int rxqi, unsigned int rxq, unsigned int tc,
  2718. unsigned int vi, unsigned int cmask, unsigned int pmask,
  2719. unsigned int nexact, unsigned int rcaps, unsigned int wxcaps)
  2720. {
  2721. struct fw_pfvf_cmd c;
  2722. memset(&c, 0, sizeof(c));
  2723. c.op_to_vfn = htonl(FW_CMD_OP(FW_PFVF_CMD) | FW_CMD_REQUEST |
  2724. FW_CMD_WRITE | FW_PFVF_CMD_PFN(pf) |
  2725. FW_PFVF_CMD_VFN(vf));
  2726. c.retval_len16 = htonl(FW_LEN16(c));
  2727. c.niqflint_niq = htonl(FW_PFVF_CMD_NIQFLINT(rxqi) |
  2728. FW_PFVF_CMD_NIQ(rxq));
  2729. c.type_to_neq = htonl(FW_PFVF_CMD_CMASK(cmask) |
  2730. FW_PFVF_CMD_PMASK(pmask) |
  2731. FW_PFVF_CMD_NEQ(txq));
  2732. c.tc_to_nexactf = htonl(FW_PFVF_CMD_TC(tc) | FW_PFVF_CMD_NVI(vi) |
  2733. FW_PFVF_CMD_NEXACTF(nexact));
  2734. c.r_caps_to_nethctrl = htonl(FW_PFVF_CMD_R_CAPS(rcaps) |
  2735. FW_PFVF_CMD_WX_CAPS(wxcaps) |
  2736. FW_PFVF_CMD_NETHCTRL(txq_eth_ctrl));
  2737. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2738. }
  2739. /**
  2740. * t4_alloc_vi - allocate a virtual interface
  2741. * @adap: the adapter
  2742. * @mbox: mailbox to use for the FW command
  2743. * @port: physical port associated with the VI
  2744. * @pf: the PF owning the VI
  2745. * @vf: the VF owning the VI
  2746. * @nmac: number of MAC addresses needed (1 to 5)
  2747. * @mac: the MAC addresses of the VI
  2748. * @rss_size: size of RSS table slice associated with this VI
  2749. *
  2750. * Allocates a virtual interface for the given physical port. If @mac is
  2751. * not %NULL it contains the MAC addresses of the VI as assigned by FW.
  2752. * @mac should be large enough to hold @nmac Ethernet addresses, they are
  2753. * stored consecutively so the space needed is @nmac * 6 bytes.
  2754. * Returns a negative error number or the non-negative VI id.
  2755. */
  2756. int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port,
  2757. unsigned int pf, unsigned int vf, unsigned int nmac, u8 *mac,
  2758. unsigned int *rss_size)
  2759. {
  2760. int ret;
  2761. struct fw_vi_cmd c;
  2762. memset(&c, 0, sizeof(c));
  2763. c.op_to_vfn = htonl(FW_CMD_OP(FW_VI_CMD) | FW_CMD_REQUEST |
  2764. FW_CMD_WRITE | FW_CMD_EXEC |
  2765. FW_VI_CMD_PFN(pf) | FW_VI_CMD_VFN(vf));
  2766. c.alloc_to_len16 = htonl(FW_VI_CMD_ALLOC | FW_LEN16(c));
  2767. c.portid_pkd = FW_VI_CMD_PORTID(port);
  2768. c.nmac = nmac - 1;
  2769. ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
  2770. if (ret)
  2771. return ret;
  2772. if (mac) {
  2773. memcpy(mac, c.mac, sizeof(c.mac));
  2774. switch (nmac) {
  2775. case 5:
  2776. memcpy(mac + 24, c.nmac3, sizeof(c.nmac3));
  2777. case 4:
  2778. memcpy(mac + 18, c.nmac2, sizeof(c.nmac2));
  2779. case 3:
  2780. memcpy(mac + 12, c.nmac1, sizeof(c.nmac1));
  2781. case 2:
  2782. memcpy(mac + 6, c.nmac0, sizeof(c.nmac0));
  2783. }
  2784. }
  2785. if (rss_size)
  2786. *rss_size = FW_VI_CMD_RSSSIZE_GET(ntohs(c.rsssize_pkd));
  2787. return FW_VI_CMD_VIID_GET(ntohs(c.type_viid));
  2788. }
  2789. /**
  2790. * t4_set_rxmode - set Rx properties of a virtual interface
  2791. * @adap: the adapter
  2792. * @mbox: mailbox to use for the FW command
  2793. * @viid: the VI id
  2794. * @mtu: the new MTU or -1
  2795. * @promisc: 1 to enable promiscuous mode, 0 to disable it, -1 no change
  2796. * @all_multi: 1 to enable all-multi mode, 0 to disable it, -1 no change
  2797. * @bcast: 1 to enable broadcast Rx, 0 to disable it, -1 no change
  2798. * @vlanex: 1 to enable HW VLAN extraction, 0 to disable it, -1 no change
  2799. * @sleep_ok: if true we may sleep while awaiting command completion
  2800. *
  2801. * Sets Rx properties of a virtual interface.
  2802. */
  2803. int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid,
  2804. int mtu, int promisc, int all_multi, int bcast, int vlanex,
  2805. bool sleep_ok)
  2806. {
  2807. struct fw_vi_rxmode_cmd c;
  2808. /* convert to FW values */
  2809. if (mtu < 0)
  2810. mtu = FW_RXMODE_MTU_NO_CHG;
  2811. if (promisc < 0)
  2812. promisc = FW_VI_RXMODE_CMD_PROMISCEN_MASK;
  2813. if (all_multi < 0)
  2814. all_multi = FW_VI_RXMODE_CMD_ALLMULTIEN_MASK;
  2815. if (bcast < 0)
  2816. bcast = FW_VI_RXMODE_CMD_BROADCASTEN_MASK;
  2817. if (vlanex < 0)
  2818. vlanex = FW_VI_RXMODE_CMD_VLANEXEN_MASK;
  2819. memset(&c, 0, sizeof(c));
  2820. c.op_to_viid = htonl(FW_CMD_OP(FW_VI_RXMODE_CMD) | FW_CMD_REQUEST |
  2821. FW_CMD_WRITE | FW_VI_RXMODE_CMD_VIID(viid));
  2822. c.retval_len16 = htonl(FW_LEN16(c));
  2823. c.mtu_to_vlanexen = htonl(FW_VI_RXMODE_CMD_MTU(mtu) |
  2824. FW_VI_RXMODE_CMD_PROMISCEN(promisc) |
  2825. FW_VI_RXMODE_CMD_ALLMULTIEN(all_multi) |
  2826. FW_VI_RXMODE_CMD_BROADCASTEN(bcast) |
  2827. FW_VI_RXMODE_CMD_VLANEXEN(vlanex));
  2828. return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
  2829. }
  2830. /**
  2831. * t4_alloc_mac_filt - allocates exact-match filters for MAC addresses
  2832. * @adap: the adapter
  2833. * @mbox: mailbox to use for the FW command
  2834. * @viid: the VI id
  2835. * @free: if true any existing filters for this VI id are first removed
  2836. * @naddr: the number of MAC addresses to allocate filters for (up to 7)
  2837. * @addr: the MAC address(es)
  2838. * @idx: where to store the index of each allocated filter
  2839. * @hash: pointer to hash address filter bitmap
  2840. * @sleep_ok: call is allowed to sleep
  2841. *
  2842. * Allocates an exact-match filter for each of the supplied addresses and
  2843. * sets it to the corresponding address. If @idx is not %NULL it should
  2844. * have at least @naddr entries, each of which will be set to the index of
  2845. * the filter allocated for the corresponding MAC address. If a filter
  2846. * could not be allocated for an address its index is set to 0xffff.
  2847. * If @hash is not %NULL addresses that fail to allocate an exact filter
  2848. * are hashed and update the hash filter bitmap pointed at by @hash.
  2849. *
  2850. * Returns a negative error number or the number of filters allocated.
  2851. */
  2852. int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox,
  2853. unsigned int viid, bool free, unsigned int naddr,
  2854. const u8 **addr, u16 *idx, u64 *hash, bool sleep_ok)
  2855. {
  2856. int i, ret;
  2857. struct fw_vi_mac_cmd c;
  2858. struct fw_vi_mac_exact *p;
  2859. if (naddr > 7)
  2860. return -EINVAL;
  2861. memset(&c, 0, sizeof(c));
  2862. c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
  2863. FW_CMD_WRITE | (free ? FW_CMD_EXEC : 0) |
  2864. FW_VI_MAC_CMD_VIID(viid));
  2865. c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_FREEMACS(free) |
  2866. FW_CMD_LEN16((naddr + 2) / 2));
  2867. for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
  2868. p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
  2869. FW_VI_MAC_CMD_IDX(FW_VI_MAC_ADD_MAC));
  2870. memcpy(p->macaddr, addr[i], sizeof(p->macaddr));
  2871. }
  2872. ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok);
  2873. if (ret)
  2874. return ret;
  2875. for (i = 0, p = c.u.exact; i < naddr; i++, p++) {
  2876. u16 index = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
  2877. if (idx)
  2878. idx[i] = index >= NEXACT_MAC ? 0xffff : index;
  2879. if (index < NEXACT_MAC)
  2880. ret++;
  2881. else if (hash)
  2882. *hash |= (1ULL << hash_mac_addr(addr[i]));
  2883. }
  2884. return ret;
  2885. }
  2886. /**
  2887. * t4_change_mac - modifies the exact-match filter for a MAC address
  2888. * @adap: the adapter
  2889. * @mbox: mailbox to use for the FW command
  2890. * @viid: the VI id
  2891. * @idx: index of existing filter for old value of MAC address, or -1
  2892. * @addr: the new MAC address value
  2893. * @persist: whether a new MAC allocation should be persistent
  2894. * @add_smt: if true also add the address to the HW SMT
  2895. *
  2896. * Modifies an exact-match filter and sets it to the new MAC address.
  2897. * Note that in general it is not possible to modify the value of a given
  2898. * filter so the generic way to modify an address filter is to free the one
  2899. * being used by the old address value and allocate a new filter for the
  2900. * new address value. @idx can be -1 if the address is a new addition.
  2901. *
  2902. * Returns a negative error number or the index of the filter with the new
  2903. * MAC value.
  2904. */
  2905. int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid,
  2906. int idx, const u8 *addr, bool persist, bool add_smt)
  2907. {
  2908. int ret, mode;
  2909. struct fw_vi_mac_cmd c;
  2910. struct fw_vi_mac_exact *p = c.u.exact;
  2911. if (idx < 0) /* new allocation */
  2912. idx = persist ? FW_VI_MAC_ADD_PERSIST_MAC : FW_VI_MAC_ADD_MAC;
  2913. mode = add_smt ? FW_VI_MAC_SMT_AND_MPSTCAM : FW_VI_MAC_MPS_TCAM_ENTRY;
  2914. memset(&c, 0, sizeof(c));
  2915. c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
  2916. FW_CMD_WRITE | FW_VI_MAC_CMD_VIID(viid));
  2917. c.freemacs_to_len16 = htonl(FW_CMD_LEN16(1));
  2918. p->valid_to_idx = htons(FW_VI_MAC_CMD_VALID |
  2919. FW_VI_MAC_CMD_SMAC_RESULT(mode) |
  2920. FW_VI_MAC_CMD_IDX(idx));
  2921. memcpy(p->macaddr, addr, sizeof(p->macaddr));
  2922. ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
  2923. if (ret == 0) {
  2924. ret = FW_VI_MAC_CMD_IDX_GET(ntohs(p->valid_to_idx));
  2925. if (ret >= NEXACT_MAC)
  2926. ret = -ENOMEM;
  2927. }
  2928. return ret;
  2929. }
  2930. /**
  2931. * t4_set_addr_hash - program the MAC inexact-match hash filter
  2932. * @adap: the adapter
  2933. * @mbox: mailbox to use for the FW command
  2934. * @viid: the VI id
  2935. * @ucast: whether the hash filter should also match unicast addresses
  2936. * @vec: the value to be written to the hash filter
  2937. * @sleep_ok: call is allowed to sleep
  2938. *
  2939. * Sets the 64-bit inexact-match hash filter for a virtual interface.
  2940. */
  2941. int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid,
  2942. bool ucast, u64 vec, bool sleep_ok)
  2943. {
  2944. struct fw_vi_mac_cmd c;
  2945. memset(&c, 0, sizeof(c));
  2946. c.op_to_viid = htonl(FW_CMD_OP(FW_VI_MAC_CMD) | FW_CMD_REQUEST |
  2947. FW_CMD_WRITE | FW_VI_ENABLE_CMD_VIID(viid));
  2948. c.freemacs_to_len16 = htonl(FW_VI_MAC_CMD_HASHVECEN |
  2949. FW_VI_MAC_CMD_HASHUNIEN(ucast) |
  2950. FW_CMD_LEN16(1));
  2951. c.u.hash.hashvec = cpu_to_be64(vec);
  2952. return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok);
  2953. }
  2954. /**
  2955. * t4_enable_vi - enable/disable a virtual interface
  2956. * @adap: the adapter
  2957. * @mbox: mailbox to use for the FW command
  2958. * @viid: the VI id
  2959. * @rx_en: 1=enable Rx, 0=disable Rx
  2960. * @tx_en: 1=enable Tx, 0=disable Tx
  2961. *
  2962. * Enables/disables a virtual interface.
  2963. */
  2964. int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid,
  2965. bool rx_en, bool tx_en)
  2966. {
  2967. struct fw_vi_enable_cmd c;
  2968. memset(&c, 0, sizeof(c));
  2969. c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
  2970. FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
  2971. c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_IEN(rx_en) |
  2972. FW_VI_ENABLE_CMD_EEN(tx_en) | FW_LEN16(c));
  2973. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2974. }
  2975. /**
  2976. * t4_identify_port - identify a VI's port by blinking its LED
  2977. * @adap: the adapter
  2978. * @mbox: mailbox to use for the FW command
  2979. * @viid: the VI id
  2980. * @nblinks: how many times to blink LED at 2.5 Hz
  2981. *
  2982. * Identifies a VI's port by blinking its LED.
  2983. */
  2984. int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid,
  2985. unsigned int nblinks)
  2986. {
  2987. struct fw_vi_enable_cmd c;
  2988. memset(&c, 0, sizeof(c));
  2989. c.op_to_viid = htonl(FW_CMD_OP(FW_VI_ENABLE_CMD) | FW_CMD_REQUEST |
  2990. FW_CMD_EXEC | FW_VI_ENABLE_CMD_VIID(viid));
  2991. c.ien_to_len16 = htonl(FW_VI_ENABLE_CMD_LED | FW_LEN16(c));
  2992. c.blinkdur = htons(nblinks);
  2993. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  2994. }
  2995. /**
  2996. * t4_iq_free - free an ingress queue and its FLs
  2997. * @adap: the adapter
  2998. * @mbox: mailbox to use for the FW command
  2999. * @pf: the PF owning the queues
  3000. * @vf: the VF owning the queues
  3001. * @iqtype: the ingress queue type
  3002. * @iqid: ingress queue id
  3003. * @fl0id: FL0 queue id or 0xffff if no attached FL0
  3004. * @fl1id: FL1 queue id or 0xffff if no attached FL1
  3005. *
  3006. * Frees an ingress queue and its associated FLs, if any.
  3007. */
  3008. int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
  3009. unsigned int vf, unsigned int iqtype, unsigned int iqid,
  3010. unsigned int fl0id, unsigned int fl1id)
  3011. {
  3012. struct fw_iq_cmd c;
  3013. memset(&c, 0, sizeof(c));
  3014. c.op_to_vfn = htonl(FW_CMD_OP(FW_IQ_CMD) | FW_CMD_REQUEST |
  3015. FW_CMD_EXEC | FW_IQ_CMD_PFN(pf) |
  3016. FW_IQ_CMD_VFN(vf));
  3017. c.alloc_to_len16 = htonl(FW_IQ_CMD_FREE | FW_LEN16(c));
  3018. c.type_to_iqandstindex = htonl(FW_IQ_CMD_TYPE(iqtype));
  3019. c.iqid = htons(iqid);
  3020. c.fl0id = htons(fl0id);
  3021. c.fl1id = htons(fl1id);
  3022. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  3023. }
  3024. /**
  3025. * t4_eth_eq_free - free an Ethernet egress queue
  3026. * @adap: the adapter
  3027. * @mbox: mailbox to use for the FW command
  3028. * @pf: the PF owning the queue
  3029. * @vf: the VF owning the queue
  3030. * @eqid: egress queue id
  3031. *
  3032. * Frees an Ethernet egress queue.
  3033. */
  3034. int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
  3035. unsigned int vf, unsigned int eqid)
  3036. {
  3037. struct fw_eq_eth_cmd c;
  3038. memset(&c, 0, sizeof(c));
  3039. c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_ETH_CMD) | FW_CMD_REQUEST |
  3040. FW_CMD_EXEC | FW_EQ_ETH_CMD_PFN(pf) |
  3041. FW_EQ_ETH_CMD_VFN(vf));
  3042. c.alloc_to_len16 = htonl(FW_EQ_ETH_CMD_FREE | FW_LEN16(c));
  3043. c.eqid_pkd = htonl(FW_EQ_ETH_CMD_EQID(eqid));
  3044. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  3045. }
  3046. /**
  3047. * t4_ctrl_eq_free - free a control egress queue
  3048. * @adap: the adapter
  3049. * @mbox: mailbox to use for the FW command
  3050. * @pf: the PF owning the queue
  3051. * @vf: the VF owning the queue
  3052. * @eqid: egress queue id
  3053. *
  3054. * Frees a control egress queue.
  3055. */
  3056. int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
  3057. unsigned int vf, unsigned int eqid)
  3058. {
  3059. struct fw_eq_ctrl_cmd c;
  3060. memset(&c, 0, sizeof(c));
  3061. c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_CTRL_CMD) | FW_CMD_REQUEST |
  3062. FW_CMD_EXEC | FW_EQ_CTRL_CMD_PFN(pf) |
  3063. FW_EQ_CTRL_CMD_VFN(vf));
  3064. c.alloc_to_len16 = htonl(FW_EQ_CTRL_CMD_FREE | FW_LEN16(c));
  3065. c.cmpliqid_eqid = htonl(FW_EQ_CTRL_CMD_EQID(eqid));
  3066. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  3067. }
  3068. /**
  3069. * t4_ofld_eq_free - free an offload egress queue
  3070. * @adap: the adapter
  3071. * @mbox: mailbox to use for the FW command
  3072. * @pf: the PF owning the queue
  3073. * @vf: the VF owning the queue
  3074. * @eqid: egress queue id
  3075. *
  3076. * Frees a control egress queue.
  3077. */
  3078. int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf,
  3079. unsigned int vf, unsigned int eqid)
  3080. {
  3081. struct fw_eq_ofld_cmd c;
  3082. memset(&c, 0, sizeof(c));
  3083. c.op_to_vfn = htonl(FW_CMD_OP(FW_EQ_OFLD_CMD) | FW_CMD_REQUEST |
  3084. FW_CMD_EXEC | FW_EQ_OFLD_CMD_PFN(pf) |
  3085. FW_EQ_OFLD_CMD_VFN(vf));
  3086. c.alloc_to_len16 = htonl(FW_EQ_OFLD_CMD_FREE | FW_LEN16(c));
  3087. c.eqid_pkd = htonl(FW_EQ_OFLD_CMD_EQID(eqid));
  3088. return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
  3089. }
  3090. /**
  3091. * t4_handle_fw_rpl - process a FW reply message
  3092. * @adap: the adapter
  3093. * @rpl: start of the FW message
  3094. *
  3095. * Processes a FW message, such as link state change messages.
  3096. */
  3097. int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl)
  3098. {
  3099. u8 opcode = *(const u8 *)rpl;
  3100. if (opcode == FW_PORT_CMD) { /* link/module state change message */
  3101. int speed = 0, fc = 0;
  3102. const struct fw_port_cmd *p = (void *)rpl;
  3103. int chan = FW_PORT_CMD_PORTID_GET(ntohl(p->op_to_portid));
  3104. int port = adap->chan_map[chan];
  3105. struct port_info *pi = adap2pinfo(adap, port);
  3106. struct link_config *lc = &pi->link_cfg;
  3107. u32 stat = ntohl(p->u.info.lstatus_to_modtype);
  3108. int link_ok = (stat & FW_PORT_CMD_LSTATUS) != 0;
  3109. u32 mod = FW_PORT_CMD_MODTYPE_GET(stat);
  3110. if (stat & FW_PORT_CMD_RXPAUSE)
  3111. fc |= PAUSE_RX;
  3112. if (stat & FW_PORT_CMD_TXPAUSE)
  3113. fc |= PAUSE_TX;
  3114. if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_100M))
  3115. speed = SPEED_100;
  3116. else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_1G))
  3117. speed = SPEED_1000;
  3118. else if (stat & FW_PORT_CMD_LSPEED(FW_PORT_CAP_SPEED_10G))
  3119. speed = SPEED_10000;
  3120. if (link_ok != lc->link_ok || speed != lc->speed ||
  3121. fc != lc->fc) { /* something changed */
  3122. lc->link_ok = link_ok;
  3123. lc->speed = speed;
  3124. lc->fc = fc;
  3125. t4_os_link_changed(adap, port, link_ok);
  3126. }
  3127. if (mod != pi->mod_type) {
  3128. pi->mod_type = mod;
  3129. t4_os_portmod_changed(adap, port);
  3130. }
  3131. }
  3132. return 0;
  3133. }
  3134. static void get_pci_mode(struct adapter *adapter, struct pci_params *p)
  3135. {
  3136. u16 val;
  3137. if (pci_is_pcie(adapter->pdev)) {
  3138. pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
  3139. p->speed = val & PCI_EXP_LNKSTA_CLS;
  3140. p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
  3141. }
  3142. }
  3143. /**
  3144. * init_link_config - initialize a link's SW state
  3145. * @lc: structure holding the link state
  3146. * @caps: link capabilities
  3147. *
  3148. * Initializes the SW state maintained for each link, including the link's
  3149. * capabilities and default speed/flow-control/autonegotiation settings.
  3150. */
  3151. static void init_link_config(struct link_config *lc, unsigned int caps)
  3152. {
  3153. lc->supported = caps;
  3154. lc->requested_speed = 0;
  3155. lc->speed = 0;
  3156. lc->requested_fc = lc->fc = PAUSE_RX | PAUSE_TX;
  3157. if (lc->supported & FW_PORT_CAP_ANEG) {
  3158. lc->advertising = lc->supported & ADVERT_MASK;
  3159. lc->autoneg = AUTONEG_ENABLE;
  3160. lc->requested_fc |= PAUSE_AUTONEG;
  3161. } else {
  3162. lc->advertising = 0;
  3163. lc->autoneg = AUTONEG_DISABLE;
  3164. }
  3165. }
  3166. int t4_wait_dev_ready(struct adapter *adap)
  3167. {
  3168. if (t4_read_reg(adap, PL_WHOAMI) != 0xffffffff)
  3169. return 0;
  3170. msleep(500);
  3171. return t4_read_reg(adap, PL_WHOAMI) != 0xffffffff ? 0 : -EIO;
  3172. }
  3173. static int get_flash_params(struct adapter *adap)
  3174. {
  3175. int ret;
  3176. u32 info;
  3177. ret = sf1_write(adap, 1, 1, 0, SF_RD_ID);
  3178. if (!ret)
  3179. ret = sf1_read(adap, 3, 0, 1, &info);
  3180. t4_write_reg(adap, SF_OP, 0); /* unlock SF */
  3181. if (ret)
  3182. return ret;
  3183. if ((info & 0xff) != 0x20) /* not a Numonix flash */
  3184. return -EINVAL;
  3185. info >>= 16; /* log2 of size */
  3186. if (info >= 0x14 && info < 0x18)
  3187. adap->params.sf_nsec = 1 << (info - 16);
  3188. else if (info == 0x18)
  3189. adap->params.sf_nsec = 64;
  3190. else
  3191. return -EINVAL;
  3192. adap->params.sf_size = 1 << info;
  3193. adap->params.sf_fw_start =
  3194. t4_read_reg(adap, CIM_BOOT_CFG) & BOOTADDR_MASK;
  3195. return 0;
  3196. }
  3197. /**
  3198. * t4_prep_adapter - prepare SW and HW for operation
  3199. * @adapter: the adapter
  3200. * @reset: if true perform a HW reset
  3201. *
  3202. * Initialize adapter SW state for the various HW modules, set initial
  3203. * values for some adapter tunables, take PHYs out of reset, and
  3204. * initialize the MDIO interface.
  3205. */
  3206. int t4_prep_adapter(struct adapter *adapter)
  3207. {
  3208. int ret;
  3209. ret = t4_wait_dev_ready(adapter);
  3210. if (ret < 0)
  3211. return ret;
  3212. get_pci_mode(adapter, &adapter->params.pci);
  3213. adapter->params.rev = t4_read_reg(adapter, PL_REV);
  3214. ret = get_flash_params(adapter);
  3215. if (ret < 0) {
  3216. dev_err(adapter->pdev_dev, "error %d identifying flash\n", ret);
  3217. return ret;
  3218. }
  3219. init_cong_ctrl(adapter->params.a_wnd, adapter->params.b_wnd);
  3220. /*
  3221. * Default port for debugging in case we can't reach FW.
  3222. */
  3223. adapter->params.nports = 1;
  3224. adapter->params.portvec = 1;
  3225. adapter->params.vpd.cclk = 50000;
  3226. return 0;
  3227. }
  3228. int t4_port_init(struct adapter *adap, int mbox, int pf, int vf)
  3229. {
  3230. u8 addr[6];
  3231. int ret, i, j = 0;
  3232. struct fw_port_cmd c;
  3233. struct fw_rss_vi_config_cmd rvc;
  3234. memset(&c, 0, sizeof(c));
  3235. memset(&rvc, 0, sizeof(rvc));
  3236. for_each_port(adap, i) {
  3237. unsigned int rss_size;
  3238. struct port_info *p = adap2pinfo(adap, i);
  3239. while ((adap->params.portvec & (1 << j)) == 0)
  3240. j++;
  3241. c.op_to_portid = htonl(FW_CMD_OP(FW_PORT_CMD) |
  3242. FW_CMD_REQUEST | FW_CMD_READ |
  3243. FW_PORT_CMD_PORTID(j));
  3244. c.action_to_len16 = htonl(
  3245. FW_PORT_CMD_ACTION(FW_PORT_ACTION_GET_PORT_INFO) |
  3246. FW_LEN16(c));
  3247. ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c);
  3248. if (ret)
  3249. return ret;
  3250. ret = t4_alloc_vi(adap, mbox, j, pf, vf, 1, addr, &rss_size);
  3251. if (ret < 0)
  3252. return ret;
  3253. p->viid = ret;
  3254. p->tx_chan = j;
  3255. p->lport = j;
  3256. p->rss_size = rss_size;
  3257. memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN);
  3258. adap->port[i]->dev_id = j;
  3259. ret = ntohl(c.u.info.lstatus_to_modtype);
  3260. p->mdio_addr = (ret & FW_PORT_CMD_MDIOCAP) ?
  3261. FW_PORT_CMD_MDIOADDR_GET(ret) : -1;
  3262. p->port_type = FW_PORT_CMD_PTYPE_GET(ret);
  3263. p->mod_type = FW_PORT_MOD_TYPE_NA;
  3264. rvc.op_to_viid = htonl(FW_CMD_OP(FW_RSS_VI_CONFIG_CMD) |
  3265. FW_CMD_REQUEST | FW_CMD_READ |
  3266. FW_RSS_VI_CONFIG_CMD_VIID(p->viid));
  3267. rvc.retval_len16 = htonl(FW_LEN16(rvc));
  3268. ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc);
  3269. if (ret)
  3270. return ret;
  3271. p->rss_mode = ntohl(rvc.u.basicvirtual.defaultq_to_udpen);
  3272. init_link_config(&p->link_cfg, ntohs(c.u.info.pcap));
  3273. j++;
  3274. }
  3275. return 0;
  3276. }