mmu_context_32.h 1.4 KB

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  1. #ifndef ASM_X86__MMU_CONTEXT_32_H
  2. #define ASM_X86__MMU_CONTEXT_32_H
  3. static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
  4. {
  5. #ifdef CONFIG_SMP
  6. unsigned cpu = smp_processor_id();
  7. if (per_cpu(cpu_tlbstate, cpu).state == TLBSTATE_OK)
  8. per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_LAZY;
  9. #endif
  10. }
  11. static inline void switch_mm(struct mm_struct *prev,
  12. struct mm_struct *next,
  13. struct task_struct *tsk)
  14. {
  15. int cpu = smp_processor_id();
  16. if (likely(prev != next)) {
  17. /* stop flush ipis for the previous mm */
  18. cpu_clear(cpu, prev->cpu_vm_mask);
  19. #ifdef CONFIG_SMP
  20. per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK;
  21. per_cpu(cpu_tlbstate, cpu).active_mm = next;
  22. #endif
  23. cpu_set(cpu, next->cpu_vm_mask);
  24. /* Re-load page tables */
  25. load_cr3(next->pgd);
  26. /*
  27. * load the LDT, if the LDT is different:
  28. */
  29. if (unlikely(prev->context.ldt != next->context.ldt))
  30. load_LDT_nolock(&next->context);
  31. }
  32. #ifdef CONFIG_SMP
  33. else {
  34. per_cpu(cpu_tlbstate, cpu).state = TLBSTATE_OK;
  35. BUG_ON(per_cpu(cpu_tlbstate, cpu).active_mm != next);
  36. if (!cpu_test_and_set(cpu, next->cpu_vm_mask)) {
  37. /* We were in lazy tlb mode and leave_mm disabled
  38. * tlb flush IPI delivery. We must reload %cr3.
  39. */
  40. load_cr3(next->pgd);
  41. load_LDT_nolock(&next->context);
  42. }
  43. }
  44. #endif
  45. }
  46. #define deactivate_mm(tsk, mm) \
  47. asm("movl %0,%%gs": :"r" (0));
  48. #endif /* ASM_X86__MMU_CONTEXT_32_H */