mach_apic.h 4.5 KB

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  1. #ifndef ASM_X86__MACH_ES7000__MACH_APIC_H
  2. #define ASM_X86__MACH_ES7000__MACH_APIC_H
  3. #define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
  4. #define esr_disable (1)
  5. static inline int apic_id_registered(void)
  6. {
  7. return (1);
  8. }
  9. static inline cpumask_t target_cpus(void)
  10. {
  11. #if defined CONFIG_ES7000_CLUSTERED_APIC
  12. return CPU_MASK_ALL;
  13. #else
  14. return cpumask_of_cpu(smp_processor_id());
  15. #endif
  16. }
  17. #define TARGET_CPUS (target_cpus())
  18. #if defined CONFIG_ES7000_CLUSTERED_APIC
  19. #define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
  20. #define INT_DELIVERY_MODE (dest_LowestPrio)
  21. #define INT_DEST_MODE (1) /* logical delivery broadcast to all procs */
  22. #define NO_BALANCE_IRQ (1)
  23. #undef WAKE_SECONDARY_VIA_INIT
  24. #define WAKE_SECONDARY_VIA_MIP
  25. #else
  26. #define APIC_DFR_VALUE (APIC_DFR_FLAT)
  27. #define INT_DELIVERY_MODE (dest_Fixed)
  28. #define INT_DEST_MODE (0) /* phys delivery to target procs */
  29. #define NO_BALANCE_IRQ (0)
  30. #undef APIC_DEST_LOGICAL
  31. #define APIC_DEST_LOGICAL 0x0
  32. #define WAKE_SECONDARY_VIA_INIT
  33. #endif
  34. static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
  35. {
  36. return 0;
  37. }
  38. static inline unsigned long check_apicid_present(int bit)
  39. {
  40. return physid_isset(bit, phys_cpu_present_map);
  41. }
  42. #define apicid_cluster(apicid) (apicid & 0xF0)
  43. static inline unsigned long calculate_ldr(int cpu)
  44. {
  45. unsigned long id;
  46. id = xapic_phys_to_log_apicid(cpu);
  47. return (SET_APIC_LOGICAL_ID(id));
  48. }
  49. /*
  50. * Set up the logical destination ID.
  51. *
  52. * Intel recommends to set DFR, LdR and TPR before enabling
  53. * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
  54. * document number 292116). So here it goes...
  55. */
  56. static inline void init_apic_ldr(void)
  57. {
  58. unsigned long val;
  59. int cpu = smp_processor_id();
  60. apic_write(APIC_DFR, APIC_DFR_VALUE);
  61. val = calculate_ldr(cpu);
  62. apic_write(APIC_LDR, val);
  63. }
  64. #ifndef CONFIG_X86_GENERICARCH
  65. extern void enable_apic_mode(void);
  66. #endif
  67. extern int apic_version [MAX_APICS];
  68. static inline void setup_apic_routing(void)
  69. {
  70. int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
  71. printk("Enabling APIC mode: %s. Using %d I/O APICs, target cpus %lx\n",
  72. (apic_version[apic] == 0x14) ?
  73. "Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(TARGET_CPUS)[0]);
  74. }
  75. static inline int multi_timer_check(int apic, int irq)
  76. {
  77. return 0;
  78. }
  79. static inline int apicid_to_node(int logical_apicid)
  80. {
  81. return 0;
  82. }
  83. static inline int cpu_present_to_apicid(int mps_cpu)
  84. {
  85. if (!mps_cpu)
  86. return boot_cpu_physical_apicid;
  87. else if (mps_cpu < NR_CPUS)
  88. return (int) per_cpu(x86_bios_cpu_apicid, mps_cpu);
  89. else
  90. return BAD_APICID;
  91. }
  92. static inline physid_mask_t apicid_to_cpu_present(int phys_apicid)
  93. {
  94. static int id = 0;
  95. physid_mask_t mask;
  96. mask = physid_mask_of_physid(id);
  97. ++id;
  98. return mask;
  99. }
  100. extern u8 cpu_2_logical_apicid[];
  101. /* Mapping from cpu number to logical apicid */
  102. static inline int cpu_to_logical_apicid(int cpu)
  103. {
  104. #ifdef CONFIG_SMP
  105. if (cpu >= NR_CPUS)
  106. return BAD_APICID;
  107. return (int)cpu_2_logical_apicid[cpu];
  108. #else
  109. return logical_smp_processor_id();
  110. #endif
  111. }
  112. static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map)
  113. {
  114. /* For clustered we don't have a good way to do this yet - hack */
  115. return physids_promote(0xff);
  116. }
  117. static inline void setup_portio_remap(void)
  118. {
  119. }
  120. extern unsigned int boot_cpu_physical_apicid;
  121. static inline int check_phys_apicid_present(int cpu_physical_apicid)
  122. {
  123. boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
  124. return (1);
  125. }
  126. static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
  127. {
  128. int num_bits_set;
  129. int cpus_found = 0;
  130. int cpu;
  131. int apicid;
  132. num_bits_set = cpus_weight(cpumask);
  133. /* Return id to all */
  134. if (num_bits_set == NR_CPUS)
  135. #if defined CONFIG_ES7000_CLUSTERED_APIC
  136. return 0xFF;
  137. #else
  138. return cpu_to_logical_apicid(0);
  139. #endif
  140. /*
  141. * The cpus in the mask must all be on the apic cluster. If are not
  142. * on the same apicid cluster return default value of TARGET_CPUS.
  143. */
  144. cpu = first_cpu(cpumask);
  145. apicid = cpu_to_logical_apicid(cpu);
  146. while (cpus_found < num_bits_set) {
  147. if (cpu_isset(cpu, cpumask)) {
  148. int new_apicid = cpu_to_logical_apicid(cpu);
  149. if (apicid_cluster(apicid) !=
  150. apicid_cluster(new_apicid)){
  151. printk ("%s: Not a valid mask!\n",__FUNCTION__);
  152. #if defined CONFIG_ES7000_CLUSTERED_APIC
  153. return 0xFF;
  154. #else
  155. return cpu_to_logical_apicid(0);
  156. #endif
  157. }
  158. apicid = new_apicid;
  159. cpus_found++;
  160. }
  161. cpu++;
  162. }
  163. return apicid;
  164. }
  165. static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
  166. {
  167. return cpuid_apic >> index_msb;
  168. }
  169. #endif /* ASM_X86__MACH_ES7000__MACH_APIC_H */