omap_wdt.c 9.2 KB

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  1. /*
  2. * linux/drivers/char/watchdog/omap_wdt.c
  3. *
  4. * Watchdog driver for the TI OMAP 16xx & 24xx 32KHz (non-secure) watchdog
  5. *
  6. * Author: MontaVista Software, Inc.
  7. * <gdavis@mvista.com> or <source@mvista.com>
  8. *
  9. * 2003 (c) MontaVista Software, Inc. This file is licensed under the
  10. * terms of the GNU General Public License version 2. This program is
  11. * licensed "as is" without any warranty of any kind, whether express
  12. * or implied.
  13. *
  14. * History:
  15. *
  16. * 20030527: George G. Davis <gdavis@mvista.com>
  17. * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
  18. * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
  19. * Based on SoftDog driver by Alan Cox <alan@redhat.com>
  20. *
  21. * Copyright (c) 2004 Texas Instruments.
  22. * 1. Modified to support OMAP1610 32-KHz watchdog timer
  23. * 2. Ported to 2.6 kernel
  24. *
  25. * Copyright (c) 2005 David Brownell
  26. * Use the driver model and standard identifiers; handle bigger timeouts.
  27. */
  28. #include <linux/module.h>
  29. #include <linux/types.h>
  30. #include <linux/kernel.h>
  31. #include <linux/fs.h>
  32. #include <linux/mm.h>
  33. #include <linux/miscdevice.h>
  34. #include <linux/watchdog.h>
  35. #include <linux/reboot.h>
  36. #include <linux/init.h>
  37. #include <linux/err.h>
  38. #include <linux/platform_device.h>
  39. #include <linux/moduleparam.h>
  40. #include <linux/clk.h>
  41. #include <linux/bitops.h>
  42. #include <linux/io.h>
  43. #include <linux/uaccess.h>
  44. #include <mach/hardware.h>
  45. #include <mach/prcm.h>
  46. #include "omap_wdt.h"
  47. static unsigned timer_margin;
  48. module_param(timer_margin, uint, 0);
  49. MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
  50. static int omap_wdt_users;
  51. static struct clk *armwdt_ck;
  52. static struct clk *mpu_wdt_ick;
  53. static struct clk *mpu_wdt_fck;
  54. static unsigned int wdt_trgr_pattern = 0x1234;
  55. static spinlock_t wdt_lock;
  56. static void omap_wdt_ping(void)
  57. {
  58. /* wait for posted write to complete */
  59. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
  60. cpu_relax();
  61. wdt_trgr_pattern = ~wdt_trgr_pattern;
  62. omap_writel(wdt_trgr_pattern, (OMAP_WATCHDOG_TGR));
  63. /* wait for posted write to complete */
  64. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x08)
  65. cpu_relax();
  66. /* reloaded WCRR from WLDR */
  67. }
  68. static void omap_wdt_enable(void)
  69. {
  70. /* Sequence to enable the watchdog */
  71. omap_writel(0xBBBB, OMAP_WATCHDOG_SPR);
  72. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
  73. cpu_relax();
  74. omap_writel(0x4444, OMAP_WATCHDOG_SPR);
  75. while ((omap_readl(OMAP_WATCHDOG_WPS)) & 0x10)
  76. cpu_relax();
  77. }
  78. static void omap_wdt_disable(void)
  79. {
  80. /* sequence required to disable watchdog */
  81. omap_writel(0xAAAA, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  82. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
  83. cpu_relax();
  84. omap_writel(0x5555, OMAP_WATCHDOG_SPR); /* TIMER_MODE */
  85. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x10)
  86. cpu_relax();
  87. }
  88. static void omap_wdt_adjust_timeout(unsigned new_timeout)
  89. {
  90. if (new_timeout < TIMER_MARGIN_MIN)
  91. new_timeout = TIMER_MARGIN_DEFAULT;
  92. if (new_timeout > TIMER_MARGIN_MAX)
  93. new_timeout = TIMER_MARGIN_MAX;
  94. timer_margin = new_timeout;
  95. }
  96. static void omap_wdt_set_timeout(void)
  97. {
  98. u32 pre_margin = GET_WLDR_VAL(timer_margin);
  99. /* just count up at 32 KHz */
  100. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
  101. cpu_relax();
  102. omap_writel(pre_margin, OMAP_WATCHDOG_LDR);
  103. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x04)
  104. cpu_relax();
  105. }
  106. /*
  107. * Allow only one task to hold it open
  108. */
  109. static int omap_wdt_open(struct inode *inode, struct file *file)
  110. {
  111. if (test_and_set_bit(1, (unsigned long *)&omap_wdt_users))
  112. return -EBUSY;
  113. if (cpu_is_omap16xx())
  114. clk_enable(armwdt_ck); /* Enable the clock */
  115. if (cpu_is_omap24xx()) {
  116. clk_enable(mpu_wdt_ick); /* Enable the interface clock */
  117. clk_enable(mpu_wdt_fck); /* Enable the functional clock */
  118. }
  119. /* initialize prescaler */
  120. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
  121. cpu_relax();
  122. omap_writel((1 << 5) | (PTV << 2), OMAP_WATCHDOG_CNTRL);
  123. while (omap_readl(OMAP_WATCHDOG_WPS) & 0x01)
  124. cpu_relax();
  125. omap_wdt_set_timeout();
  126. omap_wdt_enable();
  127. return nonseekable_open(inode, file);
  128. }
  129. static int omap_wdt_release(struct inode *inode, struct file *file)
  130. {
  131. /*
  132. * Shut off the timer unless NOWAYOUT is defined.
  133. */
  134. #ifndef CONFIG_WATCHDOG_NOWAYOUT
  135. omap_wdt_disable();
  136. if (cpu_is_omap16xx()) {
  137. clk_disable(armwdt_ck); /* Disable the clock */
  138. clk_put(armwdt_ck);
  139. armwdt_ck = NULL;
  140. }
  141. if (cpu_is_omap24xx()) {
  142. clk_disable(mpu_wdt_ick); /* Disable the clock */
  143. clk_disable(mpu_wdt_fck); /* Disable the clock */
  144. clk_put(mpu_wdt_ick);
  145. clk_put(mpu_wdt_fck);
  146. mpu_wdt_ick = NULL;
  147. mpu_wdt_fck = NULL;
  148. }
  149. #else
  150. printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
  151. #endif
  152. omap_wdt_users = 0;
  153. return 0;
  154. }
  155. static ssize_t omap_wdt_write(struct file *file, const char __user *data,
  156. size_t len, loff_t *ppos)
  157. {
  158. /* Refresh LOAD_TIME. */
  159. if (len) {
  160. spin_lock(&wdt_lock);
  161. omap_wdt_ping();
  162. spin_unlock(&wdt_lock);
  163. }
  164. return len;
  165. }
  166. static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
  167. unsigned long arg)
  168. {
  169. int new_margin;
  170. static const struct watchdog_info ident = {
  171. .identity = "OMAP Watchdog",
  172. .options = WDIOF_SETTIMEOUT,
  173. .firmware_version = 0,
  174. };
  175. switch (cmd) {
  176. case WDIOC_GETSUPPORT:
  177. return copy_to_user((struct watchdog_info __user *)arg, &ident,
  178. sizeof(ident));
  179. case WDIOC_GETSTATUS:
  180. return put_user(0, (int __user *)arg);
  181. case WDIOC_GETBOOTSTATUS:
  182. if (cpu_is_omap16xx())
  183. return put_user(omap_readw(ARM_SYSST),
  184. (int __user *)arg);
  185. if (cpu_is_omap24xx())
  186. return put_user(omap_prcm_get_reset_sources(),
  187. (int __user *)arg);
  188. case WDIOC_KEEPALIVE:
  189. spin_lock(&wdt_lock);
  190. omap_wdt_ping();
  191. spin_unlock(&wdt_lock);
  192. return 0;
  193. case WDIOC_SETTIMEOUT:
  194. if (get_user(new_margin, (int __user *)arg))
  195. return -EFAULT;
  196. omap_wdt_adjust_timeout(new_margin);
  197. spin_lock(&wdt_lock);
  198. omap_wdt_disable();
  199. omap_wdt_set_timeout();
  200. omap_wdt_enable();
  201. omap_wdt_ping();
  202. spin_unlock(&wdt_lock);
  203. /* Fall */
  204. case WDIOC_GETTIMEOUT:
  205. return put_user(timer_margin, (int __user *)arg);
  206. default:
  207. return -ENOTTY;
  208. }
  209. }
  210. static const struct file_operations omap_wdt_fops = {
  211. .owner = THIS_MODULE,
  212. .write = omap_wdt_write,
  213. .unlocked_ioctl = omap_wdt_ioctl,
  214. .open = omap_wdt_open,
  215. .release = omap_wdt_release,
  216. };
  217. static struct miscdevice omap_wdt_miscdev = {
  218. .minor = WATCHDOG_MINOR,
  219. .name = "watchdog",
  220. .fops = &omap_wdt_fops,
  221. };
  222. static int __init omap_wdt_probe(struct platform_device *pdev)
  223. {
  224. struct resource *res, *mem;
  225. int ret;
  226. /* reserve static register mappings */
  227. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  228. if (!res)
  229. return -ENOENT;
  230. mem = request_mem_region(res->start, res->end - res->start + 1,
  231. pdev->name);
  232. if (mem == NULL)
  233. return -EBUSY;
  234. platform_set_drvdata(pdev, mem);
  235. omap_wdt_users = 0;
  236. if (cpu_is_omap16xx()) {
  237. armwdt_ck = clk_get(&pdev->dev, "armwdt_ck");
  238. if (IS_ERR(armwdt_ck)) {
  239. ret = PTR_ERR(armwdt_ck);
  240. armwdt_ck = NULL;
  241. goto fail;
  242. }
  243. }
  244. if (cpu_is_omap24xx()) {
  245. mpu_wdt_ick = clk_get(&pdev->dev, "mpu_wdt_ick");
  246. if (IS_ERR(mpu_wdt_ick)) {
  247. ret = PTR_ERR(mpu_wdt_ick);
  248. mpu_wdt_ick = NULL;
  249. goto fail;
  250. }
  251. mpu_wdt_fck = clk_get(&pdev->dev, "mpu_wdt_fck");
  252. if (IS_ERR(mpu_wdt_fck)) {
  253. ret = PTR_ERR(mpu_wdt_fck);
  254. mpu_wdt_fck = NULL;
  255. goto fail;
  256. }
  257. }
  258. omap_wdt_disable();
  259. omap_wdt_adjust_timeout(timer_margin);
  260. omap_wdt_miscdev.parent = &pdev->dev;
  261. ret = misc_register(&omap_wdt_miscdev);
  262. if (ret)
  263. goto fail;
  264. pr_info("OMAP Watchdog Timer: initial timeout %d sec\n", timer_margin);
  265. /* autogate OCP interface clock */
  266. omap_writel(0x01, OMAP_WATCHDOG_SYS_CONFIG);
  267. return 0;
  268. fail:
  269. if (armwdt_ck)
  270. clk_put(armwdt_ck);
  271. if (mpu_wdt_ick)
  272. clk_put(mpu_wdt_ick);
  273. if (mpu_wdt_fck)
  274. clk_put(mpu_wdt_fck);
  275. release_resource(mem);
  276. return ret;
  277. }
  278. static void omap_wdt_shutdown(struct platform_device *pdev)
  279. {
  280. omap_wdt_disable();
  281. }
  282. static int omap_wdt_remove(struct platform_device *pdev)
  283. {
  284. struct resource *mem = platform_get_drvdata(pdev);
  285. misc_deregister(&omap_wdt_miscdev);
  286. release_resource(mem);
  287. if (armwdt_ck)
  288. clk_put(armwdt_ck);
  289. if (mpu_wdt_ick)
  290. clk_put(mpu_wdt_ick);
  291. if (mpu_wdt_fck)
  292. clk_put(mpu_wdt_fck);
  293. return 0;
  294. }
  295. #ifdef CONFIG_PM
  296. /* REVISIT ... not clear this is the best way to handle system suspend; and
  297. * it's very inappropriate for selective device suspend (e.g. suspending this
  298. * through sysfs rather than by stopping the watchdog daemon). Also, this
  299. * may not play well enough with NOWAYOUT...
  300. */
  301. static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
  302. {
  303. if (omap_wdt_users)
  304. omap_wdt_disable();
  305. return 0;
  306. }
  307. static int omap_wdt_resume(struct platform_device *pdev)
  308. {
  309. if (omap_wdt_users) {
  310. omap_wdt_enable();
  311. omap_wdt_ping();
  312. }
  313. return 0;
  314. }
  315. #else
  316. #define omap_wdt_suspend NULL
  317. #define omap_wdt_resume NULL
  318. #endif
  319. static struct platform_driver omap_wdt_driver = {
  320. .probe = omap_wdt_probe,
  321. .remove = omap_wdt_remove,
  322. .shutdown = omap_wdt_shutdown,
  323. .suspend = omap_wdt_suspend,
  324. .resume = omap_wdt_resume,
  325. .driver = {
  326. .owner = THIS_MODULE,
  327. .name = "omap_wdt",
  328. },
  329. };
  330. static int __init omap_wdt_init(void)
  331. {
  332. spin_lock_init(&wdt_lock);
  333. return platform_driver_register(&omap_wdt_driver);
  334. }
  335. static void __exit omap_wdt_exit(void)
  336. {
  337. platform_driver_unregister(&omap_wdt_driver);
  338. }
  339. module_init(omap_wdt_init);
  340. module_exit(omap_wdt_exit);
  341. MODULE_AUTHOR("George G. Davis");
  342. MODULE_LICENSE("GPL");
  343. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  344. MODULE_ALIAS("platform:omap_wdt");