davinci_wdt.c 6.5 KB

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  1. /*
  2. * drivers/char/watchdog/davinci_wdt.c
  3. *
  4. * Watchdog driver for DaVinci DM644x/DM646x processors
  5. *
  6. * Copyright (C) 2006 Texas Instruments.
  7. *
  8. * 2007 (c) MontaVista Software, Inc. This file is licensed under
  9. * the terms of the GNU General Public License version 2. This program
  10. * is licensed "as is" without any warranty of any kind, whether express
  11. * or implied.
  12. */
  13. #include <linux/module.h>
  14. #include <linux/moduleparam.h>
  15. #include <linux/types.h>
  16. #include <linux/kernel.h>
  17. #include <linux/fs.h>
  18. #include <linux/miscdevice.h>
  19. #include <linux/watchdog.h>
  20. #include <linux/init.h>
  21. #include <linux/bitops.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/spinlock.h>
  24. #include <linux/uaccess.h>
  25. #include <linux/io.h>
  26. #include <mach/hardware.h>
  27. #define MODULE_NAME "DAVINCI-WDT: "
  28. #define DEFAULT_HEARTBEAT 60
  29. #define MAX_HEARTBEAT 600 /* really the max margin is 264/27MHz*/
  30. /* Timer register set definition */
  31. #define PID12 (0x0)
  32. #define EMUMGT (0x4)
  33. #define TIM12 (0x10)
  34. #define TIM34 (0x14)
  35. #define PRD12 (0x18)
  36. #define PRD34 (0x1C)
  37. #define TCR (0x20)
  38. #define TGCR (0x24)
  39. #define WDTCR (0x28)
  40. /* TCR bit definitions */
  41. #define ENAMODE12_DISABLED (0 << 6)
  42. #define ENAMODE12_ONESHOT (1 << 6)
  43. #define ENAMODE12_PERIODIC (2 << 6)
  44. /* TGCR bit definitions */
  45. #define TIM12RS_UNRESET (1 << 0)
  46. #define TIM34RS_UNRESET (1 << 1)
  47. #define TIMMODE_64BIT_WDOG (2 << 2)
  48. /* WDTCR bit definitions */
  49. #define WDEN (1 << 14)
  50. #define WDFLAG (1 << 15)
  51. #define WDKEY_SEQ0 (0xa5c6 << 16)
  52. #define WDKEY_SEQ1 (0xda7e << 16)
  53. static int heartbeat = DEFAULT_HEARTBEAT;
  54. static DEFINE_SPINLOCK(io_lock);
  55. static unsigned long wdt_status;
  56. #define WDT_IN_USE 0
  57. #define WDT_OK_TO_CLOSE 1
  58. #define WDT_REGION_INITED 2
  59. #define WDT_DEVICE_INITED 3
  60. static struct resource *wdt_mem;
  61. static void __iomem *wdt_base;
  62. static void wdt_service(void)
  63. {
  64. spin_lock(&io_lock);
  65. /* put watchdog in service state */
  66. davinci_writel(WDKEY_SEQ0, wdt_base + WDTCR);
  67. /* put watchdog in active state */
  68. davinci_writel(WDKEY_SEQ1, wdt_base + WDTCR);
  69. spin_unlock(&io_lock);
  70. }
  71. static void wdt_enable(void)
  72. {
  73. u32 tgcr;
  74. u32 timer_margin;
  75. spin_lock(&io_lock);
  76. /* disable, internal clock source */
  77. davinci_writel(0, wdt_base + TCR);
  78. /* reset timer, set mode to 64-bit watchdog, and unreset */
  79. davinci_writel(0, wdt_base + TGCR);
  80. tgcr = TIMMODE_64BIT_WDOG | TIM12RS_UNRESET | TIM34RS_UNRESET;
  81. davinci_writel(tgcr, wdt_base + TGCR);
  82. /* clear counter regs */
  83. davinci_writel(0, wdt_base + TIM12);
  84. davinci_writel(0, wdt_base + TIM34);
  85. /* set timeout period */
  86. timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) & 0xffffffff);
  87. davinci_writel(timer_margin, wdt_base + PRD12);
  88. timer_margin = (((u64)heartbeat * CLOCK_TICK_RATE) >> 32);
  89. davinci_writel(timer_margin, wdt_base + PRD34);
  90. /* enable run continuously */
  91. davinci_writel(ENAMODE12_PERIODIC, wdt_base + TCR);
  92. /* Once the WDT is in pre-active state write to
  93. * TIM12, TIM34, PRD12, PRD34, TCR, TGCR, WDTCR are
  94. * write protected (except for the WDKEY field)
  95. */
  96. /* put watchdog in pre-active state */
  97. davinci_writel(WDKEY_SEQ0 | WDEN, wdt_base + WDTCR);
  98. /* put watchdog in active state */
  99. davinci_writel(WDKEY_SEQ1 | WDEN, wdt_base + WDTCR);
  100. spin_unlock(&io_lock);
  101. }
  102. static int davinci_wdt_open(struct inode *inode, struct file *file)
  103. {
  104. if (test_and_set_bit(WDT_IN_USE, &wdt_status))
  105. return -EBUSY;
  106. wdt_enable();
  107. return nonseekable_open(inode, file);
  108. }
  109. static ssize_t
  110. davinci_wdt_write(struct file *file, const char *data, size_t len,
  111. loff_t *ppos)
  112. {
  113. if (len)
  114. wdt_service();
  115. return len;
  116. }
  117. static struct watchdog_info ident = {
  118. .options = WDIOF_KEEPALIVEPING,
  119. .identity = "DaVinci Watchdog",
  120. };
  121. static long davinci_wdt_ioctl(struct file *file,
  122. unsigned int cmd, unsigned long arg)
  123. {
  124. int ret = -ENOTTY;
  125. switch (cmd) {
  126. case WDIOC_GETSUPPORT:
  127. ret = copy_to_user((struct watchdog_info *)arg, &ident,
  128. sizeof(ident)) ? -EFAULT : 0;
  129. break;
  130. case WDIOC_GETSTATUS:
  131. case WDIOC_GETBOOTSTATUS:
  132. ret = put_user(0, (int *)arg);
  133. break;
  134. case WDIOC_KEEPALIVE:
  135. wdt_service();
  136. ret = 0;
  137. break;
  138. case WDIOC_GETTIMEOUT:
  139. ret = put_user(heartbeat, (int *)arg);
  140. break;
  141. }
  142. return ret;
  143. }
  144. static int davinci_wdt_release(struct inode *inode, struct file *file)
  145. {
  146. wdt_service();
  147. clear_bit(WDT_IN_USE, &wdt_status);
  148. return 0;
  149. }
  150. static const struct file_operations davinci_wdt_fops = {
  151. .owner = THIS_MODULE,
  152. .llseek = no_llseek,
  153. .write = davinci_wdt_write,
  154. .unlocked_ioctl = davinci_wdt_ioctl,
  155. .open = davinci_wdt_open,
  156. .release = davinci_wdt_release,
  157. };
  158. static struct miscdevice davinci_wdt_miscdev = {
  159. .minor = WATCHDOG_MINOR,
  160. .name = "watchdog",
  161. .fops = &davinci_wdt_fops,
  162. };
  163. static int davinci_wdt_probe(struct platform_device *pdev)
  164. {
  165. int ret = 0, size;
  166. struct resource *res;
  167. if (heartbeat < 1 || heartbeat > MAX_HEARTBEAT)
  168. heartbeat = DEFAULT_HEARTBEAT;
  169. printk(KERN_INFO MODULE_NAME
  170. "DaVinci Watchdog Timer: heartbeat %d sec\n", heartbeat);
  171. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  172. if (res == NULL) {
  173. printk(KERN_INFO MODULE_NAME
  174. "failed to get memory region resource\n");
  175. return -ENOENT;
  176. }
  177. size = res->end - res->start + 1;
  178. wdt_mem = request_mem_region(res->start, size, pdev->name);
  179. if (wdt_mem == NULL) {
  180. printk(KERN_INFO MODULE_NAME "failed to get memory region\n");
  181. return -ENOENT;
  182. }
  183. wdt_base = (void __iomem *)(res->start);
  184. ret = misc_register(&davinci_wdt_miscdev);
  185. if (ret < 0) {
  186. printk(KERN_ERR MODULE_NAME "cannot register misc device\n");
  187. release_resource(wdt_mem);
  188. kfree(wdt_mem);
  189. } else {
  190. set_bit(WDT_DEVICE_INITED, &wdt_status);
  191. }
  192. return ret;
  193. }
  194. static int davinci_wdt_remove(struct platform_device *pdev)
  195. {
  196. misc_deregister(&davinci_wdt_miscdev);
  197. if (wdt_mem) {
  198. release_resource(wdt_mem);
  199. kfree(wdt_mem);
  200. wdt_mem = NULL;
  201. }
  202. return 0;
  203. }
  204. static struct platform_driver platform_wdt_driver = {
  205. .driver = {
  206. .name = "watchdog",
  207. .owner = THIS_MODULE,
  208. },
  209. .probe = davinci_wdt_probe,
  210. .remove = davinci_wdt_remove,
  211. };
  212. static int __init davinci_wdt_init(void)
  213. {
  214. return platform_driver_register(&platform_wdt_driver);
  215. }
  216. static void __exit davinci_wdt_exit(void)
  217. {
  218. platform_driver_unregister(&platform_wdt_driver);
  219. }
  220. module_init(davinci_wdt_init);
  221. module_exit(davinci_wdt_exit);
  222. MODULE_AUTHOR("Texas Instruments");
  223. MODULE_DESCRIPTION("DaVinci Watchdog Driver");
  224. module_param(heartbeat, int, 0);
  225. MODULE_PARM_DESC(heartbeat,
  226. "Watchdog heartbeat period in seconds from 1 to "
  227. __MODULE_STRING(MAX_HEARTBEAT) ", default "
  228. __MODULE_STRING(DEFAULT_HEARTBEAT));
  229. MODULE_LICENSE("GPL");
  230. MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
  231. MODULE_ALIAS("platform:watchdog");