musb_gadget_ep0.c 24 KB

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  1. /*
  2. * MUSB OTG peripheral driver ep0 handling
  3. *
  4. * Copyright 2005 Mentor Graphics Corporation
  5. * Copyright (C) 2005-2006 by Texas Instruments
  6. * Copyright (C) 2006-2007 Nokia Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. *
  22. * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  23. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25. * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. */
  34. #include <linux/kernel.h>
  35. #include <linux/list.h>
  36. #include <linux/timer.h>
  37. #include <linux/spinlock.h>
  38. #include <linux/init.h>
  39. #include <linux/device.h>
  40. #include <linux/interrupt.h>
  41. #include "musb_core.h"
  42. /* ep0 is always musb->endpoints[0].ep_in */
  43. #define next_ep0_request(musb) next_in_request(&(musb)->endpoints[0])
  44. /*
  45. * locking note: we use only the controller lock, for simpler correctness.
  46. * It's always held with IRQs blocked.
  47. *
  48. * It protects the ep0 request queue as well as ep0_state, not just the
  49. * controller and indexed registers. And that lock stays held unless it
  50. * needs to be dropped to allow reentering this driver ... like upcalls to
  51. * the gadget driver, or adjusting endpoint halt status.
  52. */
  53. static char *decode_ep0stage(u8 stage)
  54. {
  55. switch (stage) {
  56. case MUSB_EP0_STAGE_SETUP: return "idle";
  57. case MUSB_EP0_STAGE_TX: return "in";
  58. case MUSB_EP0_STAGE_RX: return "out";
  59. case MUSB_EP0_STAGE_ACKWAIT: return "wait";
  60. case MUSB_EP0_STAGE_STATUSIN: return "in/status";
  61. case MUSB_EP0_STAGE_STATUSOUT: return "out/status";
  62. default: return "?";
  63. }
  64. }
  65. /* handle a standard GET_STATUS request
  66. * Context: caller holds controller lock
  67. */
  68. static int service_tx_status_request(
  69. struct musb *musb,
  70. const struct usb_ctrlrequest *ctrlrequest)
  71. {
  72. void __iomem *mbase = musb->mregs;
  73. int handled = 1;
  74. u8 result[2], epnum = 0;
  75. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  76. result[1] = 0;
  77. switch (recip) {
  78. case USB_RECIP_DEVICE:
  79. result[0] = musb->is_self_powered << USB_DEVICE_SELF_POWERED;
  80. result[0] |= musb->may_wakeup << USB_DEVICE_REMOTE_WAKEUP;
  81. #ifdef CONFIG_USB_MUSB_OTG
  82. if (musb->g.is_otg) {
  83. result[0] |= musb->g.b_hnp_enable
  84. << USB_DEVICE_B_HNP_ENABLE;
  85. result[0] |= musb->g.a_alt_hnp_support
  86. << USB_DEVICE_A_ALT_HNP_SUPPORT;
  87. result[0] |= musb->g.a_hnp_support
  88. << USB_DEVICE_A_HNP_SUPPORT;
  89. }
  90. #endif
  91. break;
  92. case USB_RECIP_INTERFACE:
  93. result[0] = 0;
  94. break;
  95. case USB_RECIP_ENDPOINT: {
  96. int is_in;
  97. struct musb_ep *ep;
  98. u16 tmp;
  99. void __iomem *regs;
  100. epnum = (u8) ctrlrequest->wIndex;
  101. if (!epnum) {
  102. result[0] = 0;
  103. break;
  104. }
  105. is_in = epnum & USB_DIR_IN;
  106. if (is_in) {
  107. epnum &= 0x0f;
  108. ep = &musb->endpoints[epnum].ep_in;
  109. } else {
  110. ep = &musb->endpoints[epnum].ep_out;
  111. }
  112. regs = musb->endpoints[epnum].regs;
  113. if (epnum >= MUSB_C_NUM_EPS || !ep->desc) {
  114. handled = -EINVAL;
  115. break;
  116. }
  117. musb_ep_select(mbase, epnum);
  118. if (is_in)
  119. tmp = musb_readw(regs, MUSB_TXCSR)
  120. & MUSB_TXCSR_P_SENDSTALL;
  121. else
  122. tmp = musb_readw(regs, MUSB_RXCSR)
  123. & MUSB_RXCSR_P_SENDSTALL;
  124. musb_ep_select(mbase, 0);
  125. result[0] = tmp ? 1 : 0;
  126. } break;
  127. default:
  128. /* class, vendor, etc ... delegate */
  129. handled = 0;
  130. break;
  131. }
  132. /* fill up the fifo; caller updates csr0 */
  133. if (handled > 0) {
  134. u16 len = le16_to_cpu(ctrlrequest->wLength);
  135. if (len > 2)
  136. len = 2;
  137. musb_write_fifo(&musb->endpoints[0], len, result);
  138. }
  139. return handled;
  140. }
  141. /*
  142. * handle a control-IN request, the end0 buffer contains the current request
  143. * that is supposed to be a standard control request. Assumes the fifo to
  144. * be at least 2 bytes long.
  145. *
  146. * @return 0 if the request was NOT HANDLED,
  147. * < 0 when error
  148. * > 0 when the request is processed
  149. *
  150. * Context: caller holds controller lock
  151. */
  152. static int
  153. service_in_request(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  154. {
  155. int handled = 0; /* not handled */
  156. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  157. == USB_TYPE_STANDARD) {
  158. switch (ctrlrequest->bRequest) {
  159. case USB_REQ_GET_STATUS:
  160. handled = service_tx_status_request(musb,
  161. ctrlrequest);
  162. break;
  163. /* case USB_REQ_SYNC_FRAME: */
  164. default:
  165. break;
  166. }
  167. }
  168. return handled;
  169. }
  170. /*
  171. * Context: caller holds controller lock
  172. */
  173. static void musb_g_ep0_giveback(struct musb *musb, struct usb_request *req)
  174. {
  175. musb_g_giveback(&musb->endpoints[0].ep_in, req, 0);
  176. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  177. }
  178. /*
  179. * Tries to start B-device HNP negotiation if enabled via sysfs
  180. */
  181. static inline void musb_try_b_hnp_enable(struct musb *musb)
  182. {
  183. void __iomem *mbase = musb->mregs;
  184. u8 devctl;
  185. DBG(1, "HNP: Setting HR\n");
  186. devctl = musb_readb(mbase, MUSB_DEVCTL);
  187. musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
  188. }
  189. /*
  190. * Handle all control requests with no DATA stage, including standard
  191. * requests such as:
  192. * USB_REQ_SET_CONFIGURATION, USB_REQ_SET_INTERFACE, unrecognized
  193. * always delegated to the gadget driver
  194. * USB_REQ_SET_ADDRESS, USB_REQ_CLEAR_FEATURE, USB_REQ_SET_FEATURE
  195. * always handled here, except for class/vendor/... features
  196. *
  197. * Context: caller holds controller lock
  198. */
  199. static int
  200. service_zero_data_request(struct musb *musb,
  201. struct usb_ctrlrequest *ctrlrequest)
  202. __releases(musb->lock)
  203. __acquires(musb->lock)
  204. {
  205. int handled = -EINVAL;
  206. void __iomem *mbase = musb->mregs;
  207. const u8 recip = ctrlrequest->bRequestType & USB_RECIP_MASK;
  208. /* the gadget driver handles everything except what we MUST handle */
  209. if ((ctrlrequest->bRequestType & USB_TYPE_MASK)
  210. == USB_TYPE_STANDARD) {
  211. switch (ctrlrequest->bRequest) {
  212. case USB_REQ_SET_ADDRESS:
  213. /* change it after the status stage */
  214. musb->set_address = true;
  215. musb->address = (u8) (ctrlrequest->wValue & 0x7f);
  216. handled = 1;
  217. break;
  218. case USB_REQ_CLEAR_FEATURE:
  219. switch (recip) {
  220. case USB_RECIP_DEVICE:
  221. if (ctrlrequest->wValue
  222. != USB_DEVICE_REMOTE_WAKEUP)
  223. break;
  224. musb->may_wakeup = 0;
  225. handled = 1;
  226. break;
  227. case USB_RECIP_INTERFACE:
  228. break;
  229. case USB_RECIP_ENDPOINT:{
  230. const u8 num = ctrlrequest->wIndex & 0x0f;
  231. struct musb_ep *musb_ep;
  232. if (num == 0
  233. || num >= MUSB_C_NUM_EPS
  234. || ctrlrequest->wValue
  235. != USB_ENDPOINT_HALT)
  236. break;
  237. if (ctrlrequest->wIndex & USB_DIR_IN)
  238. musb_ep = &musb->endpoints[num].ep_in;
  239. else
  240. musb_ep = &musb->endpoints[num].ep_out;
  241. if (!musb_ep->desc)
  242. break;
  243. /* REVISIT do it directly, no locking games */
  244. spin_unlock(&musb->lock);
  245. musb_gadget_set_halt(&musb_ep->end_point, 0);
  246. spin_lock(&musb->lock);
  247. /* select ep0 again */
  248. musb_ep_select(mbase, 0);
  249. handled = 1;
  250. } break;
  251. default:
  252. /* class, vendor, etc ... delegate */
  253. handled = 0;
  254. break;
  255. }
  256. break;
  257. case USB_REQ_SET_FEATURE:
  258. switch (recip) {
  259. case USB_RECIP_DEVICE:
  260. handled = 1;
  261. switch (ctrlrequest->wValue) {
  262. case USB_DEVICE_REMOTE_WAKEUP:
  263. musb->may_wakeup = 1;
  264. break;
  265. case USB_DEVICE_TEST_MODE:
  266. if (musb->g.speed != USB_SPEED_HIGH)
  267. goto stall;
  268. if (ctrlrequest->wIndex & 0xff)
  269. goto stall;
  270. switch (ctrlrequest->wIndex >> 8) {
  271. case 1:
  272. pr_debug("TEST_J\n");
  273. /* TEST_J */
  274. musb->test_mode_nr =
  275. MUSB_TEST_J;
  276. break;
  277. case 2:
  278. /* TEST_K */
  279. pr_debug("TEST_K\n");
  280. musb->test_mode_nr =
  281. MUSB_TEST_K;
  282. break;
  283. case 3:
  284. /* TEST_SE0_NAK */
  285. pr_debug("TEST_SE0_NAK\n");
  286. musb->test_mode_nr =
  287. MUSB_TEST_SE0_NAK;
  288. break;
  289. case 4:
  290. /* TEST_PACKET */
  291. pr_debug("TEST_PACKET\n");
  292. musb->test_mode_nr =
  293. MUSB_TEST_PACKET;
  294. break;
  295. default:
  296. goto stall;
  297. }
  298. /* enter test mode after irq */
  299. if (handled > 0)
  300. musb->test_mode = true;
  301. break;
  302. #ifdef CONFIG_USB_MUSB_OTG
  303. case USB_DEVICE_B_HNP_ENABLE:
  304. if (!musb->g.is_otg)
  305. goto stall;
  306. musb->g.b_hnp_enable = 1;
  307. musb_try_b_hnp_enable(musb);
  308. break;
  309. case USB_DEVICE_A_HNP_SUPPORT:
  310. if (!musb->g.is_otg)
  311. goto stall;
  312. musb->g.a_hnp_support = 1;
  313. break;
  314. case USB_DEVICE_A_ALT_HNP_SUPPORT:
  315. if (!musb->g.is_otg)
  316. goto stall;
  317. musb->g.a_alt_hnp_support = 1;
  318. break;
  319. #endif
  320. stall:
  321. default:
  322. handled = -EINVAL;
  323. break;
  324. }
  325. break;
  326. case USB_RECIP_INTERFACE:
  327. break;
  328. case USB_RECIP_ENDPOINT:{
  329. const u8 epnum =
  330. ctrlrequest->wIndex & 0x0f;
  331. struct musb_ep *musb_ep;
  332. struct musb_hw_ep *ep;
  333. void __iomem *regs;
  334. int is_in;
  335. u16 csr;
  336. if (epnum == 0
  337. || epnum >= MUSB_C_NUM_EPS
  338. || ctrlrequest->wValue
  339. != USB_ENDPOINT_HALT)
  340. break;
  341. ep = musb->endpoints + epnum;
  342. regs = ep->regs;
  343. is_in = ctrlrequest->wIndex & USB_DIR_IN;
  344. if (is_in)
  345. musb_ep = &ep->ep_in;
  346. else
  347. musb_ep = &ep->ep_out;
  348. if (!musb_ep->desc)
  349. break;
  350. musb_ep_select(mbase, epnum);
  351. if (is_in) {
  352. csr = musb_readw(regs,
  353. MUSB_TXCSR);
  354. if (csr & MUSB_TXCSR_FIFONOTEMPTY)
  355. csr |= MUSB_TXCSR_FLUSHFIFO;
  356. csr |= MUSB_TXCSR_P_SENDSTALL
  357. | MUSB_TXCSR_CLRDATATOG
  358. | MUSB_TXCSR_P_WZC_BITS;
  359. musb_writew(regs, MUSB_TXCSR,
  360. csr);
  361. } else {
  362. csr = musb_readw(regs,
  363. MUSB_RXCSR);
  364. csr |= MUSB_RXCSR_P_SENDSTALL
  365. | MUSB_RXCSR_FLUSHFIFO
  366. | MUSB_RXCSR_CLRDATATOG
  367. | MUSB_TXCSR_P_WZC_BITS;
  368. musb_writew(regs, MUSB_RXCSR,
  369. csr);
  370. }
  371. /* select ep0 again */
  372. musb_ep_select(mbase, 0);
  373. handled = 1;
  374. } break;
  375. default:
  376. /* class, vendor, etc ... delegate */
  377. handled = 0;
  378. break;
  379. }
  380. break;
  381. default:
  382. /* delegate SET_CONFIGURATION, etc */
  383. handled = 0;
  384. }
  385. } else
  386. handled = 0;
  387. return handled;
  388. }
  389. /* we have an ep0out data packet
  390. * Context: caller holds controller lock
  391. */
  392. static void ep0_rxstate(struct musb *musb)
  393. {
  394. void __iomem *regs = musb->control_ep->regs;
  395. struct usb_request *req;
  396. u16 tmp;
  397. req = next_ep0_request(musb);
  398. /* read packet and ack; or stall because of gadget driver bug:
  399. * should have provided the rx buffer before setup() returned.
  400. */
  401. if (req) {
  402. void *buf = req->buf + req->actual;
  403. unsigned len = req->length - req->actual;
  404. /* read the buffer */
  405. tmp = musb_readb(regs, MUSB_COUNT0);
  406. if (tmp > len) {
  407. req->status = -EOVERFLOW;
  408. tmp = len;
  409. }
  410. musb_read_fifo(&musb->endpoints[0], tmp, buf);
  411. req->actual += tmp;
  412. tmp = MUSB_CSR0_P_SVDRXPKTRDY;
  413. if (tmp < 64 || req->actual == req->length) {
  414. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  415. tmp |= MUSB_CSR0_P_DATAEND;
  416. } else
  417. req = NULL;
  418. } else
  419. tmp = MUSB_CSR0_P_SVDRXPKTRDY | MUSB_CSR0_P_SENDSTALL;
  420. /* Completion handler may choose to stall, e.g. because the
  421. * message just received holds invalid data.
  422. */
  423. if (req) {
  424. musb->ackpend = tmp;
  425. musb_g_ep0_giveback(musb, req);
  426. if (!musb->ackpend)
  427. return;
  428. musb->ackpend = 0;
  429. }
  430. musb_ep_select(musb->mregs, 0);
  431. musb_writew(regs, MUSB_CSR0, tmp);
  432. }
  433. /*
  434. * transmitting to the host (IN), this code might be called from IRQ
  435. * and from kernel thread.
  436. *
  437. * Context: caller holds controller lock
  438. */
  439. static void ep0_txstate(struct musb *musb)
  440. {
  441. void __iomem *regs = musb->control_ep->regs;
  442. struct usb_request *request = next_ep0_request(musb);
  443. u16 csr = MUSB_CSR0_TXPKTRDY;
  444. u8 *fifo_src;
  445. u8 fifo_count;
  446. if (!request) {
  447. /* WARN_ON(1); */
  448. DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
  449. return;
  450. }
  451. /* load the data */
  452. fifo_src = (u8 *) request->buf + request->actual;
  453. fifo_count = min((unsigned) MUSB_EP0_FIFOSIZE,
  454. request->length - request->actual);
  455. musb_write_fifo(&musb->endpoints[0], fifo_count, fifo_src);
  456. request->actual += fifo_count;
  457. /* update the flags */
  458. if (fifo_count < MUSB_MAX_END0_PACKET
  459. || request->actual == request->length) {
  460. musb->ep0_state = MUSB_EP0_STAGE_STATUSOUT;
  461. csr |= MUSB_CSR0_P_DATAEND;
  462. } else
  463. request = NULL;
  464. /* report completions as soon as the fifo's loaded; there's no
  465. * win in waiting till this last packet gets acked. (other than
  466. * very precise fault reporting, needed by USB TMC; possible with
  467. * this hardware, but not usable from portable gadget drivers.)
  468. */
  469. if (request) {
  470. musb->ackpend = csr;
  471. musb_g_ep0_giveback(musb, request);
  472. if (!musb->ackpend)
  473. return;
  474. musb->ackpend = 0;
  475. }
  476. /* send it out, triggering a "txpktrdy cleared" irq */
  477. musb_ep_select(musb->mregs, 0);
  478. musb_writew(regs, MUSB_CSR0, csr);
  479. }
  480. /*
  481. * Read a SETUP packet (struct usb_ctrlrequest) from the hardware.
  482. * Fields are left in USB byte-order.
  483. *
  484. * Context: caller holds controller lock.
  485. */
  486. static void
  487. musb_read_setup(struct musb *musb, struct usb_ctrlrequest *req)
  488. {
  489. struct usb_request *r;
  490. void __iomem *regs = musb->control_ep->regs;
  491. musb_read_fifo(&musb->endpoints[0], sizeof *req, (u8 *)req);
  492. /* NOTE: earlier 2.6 versions changed setup packets to host
  493. * order, but now USB packets always stay in USB byte order.
  494. */
  495. DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
  496. req->bRequestType,
  497. req->bRequest,
  498. le16_to_cpu(req->wValue),
  499. le16_to_cpu(req->wIndex),
  500. le16_to_cpu(req->wLength));
  501. /* clean up any leftover transfers */
  502. r = next_ep0_request(musb);
  503. if (r)
  504. musb_g_ep0_giveback(musb, r);
  505. /* For zero-data requests we want to delay the STATUS stage to
  506. * avoid SETUPEND errors. If we read data (OUT), delay accepting
  507. * packets until there's a buffer to store them in.
  508. *
  509. * If we write data, the controller acts happier if we enable
  510. * the TX FIFO right away, and give the controller a moment
  511. * to switch modes...
  512. */
  513. musb->set_address = false;
  514. musb->ackpend = MUSB_CSR0_P_SVDRXPKTRDY;
  515. if (req->wLength == 0) {
  516. if (req->bRequestType & USB_DIR_IN)
  517. musb->ackpend |= MUSB_CSR0_TXPKTRDY;
  518. musb->ep0_state = MUSB_EP0_STAGE_ACKWAIT;
  519. } else if (req->bRequestType & USB_DIR_IN) {
  520. musb->ep0_state = MUSB_EP0_STAGE_TX;
  521. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDRXPKTRDY);
  522. while ((musb_readw(regs, MUSB_CSR0)
  523. & MUSB_CSR0_RXPKTRDY) != 0)
  524. cpu_relax();
  525. musb->ackpend = 0;
  526. } else
  527. musb->ep0_state = MUSB_EP0_STAGE_RX;
  528. }
  529. static int
  530. forward_to_driver(struct musb *musb, const struct usb_ctrlrequest *ctrlrequest)
  531. __releases(musb->lock)
  532. __acquires(musb->lock)
  533. {
  534. int retval;
  535. if (!musb->gadget_driver)
  536. return -EOPNOTSUPP;
  537. spin_unlock(&musb->lock);
  538. retval = musb->gadget_driver->setup(&musb->g, ctrlrequest);
  539. spin_lock(&musb->lock);
  540. return retval;
  541. }
  542. /*
  543. * Handle peripheral ep0 interrupt
  544. *
  545. * Context: irq handler; we won't re-enter the driver that way.
  546. */
  547. irqreturn_t musb_g_ep0_irq(struct musb *musb)
  548. {
  549. u16 csr;
  550. u16 len;
  551. void __iomem *mbase = musb->mregs;
  552. void __iomem *regs = musb->endpoints[0].regs;
  553. irqreturn_t retval = IRQ_NONE;
  554. musb_ep_select(mbase, 0); /* select ep0 */
  555. csr = musb_readw(regs, MUSB_CSR0);
  556. len = musb_readb(regs, MUSB_COUNT0);
  557. DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
  558. csr, len,
  559. musb_readb(mbase, MUSB_FADDR),
  560. decode_ep0stage(musb->ep0_state));
  561. /* I sent a stall.. need to acknowledge it now.. */
  562. if (csr & MUSB_CSR0_P_SENTSTALL) {
  563. musb_writew(regs, MUSB_CSR0,
  564. csr & ~MUSB_CSR0_P_SENTSTALL);
  565. retval = IRQ_HANDLED;
  566. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  567. csr = musb_readw(regs, MUSB_CSR0);
  568. }
  569. /* request ended "early" */
  570. if (csr & MUSB_CSR0_P_SETUPEND) {
  571. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SVDSETUPEND);
  572. retval = IRQ_HANDLED;
  573. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  574. csr = musb_readw(regs, MUSB_CSR0);
  575. /* NOTE: request may need completion */
  576. }
  577. /* docs from Mentor only describe tx, rx, and idle/setup states.
  578. * we need to handle nuances around status stages, and also the
  579. * case where status and setup stages come back-to-back ...
  580. */
  581. switch (musb->ep0_state) {
  582. case MUSB_EP0_STAGE_TX:
  583. /* irq on clearing txpktrdy */
  584. if ((csr & MUSB_CSR0_TXPKTRDY) == 0) {
  585. ep0_txstate(musb);
  586. retval = IRQ_HANDLED;
  587. }
  588. break;
  589. case MUSB_EP0_STAGE_RX:
  590. /* irq on set rxpktrdy */
  591. if (csr & MUSB_CSR0_RXPKTRDY) {
  592. ep0_rxstate(musb);
  593. retval = IRQ_HANDLED;
  594. }
  595. break;
  596. case MUSB_EP0_STAGE_STATUSIN:
  597. /* end of sequence #2 (OUT/RX state) or #3 (no data) */
  598. /* update address (if needed) only @ the end of the
  599. * status phase per usb spec, which also guarantees
  600. * we get 10 msec to receive this irq... until this
  601. * is done we won't see the next packet.
  602. */
  603. if (musb->set_address) {
  604. musb->set_address = false;
  605. musb_writeb(mbase, MUSB_FADDR, musb->address);
  606. }
  607. /* enter test mode if needed (exit by reset) */
  608. else if (musb->test_mode) {
  609. DBG(1, "entering TESTMODE\n");
  610. if (MUSB_TEST_PACKET == musb->test_mode_nr)
  611. musb_load_testpacket(musb);
  612. musb_writeb(mbase, MUSB_TESTMODE,
  613. musb->test_mode_nr);
  614. }
  615. /* FALLTHROUGH */
  616. case MUSB_EP0_STAGE_STATUSOUT:
  617. /* end of sequence #1: write to host (TX state) */
  618. {
  619. struct usb_request *req;
  620. req = next_ep0_request(musb);
  621. if (req)
  622. musb_g_ep0_giveback(musb, req);
  623. }
  624. retval = IRQ_HANDLED;
  625. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  626. /* FALLTHROUGH */
  627. case MUSB_EP0_STAGE_SETUP:
  628. if (csr & MUSB_CSR0_RXPKTRDY) {
  629. struct usb_ctrlrequest setup;
  630. int handled = 0;
  631. if (len != 8) {
  632. ERR("SETUP packet len %d != 8 ?\n", len);
  633. break;
  634. }
  635. musb_read_setup(musb, &setup);
  636. retval = IRQ_HANDLED;
  637. /* sometimes the RESET won't be reported */
  638. if (unlikely(musb->g.speed == USB_SPEED_UNKNOWN)) {
  639. u8 power;
  640. printk(KERN_NOTICE "%s: peripheral reset "
  641. "irq lost!\n",
  642. musb_driver_name);
  643. power = musb_readb(mbase, MUSB_POWER);
  644. musb->g.speed = (power & MUSB_POWER_HSMODE)
  645. ? USB_SPEED_HIGH : USB_SPEED_FULL;
  646. }
  647. switch (musb->ep0_state) {
  648. /* sequence #3 (no data stage), includes requests
  649. * we can't forward (notably SET_ADDRESS and the
  650. * device/endpoint feature set/clear operations)
  651. * plus SET_CONFIGURATION and others we must
  652. */
  653. case MUSB_EP0_STAGE_ACKWAIT:
  654. handled = service_zero_data_request(
  655. musb, &setup);
  656. /* status stage might be immediate */
  657. if (handled > 0) {
  658. musb->ackpend |= MUSB_CSR0_P_DATAEND;
  659. musb->ep0_state =
  660. MUSB_EP0_STAGE_STATUSIN;
  661. }
  662. break;
  663. /* sequence #1 (IN to host), includes GET_STATUS
  664. * requests that we can't forward, GET_DESCRIPTOR
  665. * and others that we must
  666. */
  667. case MUSB_EP0_STAGE_TX:
  668. handled = service_in_request(musb, &setup);
  669. if (handled > 0) {
  670. musb->ackpend = MUSB_CSR0_TXPKTRDY
  671. | MUSB_CSR0_P_DATAEND;
  672. musb->ep0_state =
  673. MUSB_EP0_STAGE_STATUSOUT;
  674. }
  675. break;
  676. /* sequence #2 (OUT from host), always forward */
  677. default: /* MUSB_EP0_STAGE_RX */
  678. break;
  679. }
  680. DBG(3, "handled %d, csr %04x, ep0stage %s\n",
  681. handled, csr,
  682. decode_ep0stage(musb->ep0_state));
  683. /* unless we need to delegate this to the gadget
  684. * driver, we know how to wrap this up: csr0 has
  685. * not yet been written.
  686. */
  687. if (handled < 0)
  688. goto stall;
  689. else if (handled > 0)
  690. goto finish;
  691. handled = forward_to_driver(musb, &setup);
  692. if (handled < 0) {
  693. musb_ep_select(mbase, 0);
  694. stall:
  695. DBG(3, "stall (%d)\n", handled);
  696. musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
  697. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  698. finish:
  699. musb_writew(regs, MUSB_CSR0,
  700. musb->ackpend);
  701. musb->ackpend = 0;
  702. }
  703. }
  704. break;
  705. case MUSB_EP0_STAGE_ACKWAIT:
  706. /* This should not happen. But happens with tusb6010 with
  707. * g_file_storage and high speed. Do nothing.
  708. */
  709. retval = IRQ_HANDLED;
  710. break;
  711. default:
  712. /* "can't happen" */
  713. WARN_ON(1);
  714. musb_writew(regs, MUSB_CSR0, MUSB_CSR0_P_SENDSTALL);
  715. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  716. break;
  717. }
  718. return retval;
  719. }
  720. static int
  721. musb_g_ep0_enable(struct usb_ep *ep, const struct usb_endpoint_descriptor *desc)
  722. {
  723. /* always enabled */
  724. return -EINVAL;
  725. }
  726. static int musb_g_ep0_disable(struct usb_ep *e)
  727. {
  728. /* always enabled */
  729. return -EINVAL;
  730. }
  731. static int
  732. musb_g_ep0_queue(struct usb_ep *e, struct usb_request *r, gfp_t gfp_flags)
  733. {
  734. struct musb_ep *ep;
  735. struct musb_request *req;
  736. struct musb *musb;
  737. int status;
  738. unsigned long lockflags;
  739. void __iomem *regs;
  740. if (!e || !r)
  741. return -EINVAL;
  742. ep = to_musb_ep(e);
  743. musb = ep->musb;
  744. regs = musb->control_ep->regs;
  745. req = to_musb_request(r);
  746. req->musb = musb;
  747. req->request.actual = 0;
  748. req->request.status = -EINPROGRESS;
  749. req->tx = ep->is_in;
  750. spin_lock_irqsave(&musb->lock, lockflags);
  751. if (!list_empty(&ep->req_list)) {
  752. status = -EBUSY;
  753. goto cleanup;
  754. }
  755. switch (musb->ep0_state) {
  756. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  757. case MUSB_EP0_STAGE_TX: /* control-IN data */
  758. case MUSB_EP0_STAGE_ACKWAIT: /* zero-length data */
  759. status = 0;
  760. break;
  761. default:
  762. DBG(1, "ep0 request queued in state %d\n",
  763. musb->ep0_state);
  764. status = -EINVAL;
  765. goto cleanup;
  766. }
  767. /* add request to the list */
  768. list_add_tail(&(req->request.list), &(ep->req_list));
  769. DBG(3, "queue to %s (%s), length=%d\n",
  770. ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
  771. req->request.length);
  772. musb_ep_select(musb->mregs, 0);
  773. /* sequence #1, IN ... start writing the data */
  774. if (musb->ep0_state == MUSB_EP0_STAGE_TX)
  775. ep0_txstate(musb);
  776. /* sequence #3, no-data ... issue IN status */
  777. else if (musb->ep0_state == MUSB_EP0_STAGE_ACKWAIT) {
  778. if (req->request.length)
  779. status = -EINVAL;
  780. else {
  781. musb->ep0_state = MUSB_EP0_STAGE_STATUSIN;
  782. musb_writew(regs, MUSB_CSR0,
  783. musb->ackpend | MUSB_CSR0_P_DATAEND);
  784. musb->ackpend = 0;
  785. musb_g_ep0_giveback(ep->musb, r);
  786. }
  787. /* else for sequence #2 (OUT), caller provides a buffer
  788. * before the next packet arrives. deferred responses
  789. * (after SETUP is acked) are racey.
  790. */
  791. } else if (musb->ackpend) {
  792. musb_writew(regs, MUSB_CSR0, musb->ackpend);
  793. musb->ackpend = 0;
  794. }
  795. cleanup:
  796. spin_unlock_irqrestore(&musb->lock, lockflags);
  797. return status;
  798. }
  799. static int musb_g_ep0_dequeue(struct usb_ep *ep, struct usb_request *req)
  800. {
  801. /* we just won't support this */
  802. return -EINVAL;
  803. }
  804. static int musb_g_ep0_halt(struct usb_ep *e, int value)
  805. {
  806. struct musb_ep *ep;
  807. struct musb *musb;
  808. void __iomem *base, *regs;
  809. unsigned long flags;
  810. int status;
  811. u16 csr;
  812. if (!e || !value)
  813. return -EINVAL;
  814. ep = to_musb_ep(e);
  815. musb = ep->musb;
  816. base = musb->mregs;
  817. regs = musb->control_ep->regs;
  818. status = 0;
  819. spin_lock_irqsave(&musb->lock, flags);
  820. if (!list_empty(&ep->req_list)) {
  821. status = -EBUSY;
  822. goto cleanup;
  823. }
  824. musb_ep_select(base, 0);
  825. csr = musb->ackpend;
  826. switch (musb->ep0_state) {
  827. /* Stalls are usually issued after parsing SETUP packet, either
  828. * directly in irq context from setup() or else later.
  829. */
  830. case MUSB_EP0_STAGE_TX: /* control-IN data */
  831. case MUSB_EP0_STAGE_ACKWAIT: /* STALL for zero-length data */
  832. case MUSB_EP0_STAGE_RX: /* control-OUT data */
  833. csr = musb_readw(regs, MUSB_CSR0);
  834. /* FALLTHROUGH */
  835. /* It's also OK to issue stalls during callbacks when a non-empty
  836. * DATA stage buffer has been read (or even written).
  837. */
  838. case MUSB_EP0_STAGE_STATUSIN: /* control-OUT status */
  839. case MUSB_EP0_STAGE_STATUSOUT: /* control-IN status */
  840. csr |= MUSB_CSR0_P_SENDSTALL;
  841. musb_writew(regs, MUSB_CSR0, csr);
  842. musb->ep0_state = MUSB_EP0_STAGE_SETUP;
  843. musb->ackpend = 0;
  844. break;
  845. default:
  846. DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
  847. status = -EINVAL;
  848. }
  849. cleanup:
  850. spin_unlock_irqrestore(&musb->lock, flags);
  851. return status;
  852. }
  853. const struct usb_ep_ops musb_g_ep0_ops = {
  854. .enable = musb_g_ep0_enable,
  855. .disable = musb_g_ep0_disable,
  856. .alloc_request = musb_alloc_request,
  857. .free_request = musb_free_request,
  858. .queue = musb_g_ep0_queue,
  859. .dequeue = musb_g_ep0_dequeue,
  860. .set_halt = musb_g_ep0_halt,
  861. };