musb_dma.h 5.7 KB

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  1. /*
  2. * MUSB OTG driver DMA controller abstraction
  3. *
  4. * Copyright 2005 Mentor Graphics Corporation
  5. * Copyright (C) 2005-2006 by Texas Instruments
  6. * Copyright (C) 2006-2007 Nokia Corporation
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * version 2 as published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  20. * 02110-1301 USA
  21. *
  22. * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  23. * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  24. * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  25. * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26. * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  27. * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  28. * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  29. * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  31. * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. *
  33. */
  34. #ifndef __MUSB_DMA_H__
  35. #define __MUSB_DMA_H__
  36. struct musb_hw_ep;
  37. /*
  38. * DMA Controller Abstraction
  39. *
  40. * DMA Controllers are abstracted to allow use of a variety of different
  41. * implementations of DMA, as allowed by the Inventra USB cores. On the
  42. * host side, usbcore sets up the DMA mappings and flushes caches; on the
  43. * peripheral side, the gadget controller driver does. Responsibilities
  44. * of a DMA controller driver include:
  45. *
  46. * - Handling the details of moving multiple USB packets
  47. * in cooperation with the Inventra USB core, including especially
  48. * the correct RX side treatment of short packets and buffer-full
  49. * states (both of which terminate transfers).
  50. *
  51. * - Knowing the correlation between dma channels and the
  52. * Inventra core's local endpoint resources and data direction.
  53. *
  54. * - Maintaining a list of allocated/available channels.
  55. *
  56. * - Updating channel status on interrupts,
  57. * whether shared with the Inventra core or separate.
  58. */
  59. #define DMA_ADDR_INVALID (~(dma_addr_t)0)
  60. #ifndef CONFIG_MUSB_PIO_ONLY
  61. #define is_dma_capable() (1)
  62. #else
  63. #define is_dma_capable() (0)
  64. #endif
  65. #ifdef CONFIG_USB_TI_CPPI_DMA
  66. #define is_cppi_enabled() 1
  67. #else
  68. #define is_cppi_enabled() 0
  69. #endif
  70. #ifdef CONFIG_USB_TUSB_OMAP_DMA
  71. #define tusb_dma_omap() 1
  72. #else
  73. #define tusb_dma_omap() 0
  74. #endif
  75. /*
  76. * DMA channel status ... updated by the dma controller driver whenever that
  77. * status changes, and protected by the overall controller spinlock.
  78. */
  79. enum dma_channel_status {
  80. /* unallocated */
  81. MUSB_DMA_STATUS_UNKNOWN,
  82. /* allocated ... but not busy, no errors */
  83. MUSB_DMA_STATUS_FREE,
  84. /* busy ... transactions are active */
  85. MUSB_DMA_STATUS_BUSY,
  86. /* transaction(s) aborted due to ... dma or memory bus error */
  87. MUSB_DMA_STATUS_BUS_ABORT,
  88. /* transaction(s) aborted due to ... core error or USB fault */
  89. MUSB_DMA_STATUS_CORE_ABORT
  90. };
  91. struct dma_controller;
  92. /**
  93. * struct dma_channel - A DMA channel.
  94. * @private_data: channel-private data
  95. * @max_len: the maximum number of bytes the channel can move in one
  96. * transaction (typically representing many USB maximum-sized packets)
  97. * @actual_len: how many bytes have been transferred
  98. * @status: current channel status (updated e.g. on interrupt)
  99. * @desired_mode: true if mode 1 is desired; false if mode 0 is desired
  100. *
  101. * channels are associated with an endpoint for the duration of at least
  102. * one usb transfer.
  103. */
  104. struct dma_channel {
  105. void *private_data;
  106. /* FIXME not void* private_data, but a dma_controller * */
  107. size_t max_len;
  108. size_t actual_len;
  109. enum dma_channel_status status;
  110. bool desired_mode;
  111. };
  112. /*
  113. * dma_channel_status - return status of dma channel
  114. * @c: the channel
  115. *
  116. * Returns the software's view of the channel status. If that status is BUSY
  117. * then it's possible that the hardware has completed (or aborted) a transfer,
  118. * so the driver needs to update that status.
  119. */
  120. static inline enum dma_channel_status
  121. dma_channel_status(struct dma_channel *c)
  122. {
  123. return (is_dma_capable() && c) ? c->status : MUSB_DMA_STATUS_UNKNOWN;
  124. }
  125. /**
  126. * struct dma_controller - A DMA Controller.
  127. * @start: call this to start a DMA controller;
  128. * return 0 on success, else negative errno
  129. * @stop: call this to stop a DMA controller
  130. * return 0 on success, else negative errno
  131. * @channel_alloc: call this to allocate a DMA channel
  132. * @channel_release: call this to release a DMA channel
  133. * @channel_abort: call this to abort a pending DMA transaction,
  134. * returning it to FREE (but allocated) state
  135. *
  136. * Controllers manage dma channels.
  137. */
  138. struct dma_controller {
  139. int (*start)(struct dma_controller *);
  140. int (*stop)(struct dma_controller *);
  141. struct dma_channel *(*channel_alloc)(struct dma_controller *,
  142. struct musb_hw_ep *, u8 is_tx);
  143. void (*channel_release)(struct dma_channel *);
  144. int (*channel_program)(struct dma_channel *channel,
  145. u16 maxpacket, u8 mode,
  146. dma_addr_t dma_addr,
  147. u32 length);
  148. int (*channel_abort)(struct dma_channel *);
  149. };
  150. /* called after channel_program(), may indicate a fault */
  151. extern void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit);
  152. extern struct dma_controller *__init
  153. dma_controller_create(struct musb *, void __iomem *);
  154. extern void dma_controller_destroy(struct dma_controller *);
  155. #endif /* __MUSB_DMA_H__ */