m66592-udc.c 42 KB

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  1. /*
  2. * M66592 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/usb/ch9.h>
  28. #include <linux/usb/gadget.h>
  29. #include "m66592-udc.h"
  30. MODULE_DESCRIPTION("M66592 USB gadget driver");
  31. MODULE_LICENSE("GPL");
  32. MODULE_AUTHOR("Yoshihiro Shimoda");
  33. MODULE_ALIAS("platform:m66592_udc");
  34. #define DRIVER_VERSION "18 Oct 2007"
  35. /* module parameters */
  36. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  37. static unsigned short endian = M66592_LITTLE;
  38. module_param(endian, ushort, 0644);
  39. MODULE_PARM_DESC(endian, "data endian: big=0, little=0 (default=0)");
  40. #else
  41. static unsigned short clock = M66592_XTAL24;
  42. module_param(clock, ushort, 0644);
  43. MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 "
  44. "(default=16384)");
  45. static unsigned short vif = M66592_LDRV;
  46. module_param(vif, ushort, 0644);
  47. MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0 (default=32768)");
  48. static unsigned short endian;
  49. module_param(endian, ushort, 0644);
  50. MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)");
  51. static unsigned short irq_sense = M66592_INTL;
  52. module_param(irq_sense, ushort, 0644);
  53. MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=2, falling edge=0 "
  54. "(default=2)");
  55. #endif
  56. static const char udc_name[] = "m66592_udc";
  57. static const char *m66592_ep_name[] = {
  58. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  59. };
  60. static void disable_controller(struct m66592 *m66592);
  61. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  62. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  63. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  64. gfp_t gfp_flags);
  65. static void transfer_complete(struct m66592_ep *ep,
  66. struct m66592_request *req, int status);
  67. /*-------------------------------------------------------------------------*/
  68. static inline u16 get_usb_speed(struct m66592 *m66592)
  69. {
  70. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  71. }
  72. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  73. unsigned long reg)
  74. {
  75. u16 tmp;
  76. tmp = m66592_read(m66592, M66592_INTENB0);
  77. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  78. M66592_INTENB0);
  79. m66592_bset(m66592, (1 << pipenum), reg);
  80. m66592_write(m66592, tmp, M66592_INTENB0);
  81. }
  82. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  83. unsigned long reg)
  84. {
  85. u16 tmp;
  86. tmp = m66592_read(m66592, M66592_INTENB0);
  87. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  88. M66592_INTENB0);
  89. m66592_bclr(m66592, (1 << pipenum), reg);
  90. m66592_write(m66592, tmp, M66592_INTENB0);
  91. }
  92. static void m66592_usb_connect(struct m66592 *m66592)
  93. {
  94. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  95. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  96. M66592_INTENB0);
  97. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  98. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  99. }
  100. static void m66592_usb_disconnect(struct m66592 *m66592)
  101. __releases(m66592->lock)
  102. __acquires(m66592->lock)
  103. {
  104. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  105. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  106. M66592_INTENB0);
  107. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  108. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  109. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  110. spin_unlock(&m66592->lock);
  111. m66592->driver->disconnect(&m66592->gadget);
  112. spin_lock(&m66592->lock);
  113. disable_controller(m66592);
  114. INIT_LIST_HEAD(&m66592->ep[0].queue);
  115. }
  116. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  117. {
  118. u16 pid = 0;
  119. unsigned long offset;
  120. if (pipenum == 0)
  121. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  122. else if (pipenum < M66592_MAX_NUM_PIPE) {
  123. offset = get_pipectr_addr(pipenum);
  124. pid = m66592_read(m66592, offset) & M66592_PID;
  125. } else
  126. pr_err("unexpect pipe num (%d)\n", pipenum);
  127. return pid;
  128. }
  129. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  130. u16 pid)
  131. {
  132. unsigned long offset;
  133. if (pipenum == 0)
  134. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  135. else if (pipenum < M66592_MAX_NUM_PIPE) {
  136. offset = get_pipectr_addr(pipenum);
  137. m66592_mdfy(m66592, pid, M66592_PID, offset);
  138. } else
  139. pr_err("unexpect pipe num (%d)\n", pipenum);
  140. }
  141. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  142. {
  143. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  144. }
  145. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  146. {
  147. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  148. }
  149. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  150. {
  151. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  152. }
  153. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  154. {
  155. u16 ret = 0;
  156. unsigned long offset;
  157. if (pipenum == 0)
  158. ret = m66592_read(m66592, M66592_DCPCTR);
  159. else if (pipenum < M66592_MAX_NUM_PIPE) {
  160. offset = get_pipectr_addr(pipenum);
  161. ret = m66592_read(m66592, offset);
  162. } else
  163. pr_err("unexpect pipe num (%d)\n", pipenum);
  164. return ret;
  165. }
  166. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  167. {
  168. unsigned long offset;
  169. pipe_stop(m66592, pipenum);
  170. if (pipenum == 0)
  171. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  172. else if (pipenum < M66592_MAX_NUM_PIPE) {
  173. offset = get_pipectr_addr(pipenum);
  174. m66592_bset(m66592, M66592_SQCLR, offset);
  175. } else
  176. pr_err("unexpect pipe num(%d)\n", pipenum);
  177. }
  178. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  179. {
  180. u16 tmp;
  181. int size;
  182. if (pipenum == 0) {
  183. tmp = m66592_read(m66592, M66592_DCPCFG);
  184. if ((tmp & M66592_CNTMD) != 0)
  185. size = 256;
  186. else {
  187. tmp = m66592_read(m66592, M66592_DCPMAXP);
  188. size = tmp & M66592_MAXP;
  189. }
  190. } else {
  191. m66592_write(m66592, pipenum, M66592_PIPESEL);
  192. tmp = m66592_read(m66592, M66592_PIPECFG);
  193. if ((tmp & M66592_CNTMD) != 0) {
  194. tmp = m66592_read(m66592, M66592_PIPEBUF);
  195. size = ((tmp >> 10) + 1) * 64;
  196. } else {
  197. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  198. size = tmp & M66592_MXPS;
  199. }
  200. }
  201. return size;
  202. }
  203. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  204. {
  205. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  206. if (ep->use_dma)
  207. return;
  208. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  209. ndelay(450);
  210. m66592_bset(m66592, M66592_MBW, ep->fifosel);
  211. }
  212. static int pipe_buffer_setting(struct m66592 *m66592,
  213. struct m66592_pipe_info *info)
  214. {
  215. u16 bufnum = 0, buf_bsize = 0;
  216. u16 pipecfg = 0;
  217. if (info->pipe == 0)
  218. return -EINVAL;
  219. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  220. if (info->dir_in)
  221. pipecfg |= M66592_DIR;
  222. pipecfg |= info->type;
  223. pipecfg |= info->epnum;
  224. switch (info->type) {
  225. case M66592_INT:
  226. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  227. buf_bsize = 0;
  228. break;
  229. case M66592_BULK:
  230. bufnum = m66592->bi_bufnum +
  231. (info->pipe - M66592_BASE_PIPENUM_BULK) * 16;
  232. m66592->bi_bufnum += 16;
  233. buf_bsize = 7;
  234. pipecfg |= M66592_DBLB;
  235. if (!info->dir_in)
  236. pipecfg |= M66592_SHTNAK;
  237. break;
  238. case M66592_ISO:
  239. bufnum = m66592->bi_bufnum +
  240. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  241. m66592->bi_bufnum += 16;
  242. buf_bsize = 7;
  243. break;
  244. }
  245. if (m66592->bi_bufnum > M66592_MAX_BUFNUM) {
  246. pr_err("m66592 pipe memory is insufficient(%d)\n",
  247. m66592->bi_bufnum);
  248. return -ENOMEM;
  249. }
  250. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  251. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  252. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  253. if (info->interval)
  254. info->interval--;
  255. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  256. return 0;
  257. }
  258. static void pipe_buffer_release(struct m66592 *m66592,
  259. struct m66592_pipe_info *info)
  260. {
  261. if (info->pipe == 0)
  262. return;
  263. switch (info->type) {
  264. case M66592_BULK:
  265. if (is_bulk_pipe(info->pipe))
  266. m66592->bi_bufnum -= 16;
  267. break;
  268. case M66592_ISO:
  269. if (is_isoc_pipe(info->pipe))
  270. m66592->bi_bufnum -= 16;
  271. break;
  272. }
  273. if (is_bulk_pipe(info->pipe)) {
  274. m66592->bulk--;
  275. } else if (is_interrupt_pipe(info->pipe))
  276. m66592->interrupt--;
  277. else if (is_isoc_pipe(info->pipe)) {
  278. m66592->isochronous--;
  279. if (info->type == M66592_BULK)
  280. m66592->bulk--;
  281. } else
  282. pr_err("ep_release: unexpect pipenum (%d)\n",
  283. info->pipe);
  284. }
  285. static void pipe_initialize(struct m66592_ep *ep)
  286. {
  287. struct m66592 *m66592 = ep->m66592;
  288. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  289. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  290. m66592_write(m66592, 0, ep->pipectr);
  291. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  292. if (ep->use_dma) {
  293. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  294. ndelay(450);
  295. m66592_bset(m66592, M66592_MBW, ep->fifosel);
  296. }
  297. }
  298. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  299. const struct usb_endpoint_descriptor *desc,
  300. u16 pipenum, int dma)
  301. {
  302. if ((pipenum != 0) && dma) {
  303. if (m66592->num_dma == 0) {
  304. m66592->num_dma++;
  305. ep->use_dma = 1;
  306. ep->fifoaddr = M66592_D0FIFO;
  307. ep->fifosel = M66592_D0FIFOSEL;
  308. ep->fifoctr = M66592_D0FIFOCTR;
  309. ep->fifotrn = M66592_D0FIFOTRN;
  310. #if !defined(CONFIG_SUPERH_BUILT_IN_M66592)
  311. } else if (m66592->num_dma == 1) {
  312. m66592->num_dma++;
  313. ep->use_dma = 1;
  314. ep->fifoaddr = M66592_D1FIFO;
  315. ep->fifosel = M66592_D1FIFOSEL;
  316. ep->fifoctr = M66592_D1FIFOCTR;
  317. ep->fifotrn = M66592_D1FIFOTRN;
  318. #endif
  319. } else {
  320. ep->use_dma = 0;
  321. ep->fifoaddr = M66592_CFIFO;
  322. ep->fifosel = M66592_CFIFOSEL;
  323. ep->fifoctr = M66592_CFIFOCTR;
  324. ep->fifotrn = 0;
  325. }
  326. } else {
  327. ep->use_dma = 0;
  328. ep->fifoaddr = M66592_CFIFO;
  329. ep->fifosel = M66592_CFIFOSEL;
  330. ep->fifoctr = M66592_CFIFOCTR;
  331. ep->fifotrn = 0;
  332. }
  333. ep->pipectr = get_pipectr_addr(pipenum);
  334. ep->pipenum = pipenum;
  335. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  336. m66592->pipenum2ep[pipenum] = ep;
  337. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  338. INIT_LIST_HEAD(&ep->queue);
  339. }
  340. static void m66592_ep_release(struct m66592_ep *ep)
  341. {
  342. struct m66592 *m66592 = ep->m66592;
  343. u16 pipenum = ep->pipenum;
  344. if (pipenum == 0)
  345. return;
  346. if (ep->use_dma)
  347. m66592->num_dma--;
  348. ep->pipenum = 0;
  349. ep->busy = 0;
  350. ep->use_dma = 0;
  351. }
  352. static int alloc_pipe_config(struct m66592_ep *ep,
  353. const struct usb_endpoint_descriptor *desc)
  354. {
  355. struct m66592 *m66592 = ep->m66592;
  356. struct m66592_pipe_info info;
  357. int dma = 0;
  358. int *counter;
  359. int ret;
  360. ep->desc = desc;
  361. BUG_ON(ep->pipenum);
  362. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  363. case USB_ENDPOINT_XFER_BULK:
  364. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  365. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  366. pr_err("bulk pipe is insufficient\n");
  367. return -ENODEV;
  368. } else {
  369. info.pipe = M66592_BASE_PIPENUM_ISOC
  370. + m66592->isochronous;
  371. counter = &m66592->isochronous;
  372. }
  373. } else {
  374. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  375. counter = &m66592->bulk;
  376. }
  377. info.type = M66592_BULK;
  378. dma = 1;
  379. break;
  380. case USB_ENDPOINT_XFER_INT:
  381. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  382. pr_err("interrupt pipe is insufficient\n");
  383. return -ENODEV;
  384. }
  385. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  386. info.type = M66592_INT;
  387. counter = &m66592->interrupt;
  388. break;
  389. case USB_ENDPOINT_XFER_ISOC:
  390. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  391. pr_err("isochronous pipe is insufficient\n");
  392. return -ENODEV;
  393. }
  394. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  395. info.type = M66592_ISO;
  396. counter = &m66592->isochronous;
  397. break;
  398. default:
  399. pr_err("unexpect xfer type\n");
  400. return -EINVAL;
  401. }
  402. ep->type = info.type;
  403. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  404. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  405. info.interval = desc->bInterval;
  406. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  407. info.dir_in = 1;
  408. else
  409. info.dir_in = 0;
  410. ret = pipe_buffer_setting(m66592, &info);
  411. if (ret < 0) {
  412. pr_err("pipe_buffer_setting fail\n");
  413. return ret;
  414. }
  415. (*counter)++;
  416. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  417. m66592->bulk++;
  418. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  419. pipe_initialize(ep);
  420. return 0;
  421. }
  422. static int free_pipe_config(struct m66592_ep *ep)
  423. {
  424. struct m66592 *m66592 = ep->m66592;
  425. struct m66592_pipe_info info;
  426. info.pipe = ep->pipenum;
  427. info.type = ep->type;
  428. pipe_buffer_release(m66592, &info);
  429. m66592_ep_release(ep);
  430. return 0;
  431. }
  432. /*-------------------------------------------------------------------------*/
  433. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  434. {
  435. enable_irq_ready(m66592, pipenum);
  436. enable_irq_nrdy(m66592, pipenum);
  437. }
  438. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  439. {
  440. disable_irq_ready(m66592, pipenum);
  441. disable_irq_nrdy(m66592, pipenum);
  442. }
  443. /* if complete is true, gadget driver complete function is not call */
  444. static void control_end(struct m66592 *m66592, unsigned ccpl)
  445. {
  446. m66592->ep[0].internal_ccpl = ccpl;
  447. pipe_start(m66592, 0);
  448. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  449. }
  450. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  451. {
  452. struct m66592 *m66592 = ep->m66592;
  453. pipe_change(m66592, ep->pipenum);
  454. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  455. (M66592_ISEL | M66592_CURPIPE),
  456. M66592_CFIFOSEL);
  457. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  458. if (req->req.length == 0) {
  459. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  460. pipe_start(m66592, 0);
  461. transfer_complete(ep, req, 0);
  462. } else {
  463. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  464. irq_ep0_write(ep, req);
  465. }
  466. }
  467. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  468. {
  469. struct m66592 *m66592 = ep->m66592;
  470. u16 tmp;
  471. pipe_change(m66592, ep->pipenum);
  472. disable_irq_empty(m66592, ep->pipenum);
  473. pipe_start(m66592, ep->pipenum);
  474. tmp = m66592_read(m66592, ep->fifoctr);
  475. if (unlikely((tmp & M66592_FRDY) == 0))
  476. pipe_irq_enable(m66592, ep->pipenum);
  477. else
  478. irq_packet_write(ep, req);
  479. }
  480. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  481. {
  482. struct m66592 *m66592 = ep->m66592;
  483. u16 pipenum = ep->pipenum;
  484. if (ep->pipenum == 0) {
  485. m66592_mdfy(m66592, M66592_PIPE0,
  486. (M66592_ISEL | M66592_CURPIPE),
  487. M66592_CFIFOSEL);
  488. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  489. pipe_start(m66592, pipenum);
  490. pipe_irq_enable(m66592, pipenum);
  491. } else {
  492. if (ep->use_dma) {
  493. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  494. pipe_change(m66592, pipenum);
  495. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  496. m66592_write(m66592,
  497. (req->req.length + ep->ep.maxpacket - 1)
  498. / ep->ep.maxpacket,
  499. ep->fifotrn);
  500. }
  501. pipe_start(m66592, pipenum); /* trigger once */
  502. pipe_irq_enable(m66592, pipenum);
  503. }
  504. }
  505. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  506. {
  507. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  508. start_packet_write(ep, req);
  509. else
  510. start_packet_read(ep, req);
  511. }
  512. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  513. {
  514. u16 ctsq;
  515. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  516. switch (ctsq) {
  517. case M66592_CS_RDDS:
  518. start_ep0_write(ep, req);
  519. break;
  520. case M66592_CS_WRDS:
  521. start_packet_read(ep, req);
  522. break;
  523. case M66592_CS_WRND:
  524. control_end(ep->m66592, 0);
  525. break;
  526. default:
  527. pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
  528. break;
  529. }
  530. }
  531. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  532. static void init_controller(struct m66592 *m66592)
  533. {
  534. usbf_start_clock();
  535. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  536. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  537. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  538. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  539. /* This is a workaound for SH7722 2nd cut */
  540. m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
  541. m66592_bset(m66592, 0x1000, M66592_TESTMODE);
  542. m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
  543. m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
  544. m66592_write(m66592, 0, M66592_CFBCFG);
  545. m66592_write(m66592, 0, M66592_D0FBCFG);
  546. m66592_bset(m66592, endian, M66592_CFBCFG);
  547. m66592_bset(m66592, endian, M66592_D0FBCFG);
  548. }
  549. #else /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
  550. static void init_controller(struct m66592 *m66592)
  551. {
  552. m66592_bset(m66592, (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  553. M66592_PINCFG);
  554. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  555. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL, M66592_SYSCFG);
  556. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  557. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  558. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  559. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  560. msleep(3);
  561. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  562. msleep(1);
  563. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  564. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  565. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  566. M66592_DMA0CFG);
  567. }
  568. #endif /* #if defined(CONFIG_SUPERH_BUILT_IN_M66592) */
  569. static void disable_controller(struct m66592 *m66592)
  570. {
  571. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  572. usbf_stop_clock();
  573. #else
  574. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  575. udelay(1);
  576. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  577. udelay(1);
  578. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  579. udelay(1);
  580. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  581. #endif
  582. }
  583. static void m66592_start_xclock(struct m66592 *m66592)
  584. {
  585. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  586. usbf_start_clock();
  587. #else
  588. u16 tmp;
  589. tmp = m66592_read(m66592, M66592_SYSCFG);
  590. if (!(tmp & M66592_XCKE))
  591. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  592. #endif
  593. }
  594. /*-------------------------------------------------------------------------*/
  595. static void transfer_complete(struct m66592_ep *ep,
  596. struct m66592_request *req, int status)
  597. __releases(m66592->lock)
  598. __acquires(m66592->lock)
  599. {
  600. int restart = 0;
  601. if (unlikely(ep->pipenum == 0)) {
  602. if (ep->internal_ccpl) {
  603. ep->internal_ccpl = 0;
  604. return;
  605. }
  606. }
  607. list_del_init(&req->queue);
  608. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  609. req->req.status = -ESHUTDOWN;
  610. else
  611. req->req.status = status;
  612. if (!list_empty(&ep->queue))
  613. restart = 1;
  614. spin_unlock(&ep->m66592->lock);
  615. req->req.complete(&ep->ep, &req->req);
  616. spin_lock(&ep->m66592->lock);
  617. if (restart) {
  618. req = list_entry(ep->queue.next, struct m66592_request, queue);
  619. if (ep->desc)
  620. start_packet(ep, req);
  621. }
  622. }
  623. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  624. {
  625. int i;
  626. u16 tmp;
  627. unsigned bufsize;
  628. size_t size;
  629. void *buf;
  630. u16 pipenum = ep->pipenum;
  631. struct m66592 *m66592 = ep->m66592;
  632. pipe_change(m66592, pipenum);
  633. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  634. i = 0;
  635. do {
  636. tmp = m66592_read(m66592, ep->fifoctr);
  637. if (i++ > 100000) {
  638. pr_err("pipe0 is busy. maybe cpu i/o bus "
  639. "conflict. please power off this controller.");
  640. return;
  641. }
  642. ndelay(1);
  643. } while ((tmp & M66592_FRDY) == 0);
  644. /* prepare parameters */
  645. bufsize = get_buffer_size(m66592, pipenum);
  646. buf = req->req.buf + req->req.actual;
  647. size = min(bufsize, req->req.length - req->req.actual);
  648. /* write fifo */
  649. if (req->req.buf) {
  650. if (size > 0)
  651. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  652. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  653. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  654. }
  655. /* update parameters */
  656. req->req.actual += size;
  657. /* check transfer finish */
  658. if ((!req->req.zero && (req->req.actual == req->req.length))
  659. || (size % ep->ep.maxpacket)
  660. || (size == 0)) {
  661. disable_irq_ready(m66592, pipenum);
  662. disable_irq_empty(m66592, pipenum);
  663. } else {
  664. disable_irq_ready(m66592, pipenum);
  665. enable_irq_empty(m66592, pipenum);
  666. }
  667. pipe_start(m66592, pipenum);
  668. }
  669. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  670. {
  671. u16 tmp;
  672. unsigned bufsize;
  673. size_t size;
  674. void *buf;
  675. u16 pipenum = ep->pipenum;
  676. struct m66592 *m66592 = ep->m66592;
  677. pipe_change(m66592, pipenum);
  678. tmp = m66592_read(m66592, ep->fifoctr);
  679. if (unlikely((tmp & M66592_FRDY) == 0)) {
  680. pipe_stop(m66592, pipenum);
  681. pipe_irq_disable(m66592, pipenum);
  682. pr_err("write fifo not ready. pipnum=%d\n", pipenum);
  683. return;
  684. }
  685. /* prepare parameters */
  686. bufsize = get_buffer_size(m66592, pipenum);
  687. buf = req->req.buf + req->req.actual;
  688. size = min(bufsize, req->req.length - req->req.actual);
  689. /* write fifo */
  690. if (req->req.buf) {
  691. m66592_write_fifo(m66592, ep->fifoaddr, buf, size);
  692. if ((size == 0)
  693. || ((size % ep->ep.maxpacket) != 0)
  694. || ((bufsize != ep->ep.maxpacket)
  695. && (bufsize > size)))
  696. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  697. }
  698. /* update parameters */
  699. req->req.actual += size;
  700. /* check transfer finish */
  701. if ((!req->req.zero && (req->req.actual == req->req.length))
  702. || (size % ep->ep.maxpacket)
  703. || (size == 0)) {
  704. disable_irq_ready(m66592, pipenum);
  705. enable_irq_empty(m66592, pipenum);
  706. } else {
  707. disable_irq_empty(m66592, pipenum);
  708. pipe_irq_enable(m66592, pipenum);
  709. }
  710. }
  711. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  712. {
  713. u16 tmp;
  714. int rcv_len, bufsize, req_len;
  715. int size;
  716. void *buf;
  717. u16 pipenum = ep->pipenum;
  718. struct m66592 *m66592 = ep->m66592;
  719. int finish = 0;
  720. pipe_change(m66592, pipenum);
  721. tmp = m66592_read(m66592, ep->fifoctr);
  722. if (unlikely((tmp & M66592_FRDY) == 0)) {
  723. req->req.status = -EPIPE;
  724. pipe_stop(m66592, pipenum);
  725. pipe_irq_disable(m66592, pipenum);
  726. pr_err("read fifo not ready");
  727. return;
  728. }
  729. /* prepare parameters */
  730. rcv_len = tmp & M66592_DTLN;
  731. bufsize = get_buffer_size(m66592, pipenum);
  732. buf = req->req.buf + req->req.actual;
  733. req_len = req->req.length - req->req.actual;
  734. if (rcv_len < bufsize)
  735. size = min(rcv_len, req_len);
  736. else
  737. size = min(bufsize, req_len);
  738. /* update parameters */
  739. req->req.actual += size;
  740. /* check transfer finish */
  741. if ((!req->req.zero && (req->req.actual == req->req.length))
  742. || (size % ep->ep.maxpacket)
  743. || (size == 0)) {
  744. pipe_stop(m66592, pipenum);
  745. pipe_irq_disable(m66592, pipenum);
  746. finish = 1;
  747. }
  748. /* read fifo */
  749. if (req->req.buf) {
  750. if (size == 0)
  751. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  752. else
  753. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  754. }
  755. if ((ep->pipenum != 0) && finish)
  756. transfer_complete(ep, req, 0);
  757. }
  758. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  759. {
  760. u16 check;
  761. u16 pipenum;
  762. struct m66592_ep *ep;
  763. struct m66592_request *req;
  764. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  765. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  766. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  767. M66592_CFIFOSEL);
  768. ep = &m66592->ep[0];
  769. req = list_entry(ep->queue.next, struct m66592_request, queue);
  770. irq_packet_read(ep, req);
  771. } else {
  772. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  773. check = 1 << pipenum;
  774. if ((status & check) && (enb & check)) {
  775. m66592_write(m66592, ~check, M66592_BRDYSTS);
  776. ep = m66592->pipenum2ep[pipenum];
  777. req = list_entry(ep->queue.next,
  778. struct m66592_request, queue);
  779. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  780. irq_packet_write(ep, req);
  781. else
  782. irq_packet_read(ep, req);
  783. }
  784. }
  785. }
  786. }
  787. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  788. {
  789. u16 tmp;
  790. u16 check;
  791. u16 pipenum;
  792. struct m66592_ep *ep;
  793. struct m66592_request *req;
  794. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  795. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  796. ep = &m66592->ep[0];
  797. req = list_entry(ep->queue.next, struct m66592_request, queue);
  798. irq_ep0_write(ep, req);
  799. } else {
  800. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  801. check = 1 << pipenum;
  802. if ((status & check) && (enb & check)) {
  803. m66592_write(m66592, ~check, M66592_BEMPSTS);
  804. tmp = control_reg_get(m66592, pipenum);
  805. if ((tmp & M66592_INBUFM) == 0) {
  806. disable_irq_empty(m66592, pipenum);
  807. pipe_irq_disable(m66592, pipenum);
  808. pipe_stop(m66592, pipenum);
  809. ep = m66592->pipenum2ep[pipenum];
  810. req = list_entry(ep->queue.next,
  811. struct m66592_request,
  812. queue);
  813. if (!list_empty(&ep->queue))
  814. transfer_complete(ep, req, 0);
  815. }
  816. }
  817. }
  818. }
  819. }
  820. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  821. __releases(m66592->lock)
  822. __acquires(m66592->lock)
  823. {
  824. struct m66592_ep *ep;
  825. u16 pid;
  826. u16 status = 0;
  827. u16 w_index = le16_to_cpu(ctrl->wIndex);
  828. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  829. case USB_RECIP_DEVICE:
  830. status = 1 << USB_DEVICE_SELF_POWERED;
  831. break;
  832. case USB_RECIP_INTERFACE:
  833. status = 0;
  834. break;
  835. case USB_RECIP_ENDPOINT:
  836. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  837. pid = control_reg_get_pid(m66592, ep->pipenum);
  838. if (pid == M66592_PID_STALL)
  839. status = 1 << USB_ENDPOINT_HALT;
  840. else
  841. status = 0;
  842. break;
  843. default:
  844. pipe_stall(m66592, 0);
  845. return; /* exit */
  846. }
  847. m66592->ep0_data = cpu_to_le16(status);
  848. m66592->ep0_req->buf = &m66592->ep0_data;
  849. m66592->ep0_req->length = 2;
  850. /* AV: what happens if we get called again before that gets through? */
  851. spin_unlock(&m66592->lock);
  852. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  853. spin_lock(&m66592->lock);
  854. }
  855. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  856. {
  857. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  858. case USB_RECIP_DEVICE:
  859. control_end(m66592, 1);
  860. break;
  861. case USB_RECIP_INTERFACE:
  862. control_end(m66592, 1);
  863. break;
  864. case USB_RECIP_ENDPOINT: {
  865. struct m66592_ep *ep;
  866. struct m66592_request *req;
  867. u16 w_index = le16_to_cpu(ctrl->wIndex);
  868. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  869. pipe_stop(m66592, ep->pipenum);
  870. control_reg_sqclr(m66592, ep->pipenum);
  871. control_end(m66592, 1);
  872. req = list_entry(ep->queue.next,
  873. struct m66592_request, queue);
  874. if (ep->busy) {
  875. ep->busy = 0;
  876. if (list_empty(&ep->queue))
  877. break;
  878. start_packet(ep, req);
  879. } else if (!list_empty(&ep->queue))
  880. pipe_start(m66592, ep->pipenum);
  881. }
  882. break;
  883. default:
  884. pipe_stall(m66592, 0);
  885. break;
  886. }
  887. }
  888. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  889. {
  890. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  891. case USB_RECIP_DEVICE:
  892. control_end(m66592, 1);
  893. break;
  894. case USB_RECIP_INTERFACE:
  895. control_end(m66592, 1);
  896. break;
  897. case USB_RECIP_ENDPOINT: {
  898. struct m66592_ep *ep;
  899. u16 w_index = le16_to_cpu(ctrl->wIndex);
  900. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  901. pipe_stall(m66592, ep->pipenum);
  902. control_end(m66592, 1);
  903. }
  904. break;
  905. default:
  906. pipe_stall(m66592, 0);
  907. break;
  908. }
  909. }
  910. /* if return value is true, call class driver's setup() */
  911. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  912. {
  913. u16 *p = (u16 *)ctrl;
  914. unsigned long offset = M66592_USBREQ;
  915. int i, ret = 0;
  916. /* read fifo */
  917. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  918. for (i = 0; i < 4; i++)
  919. p[i] = m66592_read(m66592, offset + i*2);
  920. /* check request */
  921. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  922. switch (ctrl->bRequest) {
  923. case USB_REQ_GET_STATUS:
  924. get_status(m66592, ctrl);
  925. break;
  926. case USB_REQ_CLEAR_FEATURE:
  927. clear_feature(m66592, ctrl);
  928. break;
  929. case USB_REQ_SET_FEATURE:
  930. set_feature(m66592, ctrl);
  931. break;
  932. default:
  933. ret = 1;
  934. break;
  935. }
  936. } else
  937. ret = 1;
  938. return ret;
  939. }
  940. static void m66592_update_usb_speed(struct m66592 *m66592)
  941. {
  942. u16 speed = get_usb_speed(m66592);
  943. switch (speed) {
  944. case M66592_HSMODE:
  945. m66592->gadget.speed = USB_SPEED_HIGH;
  946. break;
  947. case M66592_FSMODE:
  948. m66592->gadget.speed = USB_SPEED_FULL;
  949. break;
  950. default:
  951. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  952. pr_err("USB speed unknown\n");
  953. }
  954. }
  955. static void irq_device_state(struct m66592 *m66592)
  956. {
  957. u16 dvsq;
  958. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  959. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  960. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  961. m66592->driver->disconnect(&m66592->gadget);
  962. m66592_update_usb_speed(m66592);
  963. }
  964. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  965. m66592_update_usb_speed(m66592);
  966. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
  967. && m66592->gadget.speed == USB_SPEED_UNKNOWN)
  968. m66592_update_usb_speed(m66592);
  969. m66592->old_dvsq = dvsq;
  970. }
  971. static void irq_control_stage(struct m66592 *m66592)
  972. __releases(m66592->lock)
  973. __acquires(m66592->lock)
  974. {
  975. struct usb_ctrlrequest ctrl;
  976. u16 ctsq;
  977. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  978. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  979. switch (ctsq) {
  980. case M66592_CS_IDST: {
  981. struct m66592_ep *ep;
  982. struct m66592_request *req;
  983. ep = &m66592->ep[0];
  984. req = list_entry(ep->queue.next, struct m66592_request, queue);
  985. transfer_complete(ep, req, 0);
  986. }
  987. break;
  988. case M66592_CS_RDDS:
  989. case M66592_CS_WRDS:
  990. case M66592_CS_WRND:
  991. if (setup_packet(m66592, &ctrl)) {
  992. spin_unlock(&m66592->lock);
  993. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  994. pipe_stall(m66592, 0);
  995. spin_lock(&m66592->lock);
  996. }
  997. break;
  998. case M66592_CS_RDSS:
  999. case M66592_CS_WRSS:
  1000. control_end(m66592, 0);
  1001. break;
  1002. default:
  1003. pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1004. break;
  1005. }
  1006. }
  1007. static irqreturn_t m66592_irq(int irq, void *_m66592)
  1008. {
  1009. struct m66592 *m66592 = _m66592;
  1010. u16 intsts0;
  1011. u16 intenb0;
  1012. u16 brdysts, nrdysts, bempsts;
  1013. u16 brdyenb, nrdyenb, bempenb;
  1014. u16 savepipe;
  1015. u16 mask0;
  1016. spin_lock(&m66592->lock);
  1017. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1018. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1019. #if defined(CONFIG_SUPERH_BUILT_IN_M66592)
  1020. if (!intsts0 && !intenb0) {
  1021. /*
  1022. * When USB clock stops, it cannot read register. Even if a
  1023. * clock stops, the interrupt occurs. So this driver turn on
  1024. * a clock by this timing and do re-reading of register.
  1025. */
  1026. m66592_start_xclock(m66592);
  1027. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1028. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1029. }
  1030. #endif
  1031. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  1032. mask0 = intsts0 & intenb0;
  1033. if (mask0) {
  1034. brdysts = m66592_read(m66592, M66592_BRDYSTS);
  1035. nrdysts = m66592_read(m66592, M66592_NRDYSTS);
  1036. bempsts = m66592_read(m66592, M66592_BEMPSTS);
  1037. brdyenb = m66592_read(m66592, M66592_BRDYENB);
  1038. nrdyenb = m66592_read(m66592, M66592_NRDYENB);
  1039. bempenb = m66592_read(m66592, M66592_BEMPENB);
  1040. if (mask0 & M66592_VBINT) {
  1041. m66592_write(m66592, 0xffff & ~M66592_VBINT,
  1042. M66592_INTSTS0);
  1043. m66592_start_xclock(m66592);
  1044. /* start vbus sampling */
  1045. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  1046. & M66592_VBSTS;
  1047. m66592->scount = M66592_MAX_SAMPLING;
  1048. mod_timer(&m66592->timer,
  1049. jiffies + msecs_to_jiffies(50));
  1050. }
  1051. if (intsts0 & M66592_DVSQ)
  1052. irq_device_state(m66592);
  1053. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
  1054. && (brdysts & brdyenb)) {
  1055. irq_pipe_ready(m66592, brdysts, brdyenb);
  1056. }
  1057. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
  1058. && (bempsts & bempenb)) {
  1059. irq_pipe_empty(m66592, bempsts, bempenb);
  1060. }
  1061. if (intsts0 & M66592_CTRT)
  1062. irq_control_stage(m66592);
  1063. }
  1064. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1065. spin_unlock(&m66592->lock);
  1066. return IRQ_HANDLED;
  1067. }
  1068. static void m66592_timer(unsigned long _m66592)
  1069. {
  1070. struct m66592 *m66592 = (struct m66592 *)_m66592;
  1071. unsigned long flags;
  1072. u16 tmp;
  1073. spin_lock_irqsave(&m66592->lock, flags);
  1074. tmp = m66592_read(m66592, M66592_SYSCFG);
  1075. if (!(tmp & M66592_RCKE)) {
  1076. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1077. udelay(10);
  1078. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1079. }
  1080. if (m66592->scount > 0) {
  1081. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1082. if (tmp == m66592->old_vbus) {
  1083. m66592->scount--;
  1084. if (m66592->scount == 0) {
  1085. if (tmp == M66592_VBSTS)
  1086. m66592_usb_connect(m66592);
  1087. else
  1088. m66592_usb_disconnect(m66592);
  1089. } else {
  1090. mod_timer(&m66592->timer,
  1091. jiffies + msecs_to_jiffies(50));
  1092. }
  1093. } else {
  1094. m66592->scount = M66592_MAX_SAMPLING;
  1095. m66592->old_vbus = tmp;
  1096. mod_timer(&m66592->timer,
  1097. jiffies + msecs_to_jiffies(50));
  1098. }
  1099. }
  1100. spin_unlock_irqrestore(&m66592->lock, flags);
  1101. }
  1102. /*-------------------------------------------------------------------------*/
  1103. static int m66592_enable(struct usb_ep *_ep,
  1104. const struct usb_endpoint_descriptor *desc)
  1105. {
  1106. struct m66592_ep *ep;
  1107. ep = container_of(_ep, struct m66592_ep, ep);
  1108. return alloc_pipe_config(ep, desc);
  1109. }
  1110. static int m66592_disable(struct usb_ep *_ep)
  1111. {
  1112. struct m66592_ep *ep;
  1113. struct m66592_request *req;
  1114. unsigned long flags;
  1115. ep = container_of(_ep, struct m66592_ep, ep);
  1116. BUG_ON(!ep);
  1117. while (!list_empty(&ep->queue)) {
  1118. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1119. spin_lock_irqsave(&ep->m66592->lock, flags);
  1120. transfer_complete(ep, req, -ECONNRESET);
  1121. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1122. }
  1123. pipe_irq_disable(ep->m66592, ep->pipenum);
  1124. return free_pipe_config(ep);
  1125. }
  1126. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1127. gfp_t gfp_flags)
  1128. {
  1129. struct m66592_request *req;
  1130. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1131. if (!req)
  1132. return NULL;
  1133. INIT_LIST_HEAD(&req->queue);
  1134. return &req->req;
  1135. }
  1136. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1137. {
  1138. struct m66592_request *req;
  1139. req = container_of(_req, struct m66592_request, req);
  1140. kfree(req);
  1141. }
  1142. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1143. gfp_t gfp_flags)
  1144. {
  1145. struct m66592_ep *ep;
  1146. struct m66592_request *req;
  1147. unsigned long flags;
  1148. int request = 0;
  1149. ep = container_of(_ep, struct m66592_ep, ep);
  1150. req = container_of(_req, struct m66592_request, req);
  1151. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1152. return -ESHUTDOWN;
  1153. spin_lock_irqsave(&ep->m66592->lock, flags);
  1154. if (list_empty(&ep->queue))
  1155. request = 1;
  1156. list_add_tail(&req->queue, &ep->queue);
  1157. req->req.actual = 0;
  1158. req->req.status = -EINPROGRESS;
  1159. if (ep->desc == NULL) /* control */
  1160. start_ep0(ep, req);
  1161. else {
  1162. if (request && !ep->busy)
  1163. start_packet(ep, req);
  1164. }
  1165. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1166. return 0;
  1167. }
  1168. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1169. {
  1170. struct m66592_ep *ep;
  1171. struct m66592_request *req;
  1172. unsigned long flags;
  1173. ep = container_of(_ep, struct m66592_ep, ep);
  1174. req = container_of(_req, struct m66592_request, req);
  1175. spin_lock_irqsave(&ep->m66592->lock, flags);
  1176. if (!list_empty(&ep->queue))
  1177. transfer_complete(ep, req, -ECONNRESET);
  1178. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1179. return 0;
  1180. }
  1181. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1182. {
  1183. struct m66592_ep *ep;
  1184. struct m66592_request *req;
  1185. unsigned long flags;
  1186. int ret = 0;
  1187. ep = container_of(_ep, struct m66592_ep, ep);
  1188. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1189. spin_lock_irqsave(&ep->m66592->lock, flags);
  1190. if (!list_empty(&ep->queue)) {
  1191. ret = -EAGAIN;
  1192. goto out;
  1193. }
  1194. if (value) {
  1195. ep->busy = 1;
  1196. pipe_stall(ep->m66592, ep->pipenum);
  1197. } else {
  1198. ep->busy = 0;
  1199. pipe_stop(ep->m66592, ep->pipenum);
  1200. }
  1201. out:
  1202. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1203. return ret;
  1204. }
  1205. static void m66592_fifo_flush(struct usb_ep *_ep)
  1206. {
  1207. struct m66592_ep *ep;
  1208. unsigned long flags;
  1209. ep = container_of(_ep, struct m66592_ep, ep);
  1210. spin_lock_irqsave(&ep->m66592->lock, flags);
  1211. if (list_empty(&ep->queue) && !ep->busy) {
  1212. pipe_stop(ep->m66592, ep->pipenum);
  1213. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1214. }
  1215. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1216. }
  1217. static struct usb_ep_ops m66592_ep_ops = {
  1218. .enable = m66592_enable,
  1219. .disable = m66592_disable,
  1220. .alloc_request = m66592_alloc_request,
  1221. .free_request = m66592_free_request,
  1222. .queue = m66592_queue,
  1223. .dequeue = m66592_dequeue,
  1224. .set_halt = m66592_set_halt,
  1225. .fifo_flush = m66592_fifo_flush,
  1226. };
  1227. /*-------------------------------------------------------------------------*/
  1228. static struct m66592 *the_controller;
  1229. int usb_gadget_register_driver(struct usb_gadget_driver *driver)
  1230. {
  1231. struct m66592 *m66592 = the_controller;
  1232. int retval;
  1233. if (!driver
  1234. || driver->speed != USB_SPEED_HIGH
  1235. || !driver->bind
  1236. || !driver->setup)
  1237. return -EINVAL;
  1238. if (!m66592)
  1239. return -ENODEV;
  1240. if (m66592->driver)
  1241. return -EBUSY;
  1242. /* hook up the driver */
  1243. driver->driver.bus = NULL;
  1244. m66592->driver = driver;
  1245. m66592->gadget.dev.driver = &driver->driver;
  1246. retval = device_add(&m66592->gadget.dev);
  1247. if (retval) {
  1248. pr_err("device_add error (%d)\n", retval);
  1249. goto error;
  1250. }
  1251. retval = driver->bind (&m66592->gadget);
  1252. if (retval) {
  1253. pr_err("bind to driver error (%d)\n", retval);
  1254. device_del(&m66592->gadget.dev);
  1255. goto error;
  1256. }
  1257. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1258. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1259. m66592_start_xclock(m66592);
  1260. /* start vbus sampling */
  1261. m66592->old_vbus = m66592_read(m66592,
  1262. M66592_INTSTS0) & M66592_VBSTS;
  1263. m66592->scount = M66592_MAX_SAMPLING;
  1264. mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
  1265. }
  1266. return 0;
  1267. error:
  1268. m66592->driver = NULL;
  1269. m66592->gadget.dev.driver = NULL;
  1270. return retval;
  1271. }
  1272. EXPORT_SYMBOL(usb_gadget_register_driver);
  1273. int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
  1274. {
  1275. struct m66592 *m66592 = the_controller;
  1276. unsigned long flags;
  1277. if (driver != m66592->driver || !driver->unbind)
  1278. return -EINVAL;
  1279. spin_lock_irqsave(&m66592->lock, flags);
  1280. if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
  1281. m66592_usb_disconnect(m66592);
  1282. spin_unlock_irqrestore(&m66592->lock, flags);
  1283. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1284. driver->unbind(&m66592->gadget);
  1285. m66592->gadget.dev.driver = NULL;
  1286. init_controller(m66592);
  1287. disable_controller(m66592);
  1288. device_del(&m66592->gadget.dev);
  1289. m66592->driver = NULL;
  1290. return 0;
  1291. }
  1292. EXPORT_SYMBOL(usb_gadget_unregister_driver);
  1293. /*-------------------------------------------------------------------------*/
  1294. static int m66592_get_frame(struct usb_gadget *_gadget)
  1295. {
  1296. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1297. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1298. }
  1299. static struct usb_gadget_ops m66592_gadget_ops = {
  1300. .get_frame = m66592_get_frame,
  1301. };
  1302. static int __exit m66592_remove(struct platform_device *pdev)
  1303. {
  1304. struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
  1305. del_timer_sync(&m66592->timer);
  1306. iounmap(m66592->reg);
  1307. free_irq(platform_get_irq(pdev, 0), m66592);
  1308. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1309. usbf_stop_clock();
  1310. kfree(m66592);
  1311. return 0;
  1312. }
  1313. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1314. {
  1315. }
  1316. #define resource_len(r) (((r)->end - (r)->start) + 1)
  1317. static int __init m66592_probe(struct platform_device *pdev)
  1318. {
  1319. struct resource *res;
  1320. int irq;
  1321. void __iomem *reg = NULL;
  1322. struct m66592 *m66592 = NULL;
  1323. int ret = 0;
  1324. int i;
  1325. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  1326. (char *)udc_name);
  1327. if (!res) {
  1328. ret = -ENODEV;
  1329. pr_err("platform_get_resource_byname error.\n");
  1330. goto clean_up;
  1331. }
  1332. irq = platform_get_irq(pdev, 0);
  1333. if (irq < 0) {
  1334. ret = -ENODEV;
  1335. pr_err("platform_get_irq error.\n");
  1336. goto clean_up;
  1337. }
  1338. reg = ioremap(res->start, resource_len(res));
  1339. if (reg == NULL) {
  1340. ret = -ENOMEM;
  1341. pr_err("ioremap error.\n");
  1342. goto clean_up;
  1343. }
  1344. /* initialize ucd */
  1345. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1346. if (m66592 == NULL) {
  1347. pr_err("kzalloc error\n");
  1348. goto clean_up;
  1349. }
  1350. spin_lock_init(&m66592->lock);
  1351. dev_set_drvdata(&pdev->dev, m66592);
  1352. m66592->gadget.ops = &m66592_gadget_ops;
  1353. device_initialize(&m66592->gadget.dev);
  1354. dev_set_name(&m66592->gadget.dev, "gadget");
  1355. m66592->gadget.is_dualspeed = 1;
  1356. m66592->gadget.dev.parent = &pdev->dev;
  1357. m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1358. m66592->gadget.dev.release = pdev->dev.release;
  1359. m66592->gadget.name = udc_name;
  1360. init_timer(&m66592->timer);
  1361. m66592->timer.function = m66592_timer;
  1362. m66592->timer.data = (unsigned long)m66592;
  1363. m66592->reg = reg;
  1364. m66592->bi_bufnum = M66592_BASE_BUFNUM;
  1365. ret = request_irq(irq, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
  1366. udc_name, m66592);
  1367. if (ret < 0) {
  1368. pr_err("request_irq error (%d)\n", ret);
  1369. goto clean_up;
  1370. }
  1371. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1372. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1373. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1374. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1375. struct m66592_ep *ep = &m66592->ep[i];
  1376. if (i != 0) {
  1377. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1378. list_add_tail(&m66592->ep[i].ep.ep_list,
  1379. &m66592->gadget.ep_list);
  1380. }
  1381. ep->m66592 = m66592;
  1382. INIT_LIST_HEAD(&ep->queue);
  1383. ep->ep.name = m66592_ep_name[i];
  1384. ep->ep.ops = &m66592_ep_ops;
  1385. ep->ep.maxpacket = 512;
  1386. }
  1387. m66592->ep[0].ep.maxpacket = 64;
  1388. m66592->ep[0].pipenum = 0;
  1389. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1390. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1391. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1392. m66592->ep[0].fifotrn = 0;
  1393. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1394. m66592->pipenum2ep[0] = &m66592->ep[0];
  1395. m66592->epaddr2ep[0] = &m66592->ep[0];
  1396. the_controller = m66592;
  1397. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1398. if (m66592->ep0_req == NULL)
  1399. goto clean_up2;
  1400. m66592->ep0_req->complete = nop_completion;
  1401. init_controller(m66592);
  1402. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1403. return 0;
  1404. clean_up2:
  1405. free_irq(irq, m66592);
  1406. clean_up:
  1407. if (m66592) {
  1408. if (m66592->ep0_req)
  1409. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1410. kfree(m66592);
  1411. }
  1412. if (reg)
  1413. iounmap(reg);
  1414. return ret;
  1415. }
  1416. /*-------------------------------------------------------------------------*/
  1417. static struct platform_driver m66592_driver = {
  1418. .remove = __exit_p(m66592_remove),
  1419. .driver = {
  1420. .name = (char *) udc_name,
  1421. .owner = THIS_MODULE,
  1422. },
  1423. };
  1424. static int __init m66592_udc_init(void)
  1425. {
  1426. return platform_driver_probe(&m66592_driver, m66592_probe);
  1427. }
  1428. module_init(m66592_udc_init);
  1429. static void __exit m66592_udc_cleanup(void)
  1430. {
  1431. platform_driver_unregister(&m66592_driver);
  1432. }
  1433. module_exit(m66592_udc_cleanup);