pnx8xxx_uart.c 21 KB

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  1. /*
  2. * UART driver for PNX8XXX SoCs
  3. *
  4. * Author: Per Hallsmark per.hallsmark@mvista.com
  5. * Ported to 2.6 kernel by EmbeddedAlley
  6. * Reworked by Vitaly Wool <vitalywool@gmail.com>
  7. *
  8. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  9. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  10. *
  11. * This file is licensed under the terms of the GNU General Public License
  12. * version 2. This program is licensed "as is" without any warranty of
  13. * any kind, whether express or implied.
  14. *
  15. */
  16. #if defined(CONFIG_SERIAL_PNX8XXX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  17. #define SUPPORT_SYSRQ
  18. #endif
  19. #include <linux/module.h>
  20. #include <linux/ioport.h>
  21. #include <linux/init.h>
  22. #include <linux/console.h>
  23. #include <linux/sysrq.h>
  24. #include <linux/device.h>
  25. #include <linux/platform_device.h>
  26. #include <linux/tty.h>
  27. #include <linux/tty_flip.h>
  28. #include <linux/serial_core.h>
  29. #include <linux/serial.h>
  30. #include <linux/serial_pnx8xxx.h>
  31. #include <asm/io.h>
  32. #include <asm/irq.h>
  33. /* We'll be using StrongARM sa1100 serial port major/minor */
  34. #define SERIAL_PNX8XXX_MAJOR 204
  35. #define MINOR_START 5
  36. #define NR_PORTS 2
  37. #define PNX8XXX_ISR_PASS_LIMIT 256
  38. /*
  39. * Convert from ignore_status_mask or read_status_mask to FIFO
  40. * and interrupt status bits
  41. */
  42. #define SM_TO_FIFO(x) ((x) >> 10)
  43. #define SM_TO_ISTAT(x) ((x) & 0x000001ff)
  44. #define FIFO_TO_SM(x) ((x) << 10)
  45. #define ISTAT_TO_SM(x) ((x) & 0x000001ff)
  46. /*
  47. * This is the size of our serial port register set.
  48. */
  49. #define UART_PORT_SIZE 0x1000
  50. /*
  51. * This determines how often we check the modem status signals
  52. * for any change. They generally aren't connected to an IRQ
  53. * so we have to poll them. We also check immediately before
  54. * filling the TX fifo incase CTS has been dropped.
  55. */
  56. #define MCTRL_TIMEOUT (250*HZ/1000)
  57. extern struct pnx8xxx_port pnx8xxx_ports[];
  58. static inline int serial_in(struct pnx8xxx_port *sport, int offset)
  59. {
  60. return (__raw_readl(sport->port.membase + offset));
  61. }
  62. static inline void serial_out(struct pnx8xxx_port *sport, int offset, int value)
  63. {
  64. __raw_writel(value, sport->port.membase + offset);
  65. }
  66. /*
  67. * Handle any change of modem status signal since we were last called.
  68. */
  69. static void pnx8xxx_mctrl_check(struct pnx8xxx_port *sport)
  70. {
  71. unsigned int status, changed;
  72. status = sport->port.ops->get_mctrl(&sport->port);
  73. changed = status ^ sport->old_status;
  74. if (changed == 0)
  75. return;
  76. sport->old_status = status;
  77. if (changed & TIOCM_RI)
  78. sport->port.icount.rng++;
  79. if (changed & TIOCM_DSR)
  80. sport->port.icount.dsr++;
  81. if (changed & TIOCM_CAR)
  82. uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
  83. if (changed & TIOCM_CTS)
  84. uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
  85. wake_up_interruptible(&sport->port.info->delta_msr_wait);
  86. }
  87. /*
  88. * This is our per-port timeout handler, for checking the
  89. * modem status signals.
  90. */
  91. static void pnx8xxx_timeout(unsigned long data)
  92. {
  93. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)data;
  94. unsigned long flags;
  95. if (sport->port.info) {
  96. spin_lock_irqsave(&sport->port.lock, flags);
  97. pnx8xxx_mctrl_check(sport);
  98. spin_unlock_irqrestore(&sport->port.lock, flags);
  99. mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
  100. }
  101. }
  102. /*
  103. * interrupts disabled on entry
  104. */
  105. static void pnx8xxx_stop_tx(struct uart_port *port)
  106. {
  107. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  108. u32 ien;
  109. /* Disable TX intr */
  110. ien = serial_in(sport, PNX8XXX_IEN);
  111. serial_out(sport, PNX8XXX_IEN, ien & ~PNX8XXX_UART_INT_ALLTX);
  112. /* Clear all pending TX intr */
  113. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLTX);
  114. }
  115. /*
  116. * interrupts may not be disabled on entry
  117. */
  118. static void pnx8xxx_start_tx(struct uart_port *port)
  119. {
  120. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  121. u32 ien;
  122. /* Clear all pending TX intr */
  123. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLTX);
  124. /* Enable TX intr */
  125. ien = serial_in(sport, PNX8XXX_IEN);
  126. serial_out(sport, PNX8XXX_IEN, ien | PNX8XXX_UART_INT_ALLTX);
  127. }
  128. /*
  129. * Interrupts enabled
  130. */
  131. static void pnx8xxx_stop_rx(struct uart_port *port)
  132. {
  133. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  134. u32 ien;
  135. /* Disable RX intr */
  136. ien = serial_in(sport, PNX8XXX_IEN);
  137. serial_out(sport, PNX8XXX_IEN, ien & ~PNX8XXX_UART_INT_ALLRX);
  138. /* Clear all pending RX intr */
  139. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX);
  140. }
  141. /*
  142. * Set the modem control timer to fire immediately.
  143. */
  144. static void pnx8xxx_enable_ms(struct uart_port *port)
  145. {
  146. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  147. mod_timer(&sport->timer, jiffies);
  148. }
  149. static void pnx8xxx_rx_chars(struct pnx8xxx_port *sport)
  150. {
  151. struct tty_struct *tty = sport->port.info->port.tty;
  152. unsigned int status, ch, flg;
  153. status = FIFO_TO_SM(serial_in(sport, PNX8XXX_FIFO)) |
  154. ISTAT_TO_SM(serial_in(sport, PNX8XXX_ISTAT));
  155. while (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFIFO)) {
  156. ch = serial_in(sport, PNX8XXX_FIFO);
  157. sport->port.icount.rx++;
  158. flg = TTY_NORMAL;
  159. /*
  160. * note that the error handling code is
  161. * out of the main execution path
  162. */
  163. if (status & (FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE |
  164. PNX8XXX_UART_FIFO_RXPAR) |
  165. ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN))) {
  166. if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR))
  167. sport->port.icount.parity++;
  168. else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE))
  169. sport->port.icount.frame++;
  170. if (status & ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN))
  171. sport->port.icount.overrun++;
  172. status &= sport->port.read_status_mask;
  173. if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR))
  174. flg = TTY_PARITY;
  175. else if (status & FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE))
  176. flg = TTY_FRAME;
  177. #ifdef SUPPORT_SYSRQ
  178. sport->port.sysrq = 0;
  179. #endif
  180. }
  181. if (uart_handle_sysrq_char(&sport->port, ch))
  182. goto ignore_char;
  183. uart_insert_char(&sport->port, status,
  184. ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN), ch, flg);
  185. ignore_char:
  186. serial_out(sport, PNX8XXX_LCR, serial_in(sport, PNX8XXX_LCR) |
  187. PNX8XXX_UART_LCR_RX_NEXT);
  188. status = FIFO_TO_SM(serial_in(sport, PNX8XXX_FIFO)) |
  189. ISTAT_TO_SM(serial_in(sport, PNX8XXX_ISTAT));
  190. }
  191. tty_flip_buffer_push(tty);
  192. }
  193. static void pnx8xxx_tx_chars(struct pnx8xxx_port *sport)
  194. {
  195. struct circ_buf *xmit = &sport->port.info->xmit;
  196. if (sport->port.x_char) {
  197. serial_out(sport, PNX8XXX_FIFO, sport->port.x_char);
  198. sport->port.icount.tx++;
  199. sport->port.x_char = 0;
  200. return;
  201. }
  202. /*
  203. * Check the modem control lines before
  204. * transmitting anything.
  205. */
  206. pnx8xxx_mctrl_check(sport);
  207. if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
  208. pnx8xxx_stop_tx(&sport->port);
  209. return;
  210. }
  211. /*
  212. * TX while bytes available
  213. */
  214. while (((serial_in(sport, PNX8XXX_FIFO) &
  215. PNX8XXX_UART_FIFO_TXFIFO) >> 16) < 16) {
  216. serial_out(sport, PNX8XXX_FIFO, xmit->buf[xmit->tail]);
  217. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  218. sport->port.icount.tx++;
  219. if (uart_circ_empty(xmit))
  220. break;
  221. }
  222. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  223. uart_write_wakeup(&sport->port);
  224. if (uart_circ_empty(xmit))
  225. pnx8xxx_stop_tx(&sport->port);
  226. }
  227. static irqreturn_t pnx8xxx_int(int irq, void *dev_id)
  228. {
  229. struct pnx8xxx_port *sport = dev_id;
  230. unsigned int status;
  231. spin_lock(&sport->port.lock);
  232. /* Get the interrupts */
  233. status = serial_in(sport, PNX8XXX_ISTAT) & serial_in(sport, PNX8XXX_IEN);
  234. /* Break signal received */
  235. if (status & PNX8XXX_UART_INT_BREAK) {
  236. sport->port.icount.brk++;
  237. uart_handle_break(&sport->port);
  238. }
  239. /* Byte received */
  240. if (status & PNX8XXX_UART_INT_RX)
  241. pnx8xxx_rx_chars(sport);
  242. /* TX holding register empty - transmit a byte */
  243. if (status & PNX8XXX_UART_INT_TX)
  244. pnx8xxx_tx_chars(sport);
  245. /* Clear the ISTAT register */
  246. serial_out(sport, PNX8XXX_ICLR, status);
  247. spin_unlock(&sport->port.lock);
  248. return IRQ_HANDLED;
  249. }
  250. /*
  251. * Return TIOCSER_TEMT when transmitter is not busy.
  252. */
  253. static unsigned int pnx8xxx_tx_empty(struct uart_port *port)
  254. {
  255. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  256. return serial_in(sport, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO_STA ? 0 : TIOCSER_TEMT;
  257. }
  258. static unsigned int pnx8xxx_get_mctrl(struct uart_port *port)
  259. {
  260. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  261. unsigned int mctrl = TIOCM_DSR;
  262. unsigned int msr;
  263. /* REVISIT */
  264. msr = serial_in(sport, PNX8XXX_MCR);
  265. mctrl |= msr & PNX8XXX_UART_MCR_CTS ? TIOCM_CTS : 0;
  266. mctrl |= msr & PNX8XXX_UART_MCR_DCD ? TIOCM_CAR : 0;
  267. return mctrl;
  268. }
  269. static void pnx8xxx_set_mctrl(struct uart_port *port, unsigned int mctrl)
  270. {
  271. #if 0 /* FIXME */
  272. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  273. unsigned int msr;
  274. #endif
  275. }
  276. /*
  277. * Interrupts always disabled.
  278. */
  279. static void pnx8xxx_break_ctl(struct uart_port *port, int break_state)
  280. {
  281. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  282. unsigned long flags;
  283. unsigned int lcr;
  284. spin_lock_irqsave(&sport->port.lock, flags);
  285. lcr = serial_in(sport, PNX8XXX_LCR);
  286. if (break_state == -1)
  287. lcr |= PNX8XXX_UART_LCR_TXBREAK;
  288. else
  289. lcr &= ~PNX8XXX_UART_LCR_TXBREAK;
  290. serial_out(sport, PNX8XXX_LCR, lcr);
  291. spin_unlock_irqrestore(&sport->port.lock, flags);
  292. }
  293. static int pnx8xxx_startup(struct uart_port *port)
  294. {
  295. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  296. int retval;
  297. /*
  298. * Allocate the IRQ
  299. */
  300. retval = request_irq(sport->port.irq, pnx8xxx_int, 0,
  301. "pnx8xxx-uart", sport);
  302. if (retval)
  303. return retval;
  304. /*
  305. * Finally, clear and enable interrupts
  306. */
  307. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX |
  308. PNX8XXX_UART_INT_ALLTX);
  309. serial_out(sport, PNX8XXX_IEN, serial_in(sport, PNX8XXX_IEN) |
  310. PNX8XXX_UART_INT_ALLRX |
  311. PNX8XXX_UART_INT_ALLTX);
  312. /*
  313. * Enable modem status interrupts
  314. */
  315. spin_lock_irq(&sport->port.lock);
  316. pnx8xxx_enable_ms(&sport->port);
  317. spin_unlock_irq(&sport->port.lock);
  318. return 0;
  319. }
  320. static void pnx8xxx_shutdown(struct uart_port *port)
  321. {
  322. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  323. int lcr;
  324. /*
  325. * Stop our timer.
  326. */
  327. del_timer_sync(&sport->timer);
  328. /*
  329. * Disable all interrupts
  330. */
  331. serial_out(sport, PNX8XXX_IEN, 0);
  332. /*
  333. * Reset the Tx and Rx FIFOS, disable the break condition
  334. */
  335. lcr = serial_in(sport, PNX8XXX_LCR);
  336. lcr &= ~PNX8XXX_UART_LCR_TXBREAK;
  337. lcr |= PNX8XXX_UART_LCR_TX_RST | PNX8XXX_UART_LCR_RX_RST;
  338. serial_out(sport, PNX8XXX_LCR, lcr);
  339. /*
  340. * Clear all interrupts
  341. */
  342. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_ALLRX |
  343. PNX8XXX_UART_INT_ALLTX);
  344. /*
  345. * Free the interrupt
  346. */
  347. free_irq(sport->port.irq, sport);
  348. }
  349. static void
  350. pnx8xxx_set_termios(struct uart_port *port, struct ktermios *termios,
  351. struct ktermios *old)
  352. {
  353. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  354. unsigned long flags;
  355. unsigned int lcr_fcr, old_ien, baud, quot;
  356. unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
  357. /*
  358. * We only support CS7 and CS8.
  359. */
  360. while ((termios->c_cflag & CSIZE) != CS7 &&
  361. (termios->c_cflag & CSIZE) != CS8) {
  362. termios->c_cflag &= ~CSIZE;
  363. termios->c_cflag |= old_csize;
  364. old_csize = CS8;
  365. }
  366. if ((termios->c_cflag & CSIZE) == CS8)
  367. lcr_fcr = PNX8XXX_UART_LCR_8BIT;
  368. else
  369. lcr_fcr = 0;
  370. if (termios->c_cflag & CSTOPB)
  371. lcr_fcr |= PNX8XXX_UART_LCR_2STOPB;
  372. if (termios->c_cflag & PARENB) {
  373. lcr_fcr |= PNX8XXX_UART_LCR_PAREN;
  374. if (!(termios->c_cflag & PARODD))
  375. lcr_fcr |= PNX8XXX_UART_LCR_PAREVN;
  376. }
  377. /*
  378. * Ask the core to calculate the divisor for us.
  379. */
  380. baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
  381. quot = uart_get_divisor(port, baud);
  382. spin_lock_irqsave(&sport->port.lock, flags);
  383. sport->port.read_status_mask = ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN) |
  384. ISTAT_TO_SM(PNX8XXX_UART_INT_EMPTY) |
  385. ISTAT_TO_SM(PNX8XXX_UART_INT_RX);
  386. if (termios->c_iflag & INPCK)
  387. sport->port.read_status_mask |=
  388. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
  389. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR);
  390. if (termios->c_iflag & (BRKINT | PARMRK))
  391. sport->port.read_status_mask |=
  392. ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK);
  393. /*
  394. * Characters to ignore
  395. */
  396. sport->port.ignore_status_mask = 0;
  397. if (termios->c_iflag & IGNPAR)
  398. sport->port.ignore_status_mask |=
  399. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXFE) |
  400. FIFO_TO_SM(PNX8XXX_UART_FIFO_RXPAR);
  401. if (termios->c_iflag & IGNBRK) {
  402. sport->port.ignore_status_mask |=
  403. ISTAT_TO_SM(PNX8XXX_UART_INT_BREAK);
  404. /*
  405. * If we're ignoring parity and break indicators,
  406. * ignore overruns too (for real raw support).
  407. */
  408. if (termios->c_iflag & IGNPAR)
  409. sport->port.ignore_status_mask |=
  410. ISTAT_TO_SM(PNX8XXX_UART_INT_RXOVRN);
  411. }
  412. /*
  413. * ignore all characters if CREAD is not set
  414. */
  415. if ((termios->c_cflag & CREAD) == 0)
  416. sport->port.ignore_status_mask |=
  417. ISTAT_TO_SM(PNX8XXX_UART_INT_RX);
  418. del_timer_sync(&sport->timer);
  419. /*
  420. * Update the per-port timeout.
  421. */
  422. uart_update_timeout(port, termios->c_cflag, baud);
  423. /*
  424. * disable interrupts and drain transmitter
  425. */
  426. old_ien = serial_in(sport, PNX8XXX_IEN);
  427. serial_out(sport, PNX8XXX_IEN, old_ien & ~(PNX8XXX_UART_INT_ALLTX |
  428. PNX8XXX_UART_INT_ALLRX));
  429. while (serial_in(sport, PNX8XXX_FIFO) & PNX8XXX_UART_FIFO_TXFIFO_STA)
  430. barrier();
  431. /* then, disable everything */
  432. serial_out(sport, PNX8XXX_IEN, 0);
  433. /* Reset the Rx and Tx FIFOs too */
  434. lcr_fcr |= PNX8XXX_UART_LCR_TX_RST;
  435. lcr_fcr |= PNX8XXX_UART_LCR_RX_RST;
  436. /* set the parity, stop bits and data size */
  437. serial_out(sport, PNX8XXX_LCR, lcr_fcr);
  438. /* set the baud rate */
  439. quot -= 1;
  440. serial_out(sport, PNX8XXX_BAUD, quot);
  441. serial_out(sport, PNX8XXX_ICLR, -1);
  442. serial_out(sport, PNX8XXX_IEN, old_ien);
  443. if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
  444. pnx8xxx_enable_ms(&sport->port);
  445. spin_unlock_irqrestore(&sport->port.lock, flags);
  446. }
  447. static const char *pnx8xxx_type(struct uart_port *port)
  448. {
  449. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  450. return sport->port.type == PORT_PNX8XXX ? "PNX8XXX" : NULL;
  451. }
  452. /*
  453. * Release the memory region(s) being used by 'port'.
  454. */
  455. static void pnx8xxx_release_port(struct uart_port *port)
  456. {
  457. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  458. release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
  459. }
  460. /*
  461. * Request the memory region(s) being used by 'port'.
  462. */
  463. static int pnx8xxx_request_port(struct uart_port *port)
  464. {
  465. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  466. return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
  467. "pnx8xxx-uart") != NULL ? 0 : -EBUSY;
  468. }
  469. /*
  470. * Configure/autoconfigure the port.
  471. */
  472. static void pnx8xxx_config_port(struct uart_port *port, int flags)
  473. {
  474. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  475. if (flags & UART_CONFIG_TYPE &&
  476. pnx8xxx_request_port(&sport->port) == 0)
  477. sport->port.type = PORT_PNX8XXX;
  478. }
  479. /*
  480. * Verify the new serial_struct (for TIOCSSERIAL).
  481. * The only change we allow are to the flags and type, and
  482. * even then only between PORT_PNX8XXX and PORT_UNKNOWN
  483. */
  484. static int
  485. pnx8xxx_verify_port(struct uart_port *port, struct serial_struct *ser)
  486. {
  487. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  488. int ret = 0;
  489. if (ser->type != PORT_UNKNOWN && ser->type != PORT_PNX8XXX)
  490. ret = -EINVAL;
  491. if (sport->port.irq != ser->irq)
  492. ret = -EINVAL;
  493. if (ser->io_type != SERIAL_IO_MEM)
  494. ret = -EINVAL;
  495. if (sport->port.uartclk / 16 != ser->baud_base)
  496. ret = -EINVAL;
  497. if ((void *)sport->port.mapbase != ser->iomem_base)
  498. ret = -EINVAL;
  499. if (sport->port.iobase != ser->port)
  500. ret = -EINVAL;
  501. if (ser->hub6 != 0)
  502. ret = -EINVAL;
  503. return ret;
  504. }
  505. static struct uart_ops pnx8xxx_pops = {
  506. .tx_empty = pnx8xxx_tx_empty,
  507. .set_mctrl = pnx8xxx_set_mctrl,
  508. .get_mctrl = pnx8xxx_get_mctrl,
  509. .stop_tx = pnx8xxx_stop_tx,
  510. .start_tx = pnx8xxx_start_tx,
  511. .stop_rx = pnx8xxx_stop_rx,
  512. .enable_ms = pnx8xxx_enable_ms,
  513. .break_ctl = pnx8xxx_break_ctl,
  514. .startup = pnx8xxx_startup,
  515. .shutdown = pnx8xxx_shutdown,
  516. .set_termios = pnx8xxx_set_termios,
  517. .type = pnx8xxx_type,
  518. .release_port = pnx8xxx_release_port,
  519. .request_port = pnx8xxx_request_port,
  520. .config_port = pnx8xxx_config_port,
  521. .verify_port = pnx8xxx_verify_port,
  522. };
  523. /*
  524. * Setup the PNX8XXX serial ports.
  525. *
  526. * Note also that we support "console=ttySx" where "x" is either 0 or 1.
  527. */
  528. static void __init pnx8xxx_init_ports(void)
  529. {
  530. static int first = 1;
  531. int i;
  532. if (!first)
  533. return;
  534. first = 0;
  535. for (i = 0; i < NR_PORTS; i++) {
  536. init_timer(&pnx8xxx_ports[i].timer);
  537. pnx8xxx_ports[i].timer.function = pnx8xxx_timeout;
  538. pnx8xxx_ports[i].timer.data = (unsigned long)&pnx8xxx_ports[i];
  539. pnx8xxx_ports[i].port.ops = &pnx8xxx_pops;
  540. }
  541. }
  542. #ifdef CONFIG_SERIAL_PNX8XXX_CONSOLE
  543. static void pnx8xxx_console_putchar(struct uart_port *port, int ch)
  544. {
  545. struct pnx8xxx_port *sport = (struct pnx8xxx_port *)port;
  546. int status;
  547. do {
  548. /* Wait for UART_TX register to empty */
  549. status = serial_in(sport, PNX8XXX_FIFO);
  550. } while (status & PNX8XXX_UART_FIFO_TXFIFO);
  551. serial_out(sport, PNX8XXX_FIFO, ch);
  552. }
  553. /*
  554. * Interrupts are disabled on entering
  555. */static void
  556. pnx8xxx_console_write(struct console *co, const char *s, unsigned int count)
  557. {
  558. struct pnx8xxx_port *sport = &pnx8xxx_ports[co->index];
  559. unsigned int old_ien, status;
  560. /*
  561. * First, save IEN and then disable interrupts
  562. */
  563. old_ien = serial_in(sport, PNX8XXX_IEN);
  564. serial_out(sport, PNX8XXX_IEN, old_ien & ~(PNX8XXX_UART_INT_ALLTX |
  565. PNX8XXX_UART_INT_ALLRX));
  566. uart_console_write(&sport->port, s, count, pnx8xxx_console_putchar);
  567. /*
  568. * Finally, wait for transmitter to become empty
  569. * and restore IEN
  570. */
  571. do {
  572. /* Wait for UART_TX register to empty */
  573. status = serial_in(sport, PNX8XXX_FIFO);
  574. } while (status & PNX8XXX_UART_FIFO_TXFIFO);
  575. /* Clear TX and EMPTY interrupt */
  576. serial_out(sport, PNX8XXX_ICLR, PNX8XXX_UART_INT_TX |
  577. PNX8XXX_UART_INT_EMPTY);
  578. serial_out(sport, PNX8XXX_IEN, old_ien);
  579. }
  580. static int __init
  581. pnx8xxx_console_setup(struct console *co, char *options)
  582. {
  583. struct pnx8xxx_port *sport;
  584. int baud = 38400;
  585. int bits = 8;
  586. int parity = 'n';
  587. int flow = 'n';
  588. /*
  589. * Check whether an invalid uart number has been specified, and
  590. * if so, search for the first available port that does have
  591. * console support.
  592. */
  593. if (co->index == -1 || co->index >= NR_PORTS)
  594. co->index = 0;
  595. sport = &pnx8xxx_ports[co->index];
  596. if (options)
  597. uart_parse_options(options, &baud, &parity, &bits, &flow);
  598. return uart_set_options(&sport->port, co, baud, parity, bits, flow);
  599. }
  600. static struct uart_driver pnx8xxx_reg;
  601. static struct console pnx8xxx_console = {
  602. .name = "ttyS",
  603. .write = pnx8xxx_console_write,
  604. .device = uart_console_device,
  605. .setup = pnx8xxx_console_setup,
  606. .flags = CON_PRINTBUFFER,
  607. .index = -1,
  608. .data = &pnx8xxx_reg,
  609. };
  610. static int __init pnx8xxx_rs_console_init(void)
  611. {
  612. pnx8xxx_init_ports();
  613. register_console(&pnx8xxx_console);
  614. return 0;
  615. }
  616. console_initcall(pnx8xxx_rs_console_init);
  617. #define PNX8XXX_CONSOLE &pnx8xxx_console
  618. #else
  619. #define PNX8XXX_CONSOLE NULL
  620. #endif
  621. static struct uart_driver pnx8xxx_reg = {
  622. .owner = THIS_MODULE,
  623. .driver_name = "ttyS",
  624. .dev_name = "ttyS",
  625. .major = SERIAL_PNX8XXX_MAJOR,
  626. .minor = MINOR_START,
  627. .nr = NR_PORTS,
  628. .cons = PNX8XXX_CONSOLE,
  629. };
  630. static int pnx8xxx_serial_suspend(struct platform_device *pdev, pm_message_t state)
  631. {
  632. struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
  633. return uart_suspend_port(&pnx8xxx_reg, &sport->port);
  634. }
  635. static int pnx8xxx_serial_resume(struct platform_device *pdev)
  636. {
  637. struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
  638. return uart_resume_port(&pnx8xxx_reg, &sport->port);
  639. }
  640. static int pnx8xxx_serial_probe(struct platform_device *pdev)
  641. {
  642. struct resource *res = pdev->resource;
  643. int i;
  644. for (i = 0; i < pdev->num_resources; i++, res++) {
  645. if (!(res->flags & IORESOURCE_MEM))
  646. continue;
  647. for (i = 0; i < NR_PORTS; i++) {
  648. if (pnx8xxx_ports[i].port.mapbase != res->start)
  649. continue;
  650. pnx8xxx_ports[i].port.dev = &pdev->dev;
  651. uart_add_one_port(&pnx8xxx_reg, &pnx8xxx_ports[i].port);
  652. platform_set_drvdata(pdev, &pnx8xxx_ports[i]);
  653. break;
  654. }
  655. }
  656. return 0;
  657. }
  658. static int pnx8xxx_serial_remove(struct platform_device *pdev)
  659. {
  660. struct pnx8xxx_port *sport = platform_get_drvdata(pdev);
  661. platform_set_drvdata(pdev, NULL);
  662. if (sport)
  663. uart_remove_one_port(&pnx8xxx_reg, &sport->port);
  664. return 0;
  665. }
  666. static struct platform_driver pnx8xxx_serial_driver = {
  667. .driver = {
  668. .name = "pnx8xxx-uart",
  669. .owner = THIS_MODULE,
  670. },
  671. .probe = pnx8xxx_serial_probe,
  672. .remove = pnx8xxx_serial_remove,
  673. .suspend = pnx8xxx_serial_suspend,
  674. .resume = pnx8xxx_serial_resume,
  675. };
  676. static int __init pnx8xxx_serial_init(void)
  677. {
  678. int ret;
  679. printk(KERN_INFO "Serial: PNX8XXX driver\n");
  680. pnx8xxx_init_ports();
  681. ret = uart_register_driver(&pnx8xxx_reg);
  682. if (ret == 0) {
  683. ret = platform_driver_register(&pnx8xxx_serial_driver);
  684. if (ret)
  685. uart_unregister_driver(&pnx8xxx_reg);
  686. }
  687. return ret;
  688. }
  689. static void __exit pnx8xxx_serial_exit(void)
  690. {
  691. platform_driver_unregister(&pnx8xxx_serial_driver);
  692. uart_unregister_driver(&pnx8xxx_reg);
  693. }
  694. module_init(pnx8xxx_serial_init);
  695. module_exit(pnx8xxx_serial_exit);
  696. MODULE_AUTHOR("Embedded Alley Solutions, Inc.");
  697. MODULE_DESCRIPTION("PNX8XXX SoCs serial port driver");
  698. MODULE_LICENSE("GPL");
  699. MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_PNX8XXX_MAJOR);
  700. MODULE_ALIAS("platform:pnx8xxx-uart");