aic94xx_sds.c 36 KB

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  1. /*
  2. * Aic94xx SAS/SATA driver access to shared data structures and memory
  3. * maps.
  4. *
  5. * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
  6. * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
  7. *
  8. * This file is licensed under GPLv2.
  9. *
  10. * This file is part of the aic94xx driver.
  11. *
  12. * The aic94xx driver is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; version 2 of the
  15. * License.
  16. *
  17. * The aic94xx driver is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  20. * General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with the aic94xx driver; if not, write to the Free Software
  24. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  25. *
  26. */
  27. #include <linux/pci.h>
  28. #include <linux/delay.h>
  29. #include "aic94xx.h"
  30. #include "aic94xx_reg.h"
  31. #include "aic94xx_sds.h"
  32. /* ---------- OCM stuff ---------- */
  33. struct asd_ocm_dir_ent {
  34. u8 type;
  35. u8 offs[3];
  36. u8 _r1;
  37. u8 size[3];
  38. } __attribute__ ((packed));
  39. struct asd_ocm_dir {
  40. char sig[2];
  41. u8 _r1[2];
  42. u8 major; /* 0 */
  43. u8 minor; /* 0 */
  44. u8 _r2;
  45. u8 num_de;
  46. struct asd_ocm_dir_ent entry[15];
  47. } __attribute__ ((packed));
  48. #define OCM_DE_OCM_DIR 0x00
  49. #define OCM_DE_WIN_DRVR 0x01
  50. #define OCM_DE_BIOS_CHIM 0x02
  51. #define OCM_DE_RAID_ENGN 0x03
  52. #define OCM_DE_BIOS_INTL 0x04
  53. #define OCM_DE_BIOS_CHIM_OSM 0x05
  54. #define OCM_DE_BIOS_CHIM_DYNAMIC 0x06
  55. #define OCM_DE_ADDC2C_RES0 0x07
  56. #define OCM_DE_ADDC2C_RES1 0x08
  57. #define OCM_DE_ADDC2C_RES2 0x09
  58. #define OCM_DE_ADDC2C_RES3 0x0A
  59. #define OCM_INIT_DIR_ENTRIES 5
  60. /***************************************************************************
  61. * OCM directory default
  62. ***************************************************************************/
  63. static struct asd_ocm_dir OCMDirInit =
  64. {
  65. .sig = {0x4D, 0x4F}, /* signature */
  66. .num_de = OCM_INIT_DIR_ENTRIES, /* no. of directory entries */
  67. };
  68. /***************************************************************************
  69. * OCM directory Entries default
  70. ***************************************************************************/
  71. static struct asd_ocm_dir_ent OCMDirEntriesInit[OCM_INIT_DIR_ENTRIES] =
  72. {
  73. {
  74. .type = (OCM_DE_ADDC2C_RES0), /* Entry type */
  75. .offs = {128}, /* Offset */
  76. .size = {0, 4}, /* size */
  77. },
  78. {
  79. .type = (OCM_DE_ADDC2C_RES1), /* Entry type */
  80. .offs = {128, 4}, /* Offset */
  81. .size = {0, 4}, /* size */
  82. },
  83. {
  84. .type = (OCM_DE_ADDC2C_RES2), /* Entry type */
  85. .offs = {128, 8}, /* Offset */
  86. .size = {0, 4}, /* size */
  87. },
  88. {
  89. .type = (OCM_DE_ADDC2C_RES3), /* Entry type */
  90. .offs = {128, 12}, /* Offset */
  91. .size = {0, 4}, /* size */
  92. },
  93. {
  94. .type = (OCM_DE_WIN_DRVR), /* Entry type */
  95. .offs = {128, 16}, /* Offset */
  96. .size = {128, 235, 1}, /* size */
  97. },
  98. };
  99. struct asd_bios_chim_struct {
  100. char sig[4];
  101. u8 major; /* 1 */
  102. u8 minor; /* 0 */
  103. u8 bios_major;
  104. u8 bios_minor;
  105. __le32 bios_build;
  106. u8 flags;
  107. u8 pci_slot;
  108. __le16 ue_num;
  109. __le16 ue_size;
  110. u8 _r[14];
  111. /* The unit element array is right here.
  112. */
  113. } __attribute__ ((packed));
  114. /**
  115. * asd_read_ocm_seg - read an on chip memory (OCM) segment
  116. * @asd_ha: pointer to the host adapter structure
  117. * @buffer: where to write the read data
  118. * @offs: offset into OCM where to read from
  119. * @size: how many bytes to read
  120. *
  121. * Return the number of bytes not read. Return 0 on success.
  122. */
  123. static int asd_read_ocm_seg(struct asd_ha_struct *asd_ha, void *buffer,
  124. u32 offs, int size)
  125. {
  126. u8 *p = buffer;
  127. if (unlikely(asd_ha->iospace))
  128. asd_read_reg_string(asd_ha, buffer, offs+OCM_BASE_ADDR, size);
  129. else {
  130. for ( ; size > 0; size--, offs++, p++)
  131. *p = asd_read_ocm_byte(asd_ha, offs);
  132. }
  133. return size;
  134. }
  135. static int asd_read_ocm_dir(struct asd_ha_struct *asd_ha,
  136. struct asd_ocm_dir *dir, u32 offs)
  137. {
  138. int err = asd_read_ocm_seg(asd_ha, dir, offs, sizeof(*dir));
  139. if (err) {
  140. ASD_DPRINTK("couldn't read ocm segment\n");
  141. return err;
  142. }
  143. if (dir->sig[0] != 'M' || dir->sig[1] != 'O') {
  144. ASD_DPRINTK("no valid dir signature(%c%c) at start of OCM\n",
  145. dir->sig[0], dir->sig[1]);
  146. return -ENOENT;
  147. }
  148. if (dir->major != 0) {
  149. asd_printk("unsupported major version of ocm dir:0x%x\n",
  150. dir->major);
  151. return -ENOENT;
  152. }
  153. dir->num_de &= 0xf;
  154. return 0;
  155. }
  156. /**
  157. * asd_write_ocm_seg - write an on chip memory (OCM) segment
  158. * @asd_ha: pointer to the host adapter structure
  159. * @buffer: where to read the write data
  160. * @offs: offset into OCM to write to
  161. * @size: how many bytes to write
  162. *
  163. * Return the number of bytes not written. Return 0 on success.
  164. */
  165. static void asd_write_ocm_seg(struct asd_ha_struct *asd_ha, void *buffer,
  166. u32 offs, int size)
  167. {
  168. u8 *p = buffer;
  169. if (unlikely(asd_ha->iospace))
  170. asd_write_reg_string(asd_ha, buffer, offs+OCM_BASE_ADDR, size);
  171. else {
  172. for ( ; size > 0; size--, offs++, p++)
  173. asd_write_ocm_byte(asd_ha, offs, *p);
  174. }
  175. return;
  176. }
  177. #define THREE_TO_NUM(X) ((X)[0] | ((X)[1] << 8) | ((X)[2] << 16))
  178. static int asd_find_dir_entry(struct asd_ocm_dir *dir, u8 type,
  179. u32 *offs, u32 *size)
  180. {
  181. int i;
  182. struct asd_ocm_dir_ent *ent;
  183. for (i = 0; i < dir->num_de; i++) {
  184. if (dir->entry[i].type == type)
  185. break;
  186. }
  187. if (i >= dir->num_de)
  188. return -ENOENT;
  189. ent = &dir->entry[i];
  190. *offs = (u32) THREE_TO_NUM(ent->offs);
  191. *size = (u32) THREE_TO_NUM(ent->size);
  192. return 0;
  193. }
  194. #define OCM_BIOS_CHIM_DE 2
  195. #define BC_BIOS_PRESENT 1
  196. static int asd_get_bios_chim(struct asd_ha_struct *asd_ha,
  197. struct asd_ocm_dir *dir)
  198. {
  199. int err;
  200. struct asd_bios_chim_struct *bc_struct;
  201. u32 offs, size;
  202. err = asd_find_dir_entry(dir, OCM_BIOS_CHIM_DE, &offs, &size);
  203. if (err) {
  204. ASD_DPRINTK("couldn't find BIOS_CHIM dir ent\n");
  205. goto out;
  206. }
  207. err = -ENOMEM;
  208. bc_struct = kmalloc(sizeof(*bc_struct), GFP_KERNEL);
  209. if (!bc_struct) {
  210. asd_printk("no memory for bios_chim struct\n");
  211. goto out;
  212. }
  213. err = asd_read_ocm_seg(asd_ha, (void *)bc_struct, offs,
  214. sizeof(*bc_struct));
  215. if (err) {
  216. ASD_DPRINTK("couldn't read ocm segment\n");
  217. goto out2;
  218. }
  219. if (strncmp(bc_struct->sig, "SOIB", 4)
  220. && strncmp(bc_struct->sig, "IPSA", 4)) {
  221. ASD_DPRINTK("BIOS_CHIM entry has no valid sig(%c%c%c%c)\n",
  222. bc_struct->sig[0], bc_struct->sig[1],
  223. bc_struct->sig[2], bc_struct->sig[3]);
  224. err = -ENOENT;
  225. goto out2;
  226. }
  227. if (bc_struct->major != 1) {
  228. asd_printk("BIOS_CHIM unsupported major version:0x%x\n",
  229. bc_struct->major);
  230. err = -ENOENT;
  231. goto out2;
  232. }
  233. if (bc_struct->flags & BC_BIOS_PRESENT) {
  234. asd_ha->hw_prof.bios.present = 1;
  235. asd_ha->hw_prof.bios.maj = bc_struct->bios_major;
  236. asd_ha->hw_prof.bios.min = bc_struct->bios_minor;
  237. asd_ha->hw_prof.bios.bld = le32_to_cpu(bc_struct->bios_build);
  238. ASD_DPRINTK("BIOS present (%d,%d), %d\n",
  239. asd_ha->hw_prof.bios.maj,
  240. asd_ha->hw_prof.bios.min,
  241. asd_ha->hw_prof.bios.bld);
  242. }
  243. asd_ha->hw_prof.ue.num = le16_to_cpu(bc_struct->ue_num);
  244. asd_ha->hw_prof.ue.size= le16_to_cpu(bc_struct->ue_size);
  245. ASD_DPRINTK("ue num:%d, ue size:%d\n", asd_ha->hw_prof.ue.num,
  246. asd_ha->hw_prof.ue.size);
  247. size = asd_ha->hw_prof.ue.num * asd_ha->hw_prof.ue.size;
  248. if (size > 0) {
  249. err = -ENOMEM;
  250. asd_ha->hw_prof.ue.area = kmalloc(size, GFP_KERNEL);
  251. if (!asd_ha->hw_prof.ue.area)
  252. goto out2;
  253. err = asd_read_ocm_seg(asd_ha, (void *)asd_ha->hw_prof.ue.area,
  254. offs + sizeof(*bc_struct), size);
  255. if (err) {
  256. kfree(asd_ha->hw_prof.ue.area);
  257. asd_ha->hw_prof.ue.area = NULL;
  258. asd_ha->hw_prof.ue.num = 0;
  259. asd_ha->hw_prof.ue.size = 0;
  260. ASD_DPRINTK("couldn't read ue entries(%d)\n", err);
  261. }
  262. }
  263. out2:
  264. kfree(bc_struct);
  265. out:
  266. return err;
  267. }
  268. static void
  269. asd_hwi_initialize_ocm_dir (struct asd_ha_struct *asd_ha)
  270. {
  271. int i;
  272. /* Zero OCM */
  273. for (i = 0; i < OCM_MAX_SIZE; i += 4)
  274. asd_write_ocm_dword(asd_ha, i, 0);
  275. /* Write Dir */
  276. asd_write_ocm_seg(asd_ha, &OCMDirInit, 0,
  277. sizeof(struct asd_ocm_dir));
  278. /* Write Dir Entries */
  279. for (i = 0; i < OCM_INIT_DIR_ENTRIES; i++)
  280. asd_write_ocm_seg(asd_ha, &OCMDirEntriesInit[i],
  281. sizeof(struct asd_ocm_dir) +
  282. (i * sizeof(struct asd_ocm_dir_ent))
  283. , sizeof(struct asd_ocm_dir_ent));
  284. }
  285. static int
  286. asd_hwi_check_ocm_access (struct asd_ha_struct *asd_ha)
  287. {
  288. struct pci_dev *pcidev = asd_ha->pcidev;
  289. u32 reg;
  290. int err = 0;
  291. u32 v;
  292. /* check if OCM has been initialized by BIOS */
  293. reg = asd_read_reg_dword(asd_ha, EXSICNFGR);
  294. if (!(reg & OCMINITIALIZED)) {
  295. err = pci_read_config_dword(pcidev, PCIC_INTRPT_STAT, &v);
  296. if (err) {
  297. asd_printk("couldn't access PCIC_INTRPT_STAT of %s\n",
  298. pci_name(pcidev));
  299. goto out;
  300. }
  301. printk(KERN_INFO "OCM is not initialized by BIOS,"
  302. "reinitialize it and ignore it, current IntrptStatus"
  303. "is 0x%x\n", v);
  304. if (v)
  305. err = pci_write_config_dword(pcidev,
  306. PCIC_INTRPT_STAT, v);
  307. if (err) {
  308. asd_printk("couldn't write PCIC_INTRPT_STAT of %s\n",
  309. pci_name(pcidev));
  310. goto out;
  311. }
  312. asd_hwi_initialize_ocm_dir(asd_ha);
  313. }
  314. out:
  315. return err;
  316. }
  317. /**
  318. * asd_read_ocm - read on chip memory (OCM)
  319. * @asd_ha: pointer to the host adapter structure
  320. */
  321. int asd_read_ocm(struct asd_ha_struct *asd_ha)
  322. {
  323. int err;
  324. struct asd_ocm_dir *dir;
  325. if (asd_hwi_check_ocm_access(asd_ha))
  326. return -1;
  327. dir = kmalloc(sizeof(*dir), GFP_KERNEL);
  328. if (!dir) {
  329. asd_printk("no memory for ocm dir\n");
  330. return -ENOMEM;
  331. }
  332. err = asd_read_ocm_dir(asd_ha, dir, 0);
  333. if (err)
  334. goto out;
  335. err = asd_get_bios_chim(asd_ha, dir);
  336. out:
  337. kfree(dir);
  338. return err;
  339. }
  340. /* ---------- FLASH stuff ---------- */
  341. #define FLASH_RESET 0xF0
  342. #define ASD_FLASH_SIZE 0x200000
  343. #define FLASH_DIR_COOKIE "*** ADAPTEC FLASH DIRECTORY *** "
  344. #define FLASH_NEXT_ENTRY_OFFS 0x2000
  345. #define FLASH_MAX_DIR_ENTRIES 32
  346. #define FLASH_DE_TYPE_MASK 0x3FFFFFFF
  347. #define FLASH_DE_MS 0x120
  348. #define FLASH_DE_CTRL_A_USER 0xE0
  349. struct asd_flash_de {
  350. __le32 type;
  351. __le32 offs;
  352. __le32 pad_size;
  353. __le32 image_size;
  354. __le32 chksum;
  355. u8 _r[12];
  356. u8 version[32];
  357. } __attribute__ ((packed));
  358. struct asd_flash_dir {
  359. u8 cookie[32];
  360. __le32 rev; /* 2 */
  361. __le32 chksum;
  362. __le32 chksum_antidote;
  363. __le32 bld;
  364. u8 bld_id[32]; /* build id data */
  365. u8 ver_data[32]; /* date and time of build */
  366. __le32 ae_mask;
  367. __le32 v_mask;
  368. __le32 oc_mask;
  369. u8 _r[20];
  370. struct asd_flash_de dir_entry[FLASH_MAX_DIR_ENTRIES];
  371. } __attribute__ ((packed));
  372. struct asd_manuf_sec {
  373. char sig[2]; /* 'S', 'M' */
  374. u16 offs_next;
  375. u8 maj; /* 0 */
  376. u8 min; /* 0 */
  377. u16 chksum;
  378. u16 size;
  379. u8 _r[6];
  380. u8 sas_addr[SAS_ADDR_SIZE];
  381. u8 pcba_sn[ASD_PCBA_SN_SIZE];
  382. /* Here start the other segments */
  383. u8 linked_list[0];
  384. } __attribute__ ((packed));
  385. struct asd_manuf_phy_desc {
  386. u8 state; /* low 4 bits */
  387. #define MS_PHY_STATE_ENABLED 0
  388. #define MS_PHY_STATE_REPORTED 1
  389. #define MS_PHY_STATE_HIDDEN 2
  390. u8 phy_id;
  391. u16 _r;
  392. u8 phy_control_0; /* mode 5 reg 0x160 */
  393. u8 phy_control_1; /* mode 5 reg 0x161 */
  394. u8 phy_control_2; /* mode 5 reg 0x162 */
  395. u8 phy_control_3; /* mode 5 reg 0x163 */
  396. } __attribute__ ((packed));
  397. struct asd_manuf_phy_param {
  398. char sig[2]; /* 'P', 'M' */
  399. u16 next;
  400. u8 maj; /* 0 */
  401. u8 min; /* 2 */
  402. u8 num_phy_desc; /* 8 */
  403. u8 phy_desc_size; /* 8 */
  404. u8 _r[3];
  405. u8 usage_model_id;
  406. u32 _r2;
  407. struct asd_manuf_phy_desc phy_desc[ASD_MAX_PHYS];
  408. } __attribute__ ((packed));
  409. #if 0
  410. static const char *asd_sb_type[] = {
  411. "unknown",
  412. "SGPIO",
  413. [2 ... 0x7F] = "unknown",
  414. [0x80] = "ADPT_I2C",
  415. [0x81 ... 0xFF] = "VENDOR_UNIQUExx"
  416. };
  417. #endif
  418. struct asd_ms_sb_desc {
  419. u8 type;
  420. u8 node_desc_index;
  421. u8 conn_desc_index;
  422. u8 _recvd[0];
  423. } __attribute__ ((packed));
  424. #if 0
  425. static const char *asd_conn_type[] = {
  426. [0 ... 7] = "unknown",
  427. "SFF8470",
  428. "SFF8482",
  429. "SFF8484",
  430. [0x80] = "PCIX_DAUGHTER0",
  431. [0x81] = "SAS_DAUGHTER0",
  432. [0x82 ... 0xFF] = "VENDOR_UNIQUExx"
  433. };
  434. static const char *asd_conn_location[] = {
  435. "unknown",
  436. "internal",
  437. "external",
  438. "board_to_board",
  439. };
  440. #endif
  441. struct asd_ms_conn_desc {
  442. u8 type;
  443. u8 location;
  444. u8 num_sideband_desc;
  445. u8 size_sideband_desc;
  446. u32 _resvd;
  447. u8 name[16];
  448. struct asd_ms_sb_desc sb_desc[0];
  449. } __attribute__ ((packed));
  450. struct asd_nd_phy_desc {
  451. u8 vp_attch_type;
  452. u8 attch_specific[0];
  453. } __attribute__ ((packed));
  454. #if 0
  455. static const char *asd_node_type[] = {
  456. "IOP",
  457. "IO_CONTROLLER",
  458. "EXPANDER",
  459. "PORT_MULTIPLIER",
  460. "PORT_MULTIPLEXER",
  461. "MULTI_DROP_I2C_BUS",
  462. };
  463. #endif
  464. struct asd_ms_node_desc {
  465. u8 type;
  466. u8 num_phy_desc;
  467. u8 size_phy_desc;
  468. u8 _resvd;
  469. u8 name[16];
  470. struct asd_nd_phy_desc phy_desc[0];
  471. } __attribute__ ((packed));
  472. struct asd_ms_conn_map {
  473. char sig[2]; /* 'M', 'C' */
  474. __le16 next;
  475. u8 maj; /* 0 */
  476. u8 min; /* 0 */
  477. __le16 cm_size; /* size of this struct */
  478. u8 num_conn;
  479. u8 conn_size;
  480. u8 num_nodes;
  481. u8 usage_model_id;
  482. u32 _resvd;
  483. struct asd_ms_conn_desc conn_desc[0];
  484. struct asd_ms_node_desc node_desc[0];
  485. } __attribute__ ((packed));
  486. struct asd_ctrla_phy_entry {
  487. u8 sas_addr[SAS_ADDR_SIZE];
  488. u8 sas_link_rates; /* max in hi bits, min in low bits */
  489. u8 flags;
  490. u8 sata_link_rates;
  491. u8 _r[5];
  492. } __attribute__ ((packed));
  493. struct asd_ctrla_phy_settings {
  494. u8 id0; /* P'h'y */
  495. u8 _r;
  496. u16 next;
  497. u8 num_phys; /* number of PHYs in the PCI function */
  498. u8 _r2[3];
  499. struct asd_ctrla_phy_entry phy_ent[ASD_MAX_PHYS];
  500. } __attribute__ ((packed));
  501. struct asd_ll_el {
  502. u8 id0;
  503. u8 id1;
  504. __le16 next;
  505. u8 something_here[0];
  506. } __attribute__ ((packed));
  507. static int asd_poll_flash(struct asd_ha_struct *asd_ha)
  508. {
  509. int c;
  510. u8 d;
  511. for (c = 5000; c > 0; c--) {
  512. d = asd_read_reg_byte(asd_ha, asd_ha->hw_prof.flash.bar);
  513. d ^= asd_read_reg_byte(asd_ha, asd_ha->hw_prof.flash.bar);
  514. if (!d)
  515. return 0;
  516. udelay(5);
  517. }
  518. return -ENOENT;
  519. }
  520. static int asd_reset_flash(struct asd_ha_struct *asd_ha)
  521. {
  522. int err;
  523. err = asd_poll_flash(asd_ha);
  524. if (err)
  525. return err;
  526. asd_write_reg_byte(asd_ha, asd_ha->hw_prof.flash.bar, FLASH_RESET);
  527. err = asd_poll_flash(asd_ha);
  528. return err;
  529. }
  530. static int asd_read_flash_seg(struct asd_ha_struct *asd_ha,
  531. void *buffer, u32 offs, int size)
  532. {
  533. asd_read_reg_string(asd_ha, buffer, asd_ha->hw_prof.flash.bar+offs,
  534. size);
  535. return 0;
  536. }
  537. /**
  538. * asd_find_flash_dir - finds and reads the flash directory
  539. * @asd_ha: pointer to the host adapter structure
  540. * @flash_dir: pointer to flash directory structure
  541. *
  542. * If found, the flash directory segment will be copied to
  543. * @flash_dir. Return 1 if found, 0 if not.
  544. */
  545. static int asd_find_flash_dir(struct asd_ha_struct *asd_ha,
  546. struct asd_flash_dir *flash_dir)
  547. {
  548. u32 v;
  549. for (v = 0; v < ASD_FLASH_SIZE; v += FLASH_NEXT_ENTRY_OFFS) {
  550. asd_read_flash_seg(asd_ha, flash_dir, v,
  551. sizeof(FLASH_DIR_COOKIE)-1);
  552. if (memcmp(flash_dir->cookie, FLASH_DIR_COOKIE,
  553. sizeof(FLASH_DIR_COOKIE)-1) == 0) {
  554. asd_ha->hw_prof.flash.dir_offs = v;
  555. asd_read_flash_seg(asd_ha, flash_dir, v,
  556. sizeof(*flash_dir));
  557. return 1;
  558. }
  559. }
  560. return 0;
  561. }
  562. static int asd_flash_getid(struct asd_ha_struct *asd_ha)
  563. {
  564. int err = 0;
  565. u32 reg;
  566. reg = asd_read_reg_dword(asd_ha, EXSICNFGR);
  567. if (pci_read_config_dword(asd_ha->pcidev, PCI_CONF_FLSH_BAR,
  568. &asd_ha->hw_prof.flash.bar)) {
  569. asd_printk("couldn't read PCI_CONF_FLSH_BAR of %s\n",
  570. pci_name(asd_ha->pcidev));
  571. return -ENOENT;
  572. }
  573. asd_ha->hw_prof.flash.present = 1;
  574. asd_ha->hw_prof.flash.wide = reg & FLASHW ? 1 : 0;
  575. err = asd_reset_flash(asd_ha);
  576. if (err) {
  577. ASD_DPRINTK("couldn't reset flash(%d)\n", err);
  578. return err;
  579. }
  580. return 0;
  581. }
  582. static u16 asd_calc_flash_chksum(u16 *p, int size)
  583. {
  584. u16 chksum = 0;
  585. while (size-- > 0)
  586. chksum += *p++;
  587. return chksum;
  588. }
  589. static int asd_find_flash_de(struct asd_flash_dir *flash_dir, u32 entry_type,
  590. u32 *offs, u32 *size)
  591. {
  592. int i;
  593. struct asd_flash_de *de;
  594. for (i = 0; i < FLASH_MAX_DIR_ENTRIES; i++) {
  595. u32 type = le32_to_cpu(flash_dir->dir_entry[i].type);
  596. type &= FLASH_DE_TYPE_MASK;
  597. if (type == entry_type)
  598. break;
  599. }
  600. if (i >= FLASH_MAX_DIR_ENTRIES)
  601. return -ENOENT;
  602. de = &flash_dir->dir_entry[i];
  603. *offs = le32_to_cpu(de->offs);
  604. *size = le32_to_cpu(de->pad_size);
  605. return 0;
  606. }
  607. static int asd_validate_ms(struct asd_manuf_sec *ms)
  608. {
  609. if (ms->sig[0] != 'S' || ms->sig[1] != 'M') {
  610. ASD_DPRINTK("manuf sec: no valid sig(%c%c)\n",
  611. ms->sig[0], ms->sig[1]);
  612. return -ENOENT;
  613. }
  614. if (ms->maj != 0) {
  615. asd_printk("unsupported manuf. sector. major version:%x\n",
  616. ms->maj);
  617. return -ENOENT;
  618. }
  619. ms->offs_next = le16_to_cpu((__force __le16) ms->offs_next);
  620. ms->chksum = le16_to_cpu((__force __le16) ms->chksum);
  621. ms->size = le16_to_cpu((__force __le16) ms->size);
  622. if (asd_calc_flash_chksum((u16 *)ms, ms->size/2)) {
  623. asd_printk("failed manuf sector checksum\n");
  624. }
  625. return 0;
  626. }
  627. static int asd_ms_get_sas_addr(struct asd_ha_struct *asd_ha,
  628. struct asd_manuf_sec *ms)
  629. {
  630. memcpy(asd_ha->hw_prof.sas_addr, ms->sas_addr, SAS_ADDR_SIZE);
  631. return 0;
  632. }
  633. static int asd_ms_get_pcba_sn(struct asd_ha_struct *asd_ha,
  634. struct asd_manuf_sec *ms)
  635. {
  636. memcpy(asd_ha->hw_prof.pcba_sn, ms->pcba_sn, ASD_PCBA_SN_SIZE);
  637. asd_ha->hw_prof.pcba_sn[ASD_PCBA_SN_SIZE] = '\0';
  638. return 0;
  639. }
  640. /**
  641. * asd_find_ll_by_id - find a linked list entry by its id
  642. * @start: void pointer to the first element in the linked list
  643. * @id0: the first byte of the id (offs 0)
  644. * @id1: the second byte of the id (offs 1)
  645. *
  646. * @start has to be the _base_ element start, since the
  647. * linked list entries's offset is from this pointer.
  648. * Some linked list entries use only the first id, in which case
  649. * you can pass 0xFF for the second.
  650. */
  651. static void *asd_find_ll_by_id(void * const start, const u8 id0, const u8 id1)
  652. {
  653. struct asd_ll_el *el = start;
  654. do {
  655. switch (id1) {
  656. default:
  657. if (el->id1 == id1)
  658. case 0xFF:
  659. if (el->id0 == id0)
  660. return el;
  661. }
  662. el = start + le16_to_cpu(el->next);
  663. } while (el != start);
  664. return NULL;
  665. }
  666. /**
  667. * asd_ms_get_phy_params - get phy parameters from the manufacturing sector
  668. * @asd_ha: pointer to the host adapter structure
  669. * @manuf_sec: pointer to the manufacturing sector
  670. *
  671. * The manufacturing sector contans also the linked list of sub-segments,
  672. * since when it was read, its size was taken from the flash directory,
  673. * not from the structure size.
  674. *
  675. * HIDDEN phys do not count in the total count. REPORTED phys cannot
  676. * be enabled but are reported and counted towards the total.
  677. * ENABLED phys are enabled by default and count towards the total.
  678. * The absolute total phy number is ASD_MAX_PHYS. hw_prof->num_phys
  679. * merely specifies the number of phys the host adapter decided to
  680. * report. E.g., it is possible for phys 0, 1 and 2 to be HIDDEN,
  681. * phys 3, 4 and 5 to be REPORTED and phys 6 and 7 to be ENABLED.
  682. * In this case ASD_MAX_PHYS is 8, hw_prof->num_phys is 5, and only 2
  683. * are actually enabled (enabled by default, max number of phys
  684. * enableable in this case).
  685. */
  686. static int asd_ms_get_phy_params(struct asd_ha_struct *asd_ha,
  687. struct asd_manuf_sec *manuf_sec)
  688. {
  689. int i;
  690. int en_phys = 0;
  691. int rep_phys = 0;
  692. struct asd_manuf_phy_param *phy_param;
  693. struct asd_manuf_phy_param dflt_phy_param;
  694. phy_param = asd_find_ll_by_id(manuf_sec, 'P', 'M');
  695. if (!phy_param) {
  696. ASD_DPRINTK("ms: no phy parameters found\n");
  697. ASD_DPRINTK("ms: Creating default phy parameters\n");
  698. dflt_phy_param.sig[0] = 'P';
  699. dflt_phy_param.sig[1] = 'M';
  700. dflt_phy_param.maj = 0;
  701. dflt_phy_param.min = 2;
  702. dflt_phy_param.num_phy_desc = 8;
  703. dflt_phy_param.phy_desc_size = sizeof(struct asd_manuf_phy_desc);
  704. for (i =0; i < ASD_MAX_PHYS; i++) {
  705. dflt_phy_param.phy_desc[i].state = 0;
  706. dflt_phy_param.phy_desc[i].phy_id = i;
  707. dflt_phy_param.phy_desc[i].phy_control_0 = 0xf6;
  708. dflt_phy_param.phy_desc[i].phy_control_1 = 0x10;
  709. dflt_phy_param.phy_desc[i].phy_control_2 = 0x43;
  710. dflt_phy_param.phy_desc[i].phy_control_3 = 0xeb;
  711. }
  712. phy_param = &dflt_phy_param;
  713. }
  714. if (phy_param->maj != 0) {
  715. asd_printk("unsupported manuf. phy param major version:0x%x\n",
  716. phy_param->maj);
  717. return -ENOENT;
  718. }
  719. ASD_DPRINTK("ms: num_phy_desc: %d\n", phy_param->num_phy_desc);
  720. asd_ha->hw_prof.enabled_phys = 0;
  721. for (i = 0; i < phy_param->num_phy_desc; i++) {
  722. struct asd_manuf_phy_desc *pd = &phy_param->phy_desc[i];
  723. switch (pd->state & 0xF) {
  724. case MS_PHY_STATE_HIDDEN:
  725. ASD_DPRINTK("ms: phy%d: HIDDEN\n", i);
  726. continue;
  727. case MS_PHY_STATE_REPORTED:
  728. ASD_DPRINTK("ms: phy%d: REPORTED\n", i);
  729. asd_ha->hw_prof.enabled_phys &= ~(1 << i);
  730. rep_phys++;
  731. continue;
  732. case MS_PHY_STATE_ENABLED:
  733. ASD_DPRINTK("ms: phy%d: ENABLED\n", i);
  734. asd_ha->hw_prof.enabled_phys |= (1 << i);
  735. en_phys++;
  736. break;
  737. }
  738. asd_ha->hw_prof.phy_desc[i].phy_control_0 = pd->phy_control_0;
  739. asd_ha->hw_prof.phy_desc[i].phy_control_1 = pd->phy_control_1;
  740. asd_ha->hw_prof.phy_desc[i].phy_control_2 = pd->phy_control_2;
  741. asd_ha->hw_prof.phy_desc[i].phy_control_3 = pd->phy_control_3;
  742. }
  743. asd_ha->hw_prof.max_phys = rep_phys + en_phys;
  744. asd_ha->hw_prof.num_phys = en_phys;
  745. ASD_DPRINTK("ms: max_phys:0x%x, num_phys:0x%x\n",
  746. asd_ha->hw_prof.max_phys, asd_ha->hw_prof.num_phys);
  747. ASD_DPRINTK("ms: enabled_phys:0x%x\n", asd_ha->hw_prof.enabled_phys);
  748. return 0;
  749. }
  750. static int asd_ms_get_connector_map(struct asd_ha_struct *asd_ha,
  751. struct asd_manuf_sec *manuf_sec)
  752. {
  753. struct asd_ms_conn_map *cm;
  754. cm = asd_find_ll_by_id(manuf_sec, 'M', 'C');
  755. if (!cm) {
  756. ASD_DPRINTK("ms: no connector map found\n");
  757. return 0;
  758. }
  759. if (cm->maj != 0) {
  760. ASD_DPRINTK("ms: unsupported: connector map major version 0x%x"
  761. "\n", cm->maj);
  762. return -ENOENT;
  763. }
  764. /* XXX */
  765. return 0;
  766. }
  767. /**
  768. * asd_process_ms - find and extract information from the manufacturing sector
  769. * @asd_ha: pointer to the host adapter structure
  770. * @flash_dir: pointer to the flash directory
  771. */
  772. static int asd_process_ms(struct asd_ha_struct *asd_ha,
  773. struct asd_flash_dir *flash_dir)
  774. {
  775. int err;
  776. struct asd_manuf_sec *manuf_sec;
  777. u32 offs, size;
  778. err = asd_find_flash_de(flash_dir, FLASH_DE_MS, &offs, &size);
  779. if (err) {
  780. ASD_DPRINTK("Couldn't find the manuf. sector\n");
  781. goto out;
  782. }
  783. if (size == 0)
  784. goto out;
  785. err = -ENOMEM;
  786. manuf_sec = kmalloc(size, GFP_KERNEL);
  787. if (!manuf_sec) {
  788. ASD_DPRINTK("no mem for manuf sector\n");
  789. goto out;
  790. }
  791. err = asd_read_flash_seg(asd_ha, (void *)manuf_sec, offs, size);
  792. if (err) {
  793. ASD_DPRINTK("couldn't read manuf sector at 0x%x, size 0x%x\n",
  794. offs, size);
  795. goto out2;
  796. }
  797. err = asd_validate_ms(manuf_sec);
  798. if (err) {
  799. ASD_DPRINTK("couldn't validate manuf sector\n");
  800. goto out2;
  801. }
  802. err = asd_ms_get_sas_addr(asd_ha, manuf_sec);
  803. if (err) {
  804. ASD_DPRINTK("couldn't read the SAS_ADDR\n");
  805. goto out2;
  806. }
  807. ASD_DPRINTK("manuf sect SAS_ADDR %llx\n",
  808. SAS_ADDR(asd_ha->hw_prof.sas_addr));
  809. err = asd_ms_get_pcba_sn(asd_ha, manuf_sec);
  810. if (err) {
  811. ASD_DPRINTK("couldn't read the PCBA SN\n");
  812. goto out2;
  813. }
  814. ASD_DPRINTK("manuf sect PCBA SN %s\n", asd_ha->hw_prof.pcba_sn);
  815. err = asd_ms_get_phy_params(asd_ha, manuf_sec);
  816. if (err) {
  817. ASD_DPRINTK("ms: couldn't get phy parameters\n");
  818. goto out2;
  819. }
  820. err = asd_ms_get_connector_map(asd_ha, manuf_sec);
  821. if (err) {
  822. ASD_DPRINTK("ms: couldn't get connector map\n");
  823. goto out2;
  824. }
  825. out2:
  826. kfree(manuf_sec);
  827. out:
  828. return err;
  829. }
  830. static int asd_process_ctrla_phy_settings(struct asd_ha_struct *asd_ha,
  831. struct asd_ctrla_phy_settings *ps)
  832. {
  833. int i;
  834. for (i = 0; i < ps->num_phys; i++) {
  835. struct asd_ctrla_phy_entry *pe = &ps->phy_ent[i];
  836. if (!PHY_ENABLED(asd_ha, i))
  837. continue;
  838. if (*(u64 *)pe->sas_addr == 0) {
  839. asd_ha->hw_prof.enabled_phys &= ~(1 << i);
  840. continue;
  841. }
  842. /* This is the SAS address which should be sent in IDENTIFY. */
  843. memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr, pe->sas_addr,
  844. SAS_ADDR_SIZE);
  845. asd_ha->hw_prof.phy_desc[i].max_sas_lrate =
  846. (pe->sas_link_rates & 0xF0) >> 4;
  847. asd_ha->hw_prof.phy_desc[i].min_sas_lrate =
  848. (pe->sas_link_rates & 0x0F);
  849. asd_ha->hw_prof.phy_desc[i].max_sata_lrate =
  850. (pe->sata_link_rates & 0xF0) >> 4;
  851. asd_ha->hw_prof.phy_desc[i].min_sata_lrate =
  852. (pe->sata_link_rates & 0x0F);
  853. asd_ha->hw_prof.phy_desc[i].flags = pe->flags;
  854. ASD_DPRINTK("ctrla: phy%d: sas_addr: %llx, sas rate:0x%x-0x%x,"
  855. " sata rate:0x%x-0x%x, flags:0x%x\n",
  856. i,
  857. SAS_ADDR(asd_ha->hw_prof.phy_desc[i].sas_addr),
  858. asd_ha->hw_prof.phy_desc[i].max_sas_lrate,
  859. asd_ha->hw_prof.phy_desc[i].min_sas_lrate,
  860. asd_ha->hw_prof.phy_desc[i].max_sata_lrate,
  861. asd_ha->hw_prof.phy_desc[i].min_sata_lrate,
  862. asd_ha->hw_prof.phy_desc[i].flags);
  863. }
  864. return 0;
  865. }
  866. /**
  867. * asd_process_ctrl_a_user - process CTRL-A user settings
  868. * @asd_ha: pointer to the host adapter structure
  869. * @flash_dir: pointer to the flash directory
  870. */
  871. static int asd_process_ctrl_a_user(struct asd_ha_struct *asd_ha,
  872. struct asd_flash_dir *flash_dir)
  873. {
  874. int err, i;
  875. u32 offs, size;
  876. struct asd_ll_el *el;
  877. struct asd_ctrla_phy_settings *ps;
  878. struct asd_ctrla_phy_settings dflt_ps;
  879. err = asd_find_flash_de(flash_dir, FLASH_DE_CTRL_A_USER, &offs, &size);
  880. if (err) {
  881. ASD_DPRINTK("couldn't find CTRL-A user settings section\n");
  882. ASD_DPRINTK("Creating default CTRL-A user settings section\n");
  883. dflt_ps.id0 = 'h';
  884. dflt_ps.num_phys = 8;
  885. for (i =0; i < ASD_MAX_PHYS; i++) {
  886. memcpy(dflt_ps.phy_ent[i].sas_addr,
  887. asd_ha->hw_prof.sas_addr, SAS_ADDR_SIZE);
  888. dflt_ps.phy_ent[i].sas_link_rates = 0x98;
  889. dflt_ps.phy_ent[i].flags = 0x0;
  890. dflt_ps.phy_ent[i].sata_link_rates = 0x0;
  891. }
  892. size = sizeof(struct asd_ctrla_phy_settings);
  893. ps = &dflt_ps;
  894. }
  895. if (size == 0)
  896. goto out;
  897. err = -ENOMEM;
  898. el = kmalloc(size, GFP_KERNEL);
  899. if (!el) {
  900. ASD_DPRINTK("no mem for ctrla user settings section\n");
  901. goto out;
  902. }
  903. err = asd_read_flash_seg(asd_ha, (void *)el, offs, size);
  904. if (err) {
  905. ASD_DPRINTK("couldn't read ctrla phy settings section\n");
  906. goto out2;
  907. }
  908. err = -ENOENT;
  909. ps = asd_find_ll_by_id(el, 'h', 0xFF);
  910. if (!ps) {
  911. ASD_DPRINTK("couldn't find ctrla phy settings struct\n");
  912. goto out2;
  913. }
  914. err = asd_process_ctrla_phy_settings(asd_ha, ps);
  915. if (err) {
  916. ASD_DPRINTK("couldn't process ctrla phy settings\n");
  917. goto out2;
  918. }
  919. out2:
  920. kfree(el);
  921. out:
  922. return err;
  923. }
  924. /**
  925. * asd_read_flash - read flash memory
  926. * @asd_ha: pointer to the host adapter structure
  927. */
  928. int asd_read_flash(struct asd_ha_struct *asd_ha)
  929. {
  930. int err;
  931. struct asd_flash_dir *flash_dir;
  932. err = asd_flash_getid(asd_ha);
  933. if (err)
  934. return err;
  935. flash_dir = kmalloc(sizeof(*flash_dir), GFP_KERNEL);
  936. if (!flash_dir)
  937. return -ENOMEM;
  938. err = -ENOENT;
  939. if (!asd_find_flash_dir(asd_ha, flash_dir)) {
  940. ASD_DPRINTK("couldn't find flash directory\n");
  941. goto out;
  942. }
  943. if (le32_to_cpu(flash_dir->rev) != 2) {
  944. asd_printk("unsupported flash dir version:0x%x\n",
  945. le32_to_cpu(flash_dir->rev));
  946. goto out;
  947. }
  948. err = asd_process_ms(asd_ha, flash_dir);
  949. if (err) {
  950. ASD_DPRINTK("couldn't process manuf sector settings\n");
  951. goto out;
  952. }
  953. err = asd_process_ctrl_a_user(asd_ha, flash_dir);
  954. if (err) {
  955. ASD_DPRINTK("couldn't process CTRL-A user settings\n");
  956. goto out;
  957. }
  958. out:
  959. kfree(flash_dir);
  960. return err;
  961. }
  962. /**
  963. * asd_verify_flash_seg - verify data with flash memory
  964. * @asd_ha: pointer to the host adapter structure
  965. * @src: pointer to the source data to be verified
  966. * @dest_offset: offset from flash memory
  967. * @bytes_to_verify: total bytes to verify
  968. */
  969. int asd_verify_flash_seg(struct asd_ha_struct *asd_ha,
  970. const void *src, u32 dest_offset, u32 bytes_to_verify)
  971. {
  972. const u8 *src_buf;
  973. u8 flash_char;
  974. int err;
  975. u32 nv_offset, reg, i;
  976. reg = asd_ha->hw_prof.flash.bar;
  977. src_buf = NULL;
  978. err = FLASH_OK;
  979. nv_offset = dest_offset;
  980. src_buf = (const u8 *)src;
  981. for (i = 0; i < bytes_to_verify; i++) {
  982. flash_char = asd_read_reg_byte(asd_ha, reg + nv_offset + i);
  983. if (flash_char != src_buf[i]) {
  984. err = FAIL_VERIFY;
  985. break;
  986. }
  987. }
  988. return err;
  989. }
  990. /**
  991. * asd_write_flash_seg - write data into flash memory
  992. * @asd_ha: pointer to the host adapter structure
  993. * @src: pointer to the source data to be written
  994. * @dest_offset: offset from flash memory
  995. * @bytes_to_write: total bytes to write
  996. */
  997. int asd_write_flash_seg(struct asd_ha_struct *asd_ha,
  998. const void *src, u32 dest_offset, u32 bytes_to_write)
  999. {
  1000. const u8 *src_buf;
  1001. u32 nv_offset, reg, i;
  1002. int err;
  1003. reg = asd_ha->hw_prof.flash.bar;
  1004. src_buf = NULL;
  1005. err = asd_check_flash_type(asd_ha);
  1006. if (err) {
  1007. ASD_DPRINTK("couldn't find the type of flash. err=%d\n", err);
  1008. return err;
  1009. }
  1010. nv_offset = dest_offset;
  1011. err = asd_erase_nv_sector(asd_ha, nv_offset, bytes_to_write);
  1012. if (err) {
  1013. ASD_DPRINTK("Erase failed at offset:0x%x\n",
  1014. nv_offset);
  1015. return err;
  1016. }
  1017. err = asd_reset_flash(asd_ha);
  1018. if (err) {
  1019. ASD_DPRINTK("couldn't reset flash. err=%d\n", err);
  1020. return err;
  1021. }
  1022. src_buf = (const u8 *)src;
  1023. for (i = 0; i < bytes_to_write; i++) {
  1024. /* Setup program command sequence */
  1025. switch (asd_ha->hw_prof.flash.method) {
  1026. case FLASH_METHOD_A:
  1027. {
  1028. asd_write_reg_byte(asd_ha,
  1029. (reg + 0xAAA), 0xAA);
  1030. asd_write_reg_byte(asd_ha,
  1031. (reg + 0x555), 0x55);
  1032. asd_write_reg_byte(asd_ha,
  1033. (reg + 0xAAA), 0xA0);
  1034. asd_write_reg_byte(asd_ha,
  1035. (reg + nv_offset + i),
  1036. (*(src_buf + i)));
  1037. break;
  1038. }
  1039. case FLASH_METHOD_B:
  1040. {
  1041. asd_write_reg_byte(asd_ha,
  1042. (reg + 0x555), 0xAA);
  1043. asd_write_reg_byte(asd_ha,
  1044. (reg + 0x2AA), 0x55);
  1045. asd_write_reg_byte(asd_ha,
  1046. (reg + 0x555), 0xA0);
  1047. asd_write_reg_byte(asd_ha,
  1048. (reg + nv_offset + i),
  1049. (*(src_buf + i)));
  1050. break;
  1051. }
  1052. default:
  1053. break;
  1054. }
  1055. if (asd_chk_write_status(asd_ha,
  1056. (nv_offset + i), 0) != 0) {
  1057. ASD_DPRINTK("aicx: Write failed at offset:0x%x\n",
  1058. reg + nv_offset + i);
  1059. return FAIL_WRITE_FLASH;
  1060. }
  1061. }
  1062. err = asd_reset_flash(asd_ha);
  1063. if (err) {
  1064. ASD_DPRINTK("couldn't reset flash. err=%d\n", err);
  1065. return err;
  1066. }
  1067. return 0;
  1068. }
  1069. int asd_chk_write_status(struct asd_ha_struct *asd_ha,
  1070. u32 sector_addr, u8 erase_flag)
  1071. {
  1072. u32 reg;
  1073. u32 loop_cnt;
  1074. u8 nv_data1, nv_data2;
  1075. u8 toggle_bit1;
  1076. /*
  1077. * Read from DQ2 requires sector address
  1078. * while it's dont care for DQ6
  1079. */
  1080. reg = asd_ha->hw_prof.flash.bar;
  1081. for (loop_cnt = 0; loop_cnt < 50000; loop_cnt++) {
  1082. nv_data1 = asd_read_reg_byte(asd_ha, reg);
  1083. nv_data2 = asd_read_reg_byte(asd_ha, reg);
  1084. toggle_bit1 = ((nv_data1 & FLASH_STATUS_BIT_MASK_DQ6)
  1085. ^ (nv_data2 & FLASH_STATUS_BIT_MASK_DQ6));
  1086. if (toggle_bit1 == 0) {
  1087. return 0;
  1088. } else {
  1089. if (nv_data2 & FLASH_STATUS_BIT_MASK_DQ5) {
  1090. nv_data1 = asd_read_reg_byte(asd_ha,
  1091. reg);
  1092. nv_data2 = asd_read_reg_byte(asd_ha,
  1093. reg);
  1094. toggle_bit1 =
  1095. ((nv_data1 & FLASH_STATUS_BIT_MASK_DQ6)
  1096. ^ (nv_data2 & FLASH_STATUS_BIT_MASK_DQ6));
  1097. if (toggle_bit1 == 0)
  1098. return 0;
  1099. }
  1100. }
  1101. /*
  1102. * ERASE is a sector-by-sector operation and requires
  1103. * more time to finish while WRITE is byte-byte-byte
  1104. * operation and takes lesser time to finish.
  1105. *
  1106. * For some strange reason a reduced ERASE delay gives different
  1107. * behaviour across different spirit boards. Hence we set
  1108. * a optimum balance of 50mus for ERASE which works well
  1109. * across all boards.
  1110. */
  1111. if (erase_flag) {
  1112. udelay(FLASH_STATUS_ERASE_DELAY_COUNT);
  1113. } else {
  1114. udelay(FLASH_STATUS_WRITE_DELAY_COUNT);
  1115. }
  1116. }
  1117. return -1;
  1118. }
  1119. /**
  1120. * asd_hwi_erase_nv_sector - Erase the flash memory sectors.
  1121. * @asd_ha: pointer to the host adapter structure
  1122. * @flash_addr: pointer to offset from flash memory
  1123. * @size: total bytes to erase.
  1124. */
  1125. int asd_erase_nv_sector(struct asd_ha_struct *asd_ha, u32 flash_addr, u32 size)
  1126. {
  1127. u32 reg;
  1128. u32 sector_addr;
  1129. reg = asd_ha->hw_prof.flash.bar;
  1130. /* sector staring address */
  1131. sector_addr = flash_addr & FLASH_SECTOR_SIZE_MASK;
  1132. /*
  1133. * Erasing an flash sector needs to be done in six consecutive
  1134. * write cyles.
  1135. */
  1136. while (sector_addr < flash_addr+size) {
  1137. switch (asd_ha->hw_prof.flash.method) {
  1138. case FLASH_METHOD_A:
  1139. asd_write_reg_byte(asd_ha, (reg + 0xAAA), 0xAA);
  1140. asd_write_reg_byte(asd_ha, (reg + 0x555), 0x55);
  1141. asd_write_reg_byte(asd_ha, (reg + 0xAAA), 0x80);
  1142. asd_write_reg_byte(asd_ha, (reg + 0xAAA), 0xAA);
  1143. asd_write_reg_byte(asd_ha, (reg + 0x555), 0x55);
  1144. asd_write_reg_byte(asd_ha, (reg + sector_addr), 0x30);
  1145. break;
  1146. case FLASH_METHOD_B:
  1147. asd_write_reg_byte(asd_ha, (reg + 0x555), 0xAA);
  1148. asd_write_reg_byte(asd_ha, (reg + 0x2AA), 0x55);
  1149. asd_write_reg_byte(asd_ha, (reg + 0x555), 0x80);
  1150. asd_write_reg_byte(asd_ha, (reg + 0x555), 0xAA);
  1151. asd_write_reg_byte(asd_ha, (reg + 0x2AA), 0x55);
  1152. asd_write_reg_byte(asd_ha, (reg + sector_addr), 0x30);
  1153. break;
  1154. default:
  1155. break;
  1156. }
  1157. if (asd_chk_write_status(asd_ha, sector_addr, 1) != 0)
  1158. return FAIL_ERASE_FLASH;
  1159. sector_addr += FLASH_SECTOR_SIZE;
  1160. }
  1161. return 0;
  1162. }
  1163. int asd_check_flash_type(struct asd_ha_struct *asd_ha)
  1164. {
  1165. u8 manuf_id;
  1166. u8 dev_id;
  1167. u8 sec_prot;
  1168. u32 inc;
  1169. u32 reg;
  1170. int err;
  1171. /* get Flash memory base address */
  1172. reg = asd_ha->hw_prof.flash.bar;
  1173. /* Determine flash info */
  1174. err = asd_reset_flash(asd_ha);
  1175. if (err) {
  1176. ASD_DPRINTK("couldn't reset flash. err=%d\n", err);
  1177. return err;
  1178. }
  1179. asd_ha->hw_prof.flash.method = FLASH_METHOD_UNKNOWN;
  1180. asd_ha->hw_prof.flash.manuf = FLASH_MANUF_ID_UNKNOWN;
  1181. asd_ha->hw_prof.flash.dev_id = FLASH_DEV_ID_UNKNOWN;
  1182. /* Get flash info. This would most likely be AMD Am29LV family flash.
  1183. * First try the sequence for word mode. It is the same as for
  1184. * 008B (byte mode only), 160B (word mode) and 800D (word mode).
  1185. */
  1186. inc = asd_ha->hw_prof.flash.wide ? 2 : 1;
  1187. asd_write_reg_byte(asd_ha, reg + 0xAAA, 0xAA);
  1188. asd_write_reg_byte(asd_ha, reg + 0x555, 0x55);
  1189. asd_write_reg_byte(asd_ha, reg + 0xAAA, 0x90);
  1190. manuf_id = asd_read_reg_byte(asd_ha, reg);
  1191. dev_id = asd_read_reg_byte(asd_ha, reg + inc);
  1192. sec_prot = asd_read_reg_byte(asd_ha, reg + inc + inc);
  1193. /* Get out of autoselect mode. */
  1194. err = asd_reset_flash(asd_ha);
  1195. if (err) {
  1196. ASD_DPRINTK("couldn't reset flash. err=%d\n", err);
  1197. return err;
  1198. }
  1199. ASD_DPRINTK("Flash MethodA manuf_id(0x%x) dev_id(0x%x) "
  1200. "sec_prot(0x%x)\n", manuf_id, dev_id, sec_prot);
  1201. err = asd_reset_flash(asd_ha);
  1202. if (err != 0)
  1203. return err;
  1204. switch (manuf_id) {
  1205. case FLASH_MANUF_ID_AMD:
  1206. switch (sec_prot) {
  1207. case FLASH_DEV_ID_AM29LV800DT:
  1208. case FLASH_DEV_ID_AM29LV640MT:
  1209. case FLASH_DEV_ID_AM29F800B:
  1210. asd_ha->hw_prof.flash.method = FLASH_METHOD_A;
  1211. break;
  1212. default:
  1213. break;
  1214. }
  1215. break;
  1216. case FLASH_MANUF_ID_ST:
  1217. switch (sec_prot) {
  1218. case FLASH_DEV_ID_STM29W800DT:
  1219. case FLASH_DEV_ID_STM29LV640:
  1220. asd_ha->hw_prof.flash.method = FLASH_METHOD_A;
  1221. break;
  1222. default:
  1223. break;
  1224. }
  1225. break;
  1226. case FLASH_MANUF_ID_FUJITSU:
  1227. switch (sec_prot) {
  1228. case FLASH_DEV_ID_MBM29LV800TE:
  1229. case FLASH_DEV_ID_MBM29DL800TA:
  1230. asd_ha->hw_prof.flash.method = FLASH_METHOD_A;
  1231. break;
  1232. }
  1233. break;
  1234. case FLASH_MANUF_ID_MACRONIX:
  1235. switch (sec_prot) {
  1236. case FLASH_DEV_ID_MX29LV800BT:
  1237. asd_ha->hw_prof.flash.method = FLASH_METHOD_A;
  1238. break;
  1239. }
  1240. break;
  1241. }
  1242. if (asd_ha->hw_prof.flash.method == FLASH_METHOD_UNKNOWN) {
  1243. err = asd_reset_flash(asd_ha);
  1244. if (err) {
  1245. ASD_DPRINTK("couldn't reset flash. err=%d\n", err);
  1246. return err;
  1247. }
  1248. /* Issue Unlock sequence for AM29LV008BT */
  1249. asd_write_reg_byte(asd_ha, (reg + 0x555), 0xAA);
  1250. asd_write_reg_byte(asd_ha, (reg + 0x2AA), 0x55);
  1251. asd_write_reg_byte(asd_ha, (reg + 0x555), 0x90);
  1252. manuf_id = asd_read_reg_byte(asd_ha, reg);
  1253. dev_id = asd_read_reg_byte(asd_ha, reg + inc);
  1254. sec_prot = asd_read_reg_byte(asd_ha, reg + inc + inc);
  1255. ASD_DPRINTK("Flash MethodB manuf_id(0x%x) dev_id(0x%x) sec_prot"
  1256. "(0x%x)\n", manuf_id, dev_id, sec_prot);
  1257. err = asd_reset_flash(asd_ha);
  1258. if (err != 0) {
  1259. ASD_DPRINTK("couldn't reset flash. err=%d\n", err);
  1260. return err;
  1261. }
  1262. switch (manuf_id) {
  1263. case FLASH_MANUF_ID_AMD:
  1264. switch (dev_id) {
  1265. case FLASH_DEV_ID_AM29LV008BT:
  1266. asd_ha->hw_prof.flash.method = FLASH_METHOD_B;
  1267. break;
  1268. default:
  1269. break;
  1270. }
  1271. break;
  1272. case FLASH_MANUF_ID_ST:
  1273. switch (dev_id) {
  1274. case FLASH_DEV_ID_STM29008:
  1275. asd_ha->hw_prof.flash.method = FLASH_METHOD_B;
  1276. break;
  1277. default:
  1278. break;
  1279. }
  1280. break;
  1281. case FLASH_MANUF_ID_FUJITSU:
  1282. switch (dev_id) {
  1283. case FLASH_DEV_ID_MBM29LV008TA:
  1284. asd_ha->hw_prof.flash.method = FLASH_METHOD_B;
  1285. break;
  1286. }
  1287. break;
  1288. case FLASH_MANUF_ID_INTEL:
  1289. switch (dev_id) {
  1290. case FLASH_DEV_ID_I28LV00TAT:
  1291. asd_ha->hw_prof.flash.method = FLASH_METHOD_B;
  1292. break;
  1293. }
  1294. break;
  1295. case FLASH_MANUF_ID_MACRONIX:
  1296. switch (dev_id) {
  1297. case FLASH_DEV_ID_I28LV00TAT:
  1298. asd_ha->hw_prof.flash.method = FLASH_METHOD_B;
  1299. break;
  1300. }
  1301. break;
  1302. default:
  1303. return FAIL_FIND_FLASH_ID;
  1304. }
  1305. }
  1306. if (asd_ha->hw_prof.flash.method == FLASH_METHOD_UNKNOWN)
  1307. return FAIL_FIND_FLASH_ID;
  1308. asd_ha->hw_prof.flash.manuf = manuf_id;
  1309. asd_ha->hw_prof.flash.dev_id = dev_id;
  1310. asd_ha->hw_prof.flash.sec_prot = sec_prot;
  1311. return 0;
  1312. }